1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7&csi2_dphy_hw { 8 status = "okay"; 9}; 10 11&csi2_dphy0 { 12 status = "okay"; 13 14 ports { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 port@0 { 19 reg = <0>; 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 csi_dphy_input1: endpoint@0 { 24 reg = <0>; 25 remote-endpoint = <&sc3336_out>; 26 data-lanes = <1 2>; 27 }; 28 csi_dphy_input2: endpoint@1 { 29 reg = <1>; 30 remote-endpoint = <&sc4336_out>; 31 data-lanes = <1 2>; 32 }; 33 csi_dphy_input3: endpoint@2 { 34 reg = <2>; 35 remote-endpoint = <&os04a10_out>; 36 data-lanes = <1 2>; 37 }; 38 }; 39 40 port@1 { 41 reg = <1>; 42 #address-cells = <1>; 43 #size-cells = <0>; 44 45 csi_dphy_output: endpoint@0 { 46 reg = <0>; 47 remote-endpoint = <&mipi_csi2_input>; 48 }; 49 }; 50 }; 51}; 52 53&i2c4 { 54 status = "okay"; 55 clock-frequency = <400000>; 56 pinctrl-names = "default"; 57 pinctrl-0 = <&i2c4m2_xfer>; 58 59 sc3336: sc3336@30 { 60 compatible = "smartsens,sc3336"; 61 status = "okay"; 62 reg = <0x30>; 63 clocks = <&cru MCLK_REF_MIPI0>; 64 clock-names = "xvclk"; 65 reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; 66 pwdn-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; 67 pinctrl-names = "default"; 68 pinctrl-0 = <&mipi_refclk_out0>; 69 rockchip,camera-module-index = <0>; 70 rockchip,camera-module-facing = "back"; 71 rockchip,camera-module-name = "CMK-OT2119-PC1"; 72 rockchip,camera-module-lens-name = "30IRC-F16"; 73 port { 74 sc3336_out: endpoint { 75 remote-endpoint = <&csi_dphy_input1>; 76 data-lanes = <1 2>; 77 }; 78 }; 79 }; 80 81 sc4336: sc4336@30 { 82 compatible = "smartsens,sc4336"; 83 status = "okay"; 84 reg = <0x30>; 85 clocks = <&cru MCLK_REF_MIPI0>; 86 clock-names = "xvclk"; 87 reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; 88 pwdn-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; 89 pinctrl-names = "default"; 90 pinctrl-0 = <&mipi_refclk_out0>; 91 rockchip,camera-module-index = <0>; 92 rockchip,camera-module-facing = "back"; 93 rockchip,camera-module-name = "OT01"; 94 rockchip,camera-module-lens-name = "40IRC_F16"; 95 port { 96 sc4336_out: endpoint { 97 remote-endpoint = <&csi_dphy_input2>; 98 data-lanes = <1 2>; 99 }; 100 }; 101 }; 102 103 os04a10: os04a10@36 { 104 compatible = "ovti,os04a10"; 105 status = "okay"; 106 reg = <0x36>; 107 clocks = <&cru MCLK_REF_MIPI0>; 108 clock-names = "xvclk"; 109 reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; 110 pwdn-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; 111 pinctrl-names = "default"; 112 pinctrl-0 = <&mipi_refclk_out0>; 113 rockchip,camera-module-index = <0>; 114 rockchip,camera-module-facing = "back"; 115 rockchip,camera-module-name = "408b170b9d8a"; 116 rockchip,camera-module-lens-name = "40IRC-F10"; 117 port { 118 os04a10_out: endpoint { 119 remote-endpoint = <&csi_dphy_input3>; 120 data-lanes = <1 2>; 121 }; 122 }; 123 }; 124}; 125 126&mipi0_csi2 { 127 status = "okay"; 128 129 ports { 130 #address-cells = <1>; 131 #size-cells = <0>; 132 133 port@0 { 134 reg = <0>; 135 #address-cells = <1>; 136 #size-cells = <0>; 137 138 mipi_csi2_input: endpoint@1 { 139 reg = <1>; 140 remote-endpoint = <&csi_dphy_output>; 141 }; 142 }; 143 144 port@1 { 145 reg = <1>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 149 mipi_csi2_output: endpoint@0 { 150 reg = <0>; 151 remote-endpoint = <&cif_mipi_in>; 152 }; 153 }; 154 }; 155}; 156 157&rkcif { 158 status = "okay"; 159}; 160 161&rkcif_mipi_lvds { 162 status = "okay"; 163 164 pinctrl-names = "default"; 165 pinctrl-0 = <&mipi_pins>; 166 port { 167 /* MIPI CSI-2 endpoint */ 168 cif_mipi_in: endpoint { 169 remote-endpoint = <&mipi_csi2_output>; 170 }; 171 }; 172}; 173 174&rkcif_mipi_lvds_sditf { 175 status = "okay"; 176 177 port { 178 /* MIPI CSI-2 endpoint */ 179 mipi_lvds_sditf: endpoint { 180 remote-endpoint = <&isp_in>; 181 }; 182 }; 183}; 184 185&rkisp { 186 status = "okay"; 187}; 188 189&rkisp_vir0 { 190 status = "okay"; 191 192 port@0 { 193 isp_in: endpoint { 194 remote-endpoint = <&mipi_lvds_sditf>; 195 }; 196 }; 197}; 198 199