1 /******************************************************************************
2 *
3 * Copyright(c) 2019 - 2021 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _RTL8852BS_HALINIT_C_
16 #include "../../hal_headers.h"
17 #include "../rtl8852b_hal.h"
18 #include "rtl8852bs_halinit.h"
19
_hal_pre_init_8852bs(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info,struct hal_init_info_t * init_52bs)20 static void _hal_pre_init_8852bs(struct rtw_phl_com_t *phl_com,
21 struct hal_info_t *hal_info,
22 struct hal_init_info_t *init_52bs)
23 {
24 struct mac_ax_trx_info *trx_info = &init_52bs->trx_info;
25 struct mac_ax_host_rpr_cfg *rpr_cfg = (struct mac_ax_host_rpr_cfg *)hal_info->rpr_cfg;
26 /*struct mac_ax_intf_info *intf_info = &init_52bs->intf_info;*/
27
28 if (true == phl_com->dev_cap.tx_mu_ru)
29 trx_info->trx_mode = MAC_AX_TRX_SW_MODE;
30 else
31 trx_info->trx_mode = MAC_AX_TRX_HW_MODE;
32 trx_info->qta_mode = MAC_AX_QTA_SCC_TURBO;
33
34 #ifdef RTW_WKARD_LAMODE
35 PHL_INFO("%s : la_mode %d\n", __func__, phl_com->dev_cap.la_mode);
36 if (phl_com->dev_cap.la_mode)
37 trx_info->qta_mode = MAC_AX_QTA_LAMODE;
38 #endif
39
40 if (phl_com->dev_cap.rpq_agg_num) {
41 rpr_cfg->agg_def = 0;
42 rpr_cfg->agg = phl_com->dev_cap.rpq_agg_num;
43 } else {
44 rpr_cfg->agg_def = 1;
45 }
46
47 rpr_cfg->tmr_def = 1;
48 rpr_cfg->txok_en = MAC_AX_FUNC_DEF;
49 rpr_cfg->rty_lmt_en = MAC_AX_FUNC_DEF;
50 rpr_cfg->lft_drop_en = MAC_AX_FUNC_DEF;
51 rpr_cfg->macid_drop_en = MAC_AX_FUNC_DEF;
52
53 trx_info->rpr_cfg = rpr_cfg;
54
55 init_52bs->ic_name = "rtl8852bs";
56 }
57
init_hal_spec_8852bs(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal)58 void init_hal_spec_8852bs(struct rtw_phl_com_t *phl_com,
59 struct hal_info_t *hal)
60 {
61 struct bus_hw_cap_t *bus_hw = &hal->hal_com->bus_hw_cap;
62
63 init_hal_spec_8852b(phl_com, hal);
64 phl_com->dev_cap.hw_sup_flags |= HW_SUP_SDIO_MULTI_FUN;
65
66 /* default TX/RX resouce setting */
67 bus_hw->tx_buf_size = 32768; /* 32KB */
68 bus_hw->tx_buf_num = 8;
69 bus_hw->tx_mgnt_buf_size = 3096; /* 3KB */
70 bus_hw->tx_mgnt_buf_num = 3;
71 bus_hw->rx_buf_size = 90112; /* 88KB */
72 bus_hw->rx_buf_num = 8;
73
74 hal->hal_com->dev_hw_cap.ps_cap.lps_pause_tx = true;
75 }
76
hal_get_efuse_8852bs(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info)77 enum rtw_hal_status hal_get_efuse_8852bs(struct rtw_phl_com_t *phl_com,
78 struct hal_info_t *hal_info)
79 {
80 struct hal_init_info_t init_52bs;
81
82 _os_mem_set(hal_to_drvpriv(hal_info), &init_52bs, 0, sizeof(init_52bs));
83 _hal_pre_init_8852bs(phl_com, hal_info, &init_52bs);
84
85 return hal_get_efuse_8852b(phl_com, hal_info, &init_52bs);
86 }
87
hal_init_8852bs(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info)88 enum rtw_hal_status hal_init_8852bs(struct rtw_phl_com_t *phl_com,
89 struct hal_info_t *hal_info)
90 {
91 enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
92
93 /* allocate memory for hal */
94 hal_info->rpr_cfg = _os_mem_alloc(phlcom_to_drvpriv(phl_com),
95 sizeof(struct mac_ax_host_rpr_cfg));
96 if (hal_info->rpr_cfg == NULL) {
97 hal_status = RTW_HAL_STATUS_RESOURCE;
98 PHL_ERR("%s: alloc rpr_cfg failed\n", __func__);
99 goto error_rpr_cfg;
100 }
101
102 hal_status = RTW_HAL_STATUS_SUCCESS;
103
104 error_rpr_cfg:
105 return hal_status;
106 }
107
hal_deinit_8852bs(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info)108 void hal_deinit_8852bs(struct rtw_phl_com_t *phl_com,
109 struct hal_info_t *hal_info)
110 {
111 /* free memory for hal */
112 _os_mem_free(phlcom_to_drvpriv(phl_com),
113 hal_info->rpr_cfg,
114 sizeof(struct mac_ax_host_rpr_cfg));
115 }
116
hal_start_8852bs(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info)117 enum rtw_hal_status hal_start_8852bs(struct rtw_phl_com_t *phl_com,
118 struct hal_info_t *hal_info)
119 {
120 struct hal_init_info_t init_52bs;
121
122 _os_mem_set(hal_to_drvpriv(hal_info), &init_52bs, 0, sizeof(init_52bs));
123 _hal_pre_init_8852bs(phl_com, hal_info, &init_52bs);
124
125 return hal_start_8852b(phl_com, hal_info, &init_52bs);
126 }
127
hal_stop_8852bs(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal)128 enum rtw_hal_status hal_stop_8852bs(struct rtw_phl_com_t *phl_com,
129 struct hal_info_t *hal)
130 {
131 enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
132
133 hal_status = hal_stop_8852b(phl_com, hal);
134
135 #if 0
136 #ifdef CONFIG_FWLPS_IN_IPS
137 if (_SUCCESS == rtl8852bs_fw_ips_deinit(adapter))
138 return _SUCCESS;
139 #endif
140
141 return hal_deinit_rtl8852b(adapter);
142 #endif
143 return hal_status;
144 }
145
146 #ifdef CONFIG_WOWLAN
147 enum rtw_hal_status
hal_wow_init_8852bs(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info,struct rtw_phl_stainfo_t * sta)148 hal_wow_init_8852bs(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info,
149 struct rtw_phl_stainfo_t *sta)
150 {
151 struct hal_init_info_t init_52bs;
152 struct mac_ax_trx_info *trx_info = &init_52bs.trx_info;
153
154 _os_mem_set( hal_to_drvpriv(hal_info), &init_52bs, 0, sizeof(init_52bs));
155 if (true == phl_com->dev_cap.tx_mu_ru)
156 trx_info->trx_mode = MAC_AX_TRX_SW_MODE;
157 else
158 trx_info->trx_mode = MAC_AX_TRX_HW_MODE;
159 trx_info->qta_mode = MAC_AX_QTA_SCC_TURBO;
160 init_52bs.ic_name = "rtl8852bs";
161
162 return hal_wow_init_8852b(phl_com, hal_info, sta, &init_52bs);
163 }
164
165 enum rtw_hal_status
hal_wow_deinit_8852bs(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info,struct rtw_phl_stainfo_t * sta)166 hal_wow_deinit_8852bs(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info,
167 struct rtw_phl_stainfo_t *sta)
168 {
169 struct hal_init_info_t init_52bs;
170 struct mac_ax_trx_info *trx_info = &init_52bs.trx_info;
171
172 _os_mem_set( hal_to_drvpriv(hal_info), &init_52bs, 0, sizeof(init_52bs));
173 if (true == phl_com->dev_cap.tx_mu_ru)
174 trx_info->trx_mode = MAC_AX_TRX_SW_MODE;
175 else
176 trx_info->trx_mode = MAC_AX_TRX_HW_MODE;
177 trx_info->qta_mode = MAC_AX_QTA_SCC_TURBO;
178 init_52bs.ic_name = "rtl8852bs";
179
180 return hal_wow_deinit_8852b(phl_com, hal_info, sta, &init_52bs);
181 }
182 #endif /* CONFIG_WOWLAN */
183
init_default_value_8852bs(struct hal_info_t * hal,struct hal_intr_mask_cfg * cfg)184 void init_default_value_8852bs(struct hal_info_t *hal, struct hal_intr_mask_cfg *cfg)
185 {
186 struct rtw_hal_com_t *hal_com = hal->hal_com;
187
188 init_default_value_8852b(hal);
189
190 hal_com->int_mask_default = (u32)(
191 #if 0
192 B_AX_SDIO_HC10ISR_IND_EN |
193 B_AX_SDIO_HC00ISR_IND_EN |
194 B_AX_SDIO_HD1ISR_IND_EN |
195 B_AX_SDIO_HD0ISR_IND_EN |
196 #endif
197 B_AX_SDIO_HS0ISR_IND_EN |
198 #if 0
199 B_AX_SDIO_BT_INT_EN |
200 B_AX_SDIO_AVAL_INT_EN |
201 #endif
202 B_AX_RX_REQUEST_INT_EN |
203 0);
204
205 hal_com->intr.halt_c2h_int.val_default = (u32)(
206 (cfg->halt_c2h_en == 1 ? B_AX_HALT_C2H_INT_EN : 0) |
207 0);
208
209 hal_com->intr.watchdog_timer_int.val_default = (u32)(
210 (cfg->wdt_en == 1 ? B_AX_WDT_PTFM_INT_EN : 0) |
211 0);
212
213 hal_com->int_mask = hal_com->int_mask_default;
214
215 hal_com->intr.halt_c2h_int.val_mask = hal_com->intr.halt_c2h_int.val_default;
216 hal_com->intr.watchdog_timer_int.val_mask = hal_com->intr.watchdog_timer_int.val_default;
217
218 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
219 "Initialize interrupt mask: 0x%08lX, 0x%08x\n",
220 hal_com->int_mask, hal_com->intr.halt_c2h_int.val_mask);
221 }
222
hal_hci_cfg_8852bs(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal,struct rtw_ic_info * ic_info)223 u32 hal_hci_cfg_8852bs(struct rtw_phl_com_t *phl_com,
224 struct hal_info_t *hal, struct rtw_ic_info *ic_info)
225 {
226 /*struct rtw_hal_com_t *hal_com = hal->hal_com;*/
227
228 /*sync SDIO Bus-info from os*/
229 PHL_INFO("%s ===>\n", __func__);
230 PHL_INFO("sdio clock: %d Hz\n", ic_info->sdio_info.clock);
231 PHL_INFO("sdio V3 :%s\n", (ic_info->sdio_info.sd3_bus_mode) ? "YES" : "NO");
232
233
234 rtw_hal_mac_sdio_cfg(phl_com, hal, ic_info);
235
236 return RTW_HAL_STATUS_SUCCESS;
237 }
238
_hal_config_int_8852bs(struct hal_info_t * hal,enum rtw_hal_config_int hal_int_mode)239 static void _hal_config_int_8852bs(struct hal_info_t *hal, enum rtw_hal_config_int hal_int_mode)
240 {
241 struct rtw_hal_com_t *hal_com = hal->hal_com;
242 long bit_of_rx_req = 0;
243
244 switch (hal_int_mode) {
245 case RTW_HAL_EN_DEFAULT_INT:
246 hal_write32(hal_com, R_AX_SDIO_HIMR, hal_com->int_mask_default);
247 hal_write32(hal_com, R_AX_HIMR0, hal_com->intr.halt_c2h_int.val_default);
248 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
249 "Enabled interrupt: 0x%04X=%08X, 0x%04X=%08X\n",
250 R_AX_SDIO_HIMR, hal_read32(hal_com, R_AX_SDIO_HIMR),
251 R_AX_HIMR0, hal_read32(hal_com, R_AX_HIMR0));
252 break;
253 case RTW_HAL_DIS_DEFAULT_INT:
254 hal_write32(hal_com, R_AX_SDIO_HIMR, 0);
255 hal_write32(hal_com, R_AX_HIMR0, 0);
256 break;
257 case RTW_HAL_STOP_RX_INT:
258 #ifndef CONFIG_PHL_SDIO_READ_RXFF_IN_INT
259 if (_os_test_and_clear_bit(bit_of_rx_req, &hal_com->int_mask))
260 hal_write32(hal_com, R_AX_SDIO_HIMR, (u32)hal_com->int_mask);
261 #endif
262 break;
263 case RTW_HAL_RESUME_RX_INT:
264 #ifndef CONFIG_PHL_SDIO_READ_RXFF_IN_INT
265 if (!_os_test_and_set_bit(bit_of_rx_req, &hal_com->int_mask))
266 hal_write32(hal_com, R_AX_SDIO_HIMR, (u32)hal_com->int_mask);
267 #endif
268 break;
269 case RTW_HAL_SER_HANDSHAKE_MODE:
270 hal_write32(hal_com, R_AX_SDIO_HIMR, B_AX_SDIO_HS0ISR_IND_EN);
271 hal_write32(hal_com, R_AX_HIMR0, B_AX_HALT_C2H_INT_EN);
272 break;
273 case RTW_HAL_EN_HCI_INT:
274 hal_write32(hal_com, R_AX_SDIO_HIMR, hal_com->int_mask_default);
275 break;
276 case RTW_HAL_DIS_HCI_INT:
277 hal_write32(hal_com, R_AX_SDIO_HIMR, 0);
278 break;
279 default:
280 break;
281 }
282 }
283
hal_config_int_8852bs(struct hal_info_t * hal,enum rtw_phl_config_int int_mode)284 void hal_config_int_8852bs(struct hal_info_t *hal, enum rtw_phl_config_int int_mode)
285 {
286 u8 hal_int_mode = RTW_HAL_CONFIG_INT_MAX;
287
288 switch (int_mode) {
289 case RTW_PHL_STOP_RX_INT:
290 hal_int_mode = RTW_HAL_STOP_RX_INT;
291 break;
292 case RTW_PHL_RESUME_RX_INT:
293 hal_int_mode = RTW_HAL_RESUME_RX_INT;
294 break;
295 case RTW_PHL_SER_HANDSHAKE_MODE:
296 hal_int_mode = RTW_HAL_SER_HANDSHAKE_MODE;
297 break;
298 case RTW_PHL_EN_HCI_INT:
299 hal_int_mode = RTW_HAL_EN_HCI_INT;
300 break;
301 case RTW_PHL_DIS_HCI_INT:
302 hal_int_mode = RTW_HAL_DIS_HCI_INT;
303 break;
304 default:
305 PHL_ERR("%s: int_mode %d can't be supported!\n", __func__, int_mode);
306 break;
307 }
308
309 if (hal_int_mode != RTW_HAL_CONFIG_INT_MAX)
310 _hal_config_int_8852bs(hal, hal_int_mode);
311 }
312
hal_enable_int_8852bs(struct hal_info_t * hal)313 void hal_enable_int_8852bs(struct hal_info_t *hal)
314 {
315 _hal_config_int_8852bs(hal, RTW_HAL_EN_DEFAULT_INT);
316 }
317
hal_disable_int_8852bs(struct hal_info_t * hal)318 void hal_disable_int_8852bs(struct hal_info_t *hal)
319 {
320 _hal_config_int_8852bs(hal, RTW_HAL_DIS_DEFAULT_INT);
321 }
322
hal_recognize_int_8852bs(struct hal_info_t * hal)323 bool hal_recognize_int_8852bs(struct hal_info_t *hal)
324 {
325 return true;
326 }
327
hal_recognize_halt_c2h_int_8852bs(struct hal_info_t * hal)328 bool hal_recognize_halt_c2h_int_8852bs(struct hal_info_t *hal)
329 {
330 struct rtw_hal_com_t *hal_com = hal->hal_com;
331 struct hal_halt_c2h_int *g_hisr;
332
333 g_hisr = &hal_com->intr.halt_c2h_int;
334 g_hisr->intr = hal_read32(hal_com, R_AX_HISR0);
335 g_hisr->intr &= g_hisr->val_mask;
336 /* clear interrupt */
337 if (g_hisr->intr)
338 hal_write32(hal_com, R_AX_HISR0, g_hisr->intr);
339 /* check halt c2h */
340 if (g_hisr->intr & B_AX_HALT_C2H_INT_EN)
341 return true;
342
343 return false;
344 }
345
hal_clear_interrupt_8852bs(struct hal_info_t * hal)346 void hal_clear_interrupt_8852bs(struct hal_info_t *hal)
347 {
348 struct rtw_hal_com_t *hal_com = hal->hal_com;
349 u32 hisr; /* SDIO hisr */
350 u32 g_hisr; /* general hisr */
351
352
353 /* clear SDIO HISR */
354 hisr = hal_read32(hal_com, R_AX_SDIO_HISR);
355 hal_write32(hal_com, R_AX_SDIO_HISR, hisr);
356
357 /* clear general HISR */
358 g_hisr = hal_read32(hal_com, R_AX_HISR0);
359 hal_write32(hal_com, R_AX_HISR0, g_hisr);
360 }
361
362 #define R_AX_SDIO_HISR_W1C_MASK B_AX_SDIO_BT_INT
363
hal_int_hdler_8852bs(struct hal_info_t * hal)364 u32 hal_int_hdler_8852bs(struct hal_info_t *hal)
365 {
366 struct rtw_hal_com_t *hal_com = hal->hal_com;
367 u32 hisr; /* SDIO hisr */
368 u32 w1c; /* write 1 clear */
369 u32 phl_int = 0;
370
371
372 hisr = hal_read32(hal_com, R_AX_SDIO_HISR);
373 hisr &= hal_com->int_mask;
374 w1c = hisr & R_AX_SDIO_HISR_W1C_MASK;
375 /* clear interrupt */
376 if (w1c)
377 hal_write32(hal_com, R_AX_SDIO_HISR, w1c);
378 /* check interrupt */
379 if (hisr & B_AX_RX_REQUEST_INT_EN){
380 /* disable rx interrupt */
381 _hal_config_int_8852bs(hal, RTW_HAL_STOP_RX_INT);
382 phl_int |= BIT1;
383 }
384 if (hisr & B_AX_SDIO_AVAL_INT)
385 phl_int |= BIT2;
386
387 /* Check General interrupt */
388 if (hisr & B_AX_SDIO_HS0ISR_IND_EN) {
389 _hal_config_int_8852bs(hal, RTW_HAL_DIS_HCI_INT);
390 phl_int |= BIT6;
391 }
392
393 return phl_int;
394 }
395
396 enum rtw_hal_status
hal_mp_init_8852bs(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info)397 hal_mp_init_8852bs(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info)
398 {
399 enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
400 struct hal_init_info_t init_52bs;
401
402 FUNCIN_WSTS(hal_status);
403
404 _os_mem_set(hal_to_drvpriv(hal_info), &init_52bs, 0, sizeof(init_52bs));
405
406 init_52bs.ic_name = "rtl8852bs";
407
408 hal_status = hal_mp_init_8852b(phl_com, hal_info, &init_52bs);
409
410 FUNCOUT_WSTS(hal_status);
411 return hal_status;
412 }
413
414 enum rtw_hal_status
hal_mp_deinit_8852bs(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info)415 hal_mp_deinit_8852bs(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info)
416 {
417 enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
418 struct hal_init_info_t init_52bs;
419
420 FUNCIN_WSTS(hal_status);
421
422 _os_mem_set(hal_to_drvpriv(hal_info), &init_52bs, 0, sizeof(init_52bs));
423
424 init_52bs.ic_name = "rtl8852bs";
425
426 hal_status = hal_mp_deinit_8852b(phl_com, hal_info, &init_52bs);
427
428 if (RTW_HAL_STATUS_SUCCESS != hal_status) {
429
430 PHL_ERR("hal_mp_deinit_8852bs: status = %u\n", hal_status);
431 return hal_status;
432 }
433
434 FUNCOUT_WSTS(hal_status);
435 return hal_status;
436 }
437
438
439