1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 #ifndef __INC_PHYDM_API_H_8822C__ 26 #define __INC_PHYDM_API_H_8822C__ 27 28 #if (RTL8822C_SUPPORT) 29 /*2021.02.05: Let the auto_nbi_detect th be 0x1 due to technicolor issue*/ 30 #define PHY_CONFIG_VERSION_8822C "1.8.9" 31 /*#define CONFIG_TXAGC_DEBUG_8822C*/ 32 33 #define INVALID_RF_DATA 0xffffffff 34 #define INVALID_TXAGC_DATA 0xff 35 #define L_BND_DEFAULT_8822C 0xd 36 37 #define config_phydm_read_rf_check_8822c(data) ((data) != INVALID_RF_DATA) 38 #define config_phydm_read_txagc_check_8822c(data) ((data) != INVALID_TXAGC_DATA) 39 40 enum agc_tab_sel_8822c { 41 OFDM_2G_BW40_8822C = 0, 42 OFDM_5G_LOW_BAND_8822C = 1, 43 OFDM_5G_MID_BAND_8822C = 2, 44 OFDM_5G_HIGH_BAND_8822C = 3, 45 CCK_BW40_8822C = 4, 46 CCK_BW20_8822C = 5, 47 OFDM_2G_BW20_8822C = 6 48 }; 49 50 struct txagc_table_8822c { 51 u8 ref_pow_cck[2]; 52 u8 ref_pow_ofdm[2]; 53 s8 diff_t[NUM_RATE_AC_2SS]; /*by rate differential table*/ 54 }; 55 56 struct tx_path_en_8822c { 57 u8 tx_path_en_ofdm_1sts; 58 u8 tx_path_en_ofdm_2sts; 59 u8 tx_path_en_cck; 60 boolean is_path_ctrl_by_bb_reg; 61 boolean stop_path_div; 62 }; 63 64 struct rx_path_en_8822c { 65 u8 rx_path_en_ofdm; 66 u8 rx_path_en_cck; 67 }; 68 69 boolean phydm_chk_pkg_set_valid_8822c(struct dm_struct *dm, 70 u8 ver_bb, u8 ver_rf); 71 72 u32 config_phydm_read_rf_reg_8822c(struct dm_struct *dm, enum rf_path path, 73 u32 reg_addr, u32 bit_mask); 74 75 boolean config_phydm_write_rf_reg_8822c(struct dm_struct *dm, enum rf_path path, 76 u32 reg_addr, u32 bit_mask, u32 data); 77 78 boolean phydm_write_txagc_1byte_8822c(struct dm_struct *dm, u32 pw_idx, 79 u8 hw_rate); 80 81 boolean config_phydm_write_txagc_ref_8822c(struct dm_struct *dm, u8 power_index, 82 enum rf_path path, 83 enum PDM_RATE_TYPE rate_type); 84 85 boolean config_phydm_write_txagc_diff_8822c(struct dm_struct *dm, 86 s8 power_index1, s8 power_index2, 87 s8 power_index3, s8 power_index4, 88 u8 hw_rate); 89 90 #ifdef CONFIG_TXAGC_DEBUG_8822C 91 void phydm_txagc_tab_buff_show_8822c(struct dm_struct *dm); 92 #endif 93 94 s8 config_phydm_read_txagc_diff_8822c(struct dm_struct *dm, u8 hw_rate); 95 96 u8 config_phydm_read_txagc_8822c(struct dm_struct *dm, enum rf_path path, 97 u8 hw_rate, enum PDM_RATE_TYPE rate_type); 98 99 void phydm_get_tx_path_en_setting_8822c(struct dm_struct *dm, 100 struct tx_path_en_8822c *path); 101 102 void phydm_get_rx_path_en_setting_8822c(struct dm_struct *dm, 103 struct rx_path_en_8822c *path); 104 105 void phydm_config_tx_path_8822c(struct dm_struct *dm, enum bb_path tx_path_2ss, 106 enum bb_path tx_path_sel_1ss, 107 enum bb_path tx_path_sel_cck); 108 109 boolean config_phydm_trx_mode_8822c(struct dm_struct *dm, 110 enum bb_path tx_path_en, 111 enum bb_path rx_path, 112 enum bb_path tx_path_sel_1ss); 113 114 boolean config_phydm_switch_band_8822c(struct dm_struct *dm, u8 central_ch); 115 116 boolean config_phydm_switch_channel_8822c(struct dm_struct *dm, u8 central_ch); 117 118 boolean config_phydm_switch_bandwidth_8822c(struct dm_struct *dm, u8 pri_ch, 119 enum channel_width bw); 120 121 boolean config_phydm_switch_channel_bw_8822c(struct dm_struct *dm, 122 u8 central_ch, u8 primary_ch_idx, 123 enum channel_width bandwidth); 124 125 void phydm_i_only_setting_8822c(struct dm_struct *dm, boolean en_i_only, 126 boolean en_before_cca); 127 128 boolean phydm_1rcca_setting_8822c(struct dm_struct *dm, boolean en_1rcca); 129 130 void phydm_invld_pkt_setting_8822c(struct dm_struct *dm, boolean en_invld_pkt); 131 132 void phydm_cck_gi_bound_8822c(struct dm_struct *dm); 133 134 void phydm_ch_smooth_setting_8822c(struct dm_struct *dm, boolean en_ch_smooth); 135 136 u16 phydm_get_dis_dpd_by_rate_8822c(struct dm_struct *dm); 137 138 void phydm_set_auto_nbi_8822c(struct dm_struct *dm, boolean en_auto_nbi); 139 140 boolean config_phydm_parameter_init_8822c(struct dm_struct *dm, 141 enum odm_parameter_init type); 142 143 boolean phydm_chk_bb_state_idle_8822c(struct dm_struct *dm); 144 145 u16 phydm_get_gpio_setting_by_rfe_ctrl_8822c(struct dm_struct *dm); 146 147 #if CONFIG_POWERSAVING 148 boolean phydm_8822c_lps(struct dm_struct *dm, boolean enable_lps); 149 #endif /* #if CONFIG_POWERSAVING */ 150 151 void config_phydm_set_txagc_to_hw_8822c(struct dm_struct *dm); 152 153 boolean config_phydm_write_txagc_8822c(struct dm_struct *dm, u32 power_index, 154 enum rf_path path, u8 hw_rate); 155 156 void phydm_set_txagc_by_table_8822c(struct dm_struct *dm, 157 struct txagc_table_8822c *tab); 158 159 void phydm_get_txagc_ref_and_diff_8822c(struct dm_struct *dm, 160 u8 txagc_buff[2][NUM_RATE_AC_2SS], 161 u16 length, 162 struct txagc_table_8822c *tab); 163 #endif /* RTL8822C_SUPPORT */ 164 #endif /* __INC_PHYDM_API_H_8822C__ */ 165