1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * rt5651.c -- RT5651 ALSA SoC audio codec driver
4 *
5 * Copyright 2014 Realtek Semiconductor Corp.
6 * Author: Bard Liao <bardliao@realtek.com>
7 */
8
9 #include <linux/module.h>
10 #include <linux/init.h>
11 #include <linux/delay.h>
12 #include <linux/pm.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/i2c.h>
15 #include <linux/regmap.h>
16 #include <linux/platform_device.h>
17 #include <linux/spi/spi.h>
18 #include <linux/acpi.h>
19 #include <sound/core.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/soc.h>
23 #include <sound/soc-dapm.h>
24 #include <sound/initval.h>
25 #include <sound/tlv.h>
26 #include <sound/jack.h>
27 #include <linux/of_gpio.h>
28 #include <linux/gpio.h>
29 #include <linux/clk.h>
30
31 #include "rl6231.h"
32 #include "rt5651.h"
33
34 #define RT5651_DEVICE_ID_VALUE 0x6281
35
36 #define RT5651_PR_RANGE_BASE (0xff + 1)
37 #define RT5651_PR_SPACING 0x100
38
39 #define RT5651_PR_BASE (RT5651_PR_RANGE_BASE + (0 * RT5651_PR_SPACING))
40
41 static const struct regmap_range_cfg rt5651_ranges[] = {
42 { .name = "PR", .range_min = RT5651_PR_BASE,
43 .range_max = RT5651_PR_BASE + 0xb4,
44 .selector_reg = RT5651_PRIV_INDEX,
45 .selector_mask = 0xff,
46 .selector_shift = 0x0,
47 .window_start = RT5651_PRIV_DATA,
48 .window_len = 0x1, },
49 };
50
51 static const struct reg_sequence init_list[] = {
52 {RT5651_PR_BASE + 0x3d, 0x3e00},
53 };
54
55 static const struct reg_default rt5651_reg[] = {
56 { 0x00, 0x0000 },
57 { 0x02, 0xc8c8 },
58 { 0x03, 0xc8c8 },
59 { 0x05, 0x0000 },
60 { 0x0d, 0x0000 },
61 { 0x0e, 0x0000 },
62 { 0x0f, 0x0808 },
63 { 0x10, 0x0808 },
64 { 0x19, 0xafaf },
65 { 0x1a, 0xafaf },
66 { 0x1b, 0x0c00 },
67 { 0x1c, 0x2f2f },
68 { 0x1d, 0x2f2f },
69 { 0x1e, 0x0000 },
70 { 0x27, 0x7860 },
71 { 0x28, 0x7070 },
72 { 0x29, 0x8080 },
73 { 0x2a, 0x5252 },
74 { 0x2b, 0x5454 },
75 { 0x2f, 0x0000 },
76 { 0x30, 0x5000 },
77 { 0x3b, 0x0000 },
78 { 0x3c, 0x006f },
79 { 0x3d, 0x0000 },
80 { 0x3e, 0x006f },
81 { 0x45, 0x6000 },
82 { 0x4d, 0x0000 },
83 { 0x4e, 0x0000 },
84 { 0x4f, 0x0279 },
85 { 0x50, 0x0000 },
86 { 0x51, 0x0000 },
87 { 0x52, 0x0279 },
88 { 0x53, 0xf000 },
89 { 0x61, 0x0000 },
90 { 0x62, 0x0000 },
91 { 0x63, 0x00c0 },
92 { 0x64, 0x0000 },
93 { 0x65, 0x0000 },
94 { 0x66, 0x0000 },
95 { 0x70, 0x8000 },
96 { 0x71, 0x8000 },
97 { 0x73, 0x1104 },
98 { 0x74, 0x0c00 },
99 { 0x75, 0x1400 },
100 { 0x77, 0x0c00 },
101 { 0x78, 0x4000 },
102 { 0x79, 0x0123 },
103 { 0x80, 0x0000 },
104 { 0x81, 0x0000 },
105 { 0x82, 0x0000 },
106 { 0x83, 0x0800 },
107 { 0x84, 0x0000 },
108 { 0x85, 0x0008 },
109 { 0x89, 0x0000 },
110 { 0x8e, 0x0004 },
111 { 0x8f, 0x1100 },
112 { 0x90, 0x0000 },
113 { 0x93, 0x2000 },
114 { 0x94, 0x0200 },
115 { 0xb0, 0x2080 },
116 { 0xb1, 0x0000 },
117 { 0xb4, 0x2206 },
118 { 0xb5, 0x1f00 },
119 { 0xb6, 0x0000 },
120 { 0xbb, 0x0000 },
121 { 0xbc, 0x0000 },
122 { 0xbd, 0x0000 },
123 { 0xbe, 0x0000 },
124 { 0xbf, 0x0000 },
125 { 0xc0, 0x0400 },
126 { 0xc1, 0x0000 },
127 { 0xc2, 0x0000 },
128 { 0xcf, 0x0013 },
129 { 0xd0, 0x0680 },
130 { 0xd1, 0x1c17 },
131 { 0xd3, 0xb320 },
132 { 0xd9, 0x0809 },
133 { 0xfa, 0x0010 },
134 { 0xfe, 0x10ec },
135 { 0xff, 0x6281 },
136 };
137
rt5651_volatile_register(struct device * dev,unsigned int reg)138 static bool rt5651_volatile_register(struct device *dev, unsigned int reg)
139 {
140 int i;
141
142 for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) {
143 if ((reg >= rt5651_ranges[i].window_start &&
144 reg <= rt5651_ranges[i].window_start +
145 rt5651_ranges[i].window_len) ||
146 (reg >= rt5651_ranges[i].range_min &&
147 reg <= rt5651_ranges[i].range_max)) {
148 return true;
149 }
150 }
151
152 switch (reg) {
153 case RT5651_RESET:
154 case RT5651_PRIV_DATA:
155 case RT5651_EQ_CTRL1:
156 case RT5651_ALC_1:
157 case RT5651_IRQ_CTRL2:
158 case RT5651_INT_IRQ_ST:
159 case RT5651_PGM_REG_ARR1:
160 case RT5651_PGM_REG_ARR3:
161 case RT5651_VENDOR_ID:
162 case RT5651_DEVICE_ID:
163 return true;
164 default:
165 return false;
166 }
167 }
168
rt5651_readable_register(struct device * dev,unsigned int reg)169 static bool rt5651_readable_register(struct device *dev, unsigned int reg)
170 {
171 int i;
172
173 for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) {
174 if ((reg >= rt5651_ranges[i].window_start &&
175 reg <= rt5651_ranges[i].window_start +
176 rt5651_ranges[i].window_len) ||
177 (reg >= rt5651_ranges[i].range_min &&
178 reg <= rt5651_ranges[i].range_max)) {
179 return true;
180 }
181 }
182
183 switch (reg) {
184 case RT5651_RESET:
185 case RT5651_VERSION_ID:
186 case RT5651_VENDOR_ID:
187 case RT5651_DEVICE_ID:
188 case RT5651_HP_VOL:
189 case RT5651_LOUT_CTRL1:
190 case RT5651_LOUT_CTRL2:
191 case RT5651_IN1_IN2:
192 case RT5651_IN3:
193 case RT5651_INL1_INR1_VOL:
194 case RT5651_INL2_INR2_VOL:
195 case RT5651_DAC1_DIG_VOL:
196 case RT5651_DAC2_DIG_VOL:
197 case RT5651_DAC2_CTRL:
198 case RT5651_ADC_DIG_VOL:
199 case RT5651_ADC_DATA:
200 case RT5651_ADC_BST_VOL:
201 case RT5651_STO1_ADC_MIXER:
202 case RT5651_STO2_ADC_MIXER:
203 case RT5651_AD_DA_MIXER:
204 case RT5651_STO_DAC_MIXER:
205 case RT5651_DD_MIXER:
206 case RT5651_DIG_INF_DATA:
207 case RT5651_PDM_CTL:
208 case RT5651_REC_L1_MIXER:
209 case RT5651_REC_L2_MIXER:
210 case RT5651_REC_R1_MIXER:
211 case RT5651_REC_R2_MIXER:
212 case RT5651_HPO_MIXER:
213 case RT5651_OUT_L1_MIXER:
214 case RT5651_OUT_L2_MIXER:
215 case RT5651_OUT_L3_MIXER:
216 case RT5651_OUT_R1_MIXER:
217 case RT5651_OUT_R2_MIXER:
218 case RT5651_OUT_R3_MIXER:
219 case RT5651_LOUT_MIXER:
220 case RT5651_PWR_DIG1:
221 case RT5651_PWR_DIG2:
222 case RT5651_PWR_ANLG1:
223 case RT5651_PWR_ANLG2:
224 case RT5651_PWR_MIXER:
225 case RT5651_PWR_VOL:
226 case RT5651_PRIV_INDEX:
227 case RT5651_PRIV_DATA:
228 case RT5651_I2S1_SDP:
229 case RT5651_I2S2_SDP:
230 case RT5651_ADDA_CLK1:
231 case RT5651_ADDA_CLK2:
232 case RT5651_DMIC:
233 case RT5651_TDM_CTL_1:
234 case RT5651_TDM_CTL_2:
235 case RT5651_TDM_CTL_3:
236 case RT5651_GLB_CLK:
237 case RT5651_PLL_CTRL1:
238 case RT5651_PLL_CTRL2:
239 case RT5651_PLL_MODE_1:
240 case RT5651_PLL_MODE_2:
241 case RT5651_PLL_MODE_3:
242 case RT5651_PLL_MODE_4:
243 case RT5651_PLL_MODE_5:
244 case RT5651_PLL_MODE_6:
245 case RT5651_PLL_MODE_7:
246 case RT5651_DEPOP_M1:
247 case RT5651_DEPOP_M2:
248 case RT5651_DEPOP_M3:
249 case RT5651_CHARGE_PUMP:
250 case RT5651_MICBIAS:
251 case RT5651_A_JD_CTL1:
252 case RT5651_EQ_CTRL1:
253 case RT5651_EQ_CTRL2:
254 case RT5651_ALC_1:
255 case RT5651_ALC_2:
256 case RT5651_ALC_3:
257 case RT5651_JD_CTRL1:
258 case RT5651_JD_CTRL2:
259 case RT5651_IRQ_CTRL1:
260 case RT5651_IRQ_CTRL2:
261 case RT5651_INT_IRQ_ST:
262 case RT5651_GPIO_CTRL1:
263 case RT5651_GPIO_CTRL2:
264 case RT5651_GPIO_CTRL3:
265 case RT5651_PGM_REG_ARR1:
266 case RT5651_PGM_REG_ARR2:
267 case RT5651_PGM_REG_ARR3:
268 case RT5651_PGM_REG_ARR4:
269 case RT5651_PGM_REG_ARR5:
270 case RT5651_SCB_FUNC:
271 case RT5651_SCB_CTRL:
272 case RT5651_BASE_BACK:
273 case RT5651_MP3_PLUS1:
274 case RT5651_MP3_PLUS2:
275 case RT5651_ADJ_HPF_CTRL1:
276 case RT5651_ADJ_HPF_CTRL2:
277 case RT5651_HP_CALIB_AMP_DET:
278 case RT5651_HP_CALIB2:
279 case RT5651_SV_ZCD1:
280 case RT5651_SV_ZCD2:
281 case RT5651_D_MISC:
282 case RT5651_DUMMY2:
283 case RT5651_DUMMY3:
284 return true;
285 default:
286 return false;
287 }
288 }
289
rt5651_asrc_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)290 static int rt5651_asrc_get(struct snd_kcontrol *kcontrol,
291 struct snd_ctl_elem_value *ucontrol)
292 {
293 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
294 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
295
296 ucontrol->value.integer.value[0] = rt5651->asrc_en;
297
298 return 0;
299 }
300
rt5651_asrc_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)301 static int rt5651_asrc_put(struct snd_kcontrol *kcontrol,
302 struct snd_ctl_elem_value *ucontrol)
303 {
304 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
305 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
306
307 rt5651->asrc_en = ucontrol->value.integer.value[0];
308 if (rt5651->asrc_en) {
309 regmap_write(rt5651->regmap, 0x80, 0x4000);
310 regmap_write(rt5651->regmap, 0x81, 0x0302);
311 regmap_write(rt5651->regmap, 0x82, 0x0800);
312 regmap_write(rt5651->regmap, 0x73, 0x1004);
313 regmap_write(rt5651->regmap, 0x83, 0x1000);
314 regmap_write(rt5651->regmap, 0x84, 0x7000);
315 snd_soc_component_update_bits(component, 0x64, 0x0200, 0x0200);
316 snd_soc_component_update_bits(component, RT5651_D_MISC, 0xc00, 0xc00);
317 } else {
318 regmap_write(rt5651->regmap, 0x83, 0x0);
319 regmap_write(rt5651->regmap, 0x84, 0x0);
320 }
321 return 0;
322 }
323
324 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
325 static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -6562, 0);
326 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
327 static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -1762, 3000);
328 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
329
330 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
331 static const DECLARE_TLV_DB_RANGE(bst_tlv,
332 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
333 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
334 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
335 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
336 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
337 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
338 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
339 );
340
341 /* Interface data select */
342 static const char * const rt5651_data_select[] = {
343 "Normal", "Swap", "left copy to right", "right copy to left"};
344
345 static SOC_ENUM_SINGLE_DECL(rt5651_if2_dac_enum, RT5651_DIG_INF_DATA,
346 RT5651_IF2_DAC_SEL_SFT, rt5651_data_select);
347
348 static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_enum, RT5651_DIG_INF_DATA,
349 RT5651_IF2_ADC_SEL_SFT, rt5651_data_select);
350
351 static const char * const rt5651_asrc_mode[] = {"Disable", "Enable"};
352
353 static SOC_ENUM_SINGLE_DECL(rt5651_asrc_enum, 0, 0, rt5651_asrc_mode);
354
355 static const struct snd_kcontrol_new rt5651_snd_controls[] = {
356 /* Headphone Output Volume */
357 SOC_DOUBLE_TLV("HP Playback Volume", RT5651_HP_VOL,
358 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv),
359 /* OUTPUT Control */
360 SOC_DOUBLE_TLV("OUT Playback Volume", RT5651_LOUT_CTRL1,
361 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv),
362
363 /* DAC Digital Volume */
364 SOC_DOUBLE("DAC2 Playback Switch", RT5651_DAC2_CTRL,
365 RT5651_M_DAC_L2_VOL_SFT, RT5651_M_DAC_R2_VOL_SFT, 1, 1),
366 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5651_DAC1_DIG_VOL,
367 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
368 175, 0, dac_vol_tlv),
369 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5651_DAC2_DIG_VOL,
370 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
371 175, 0, dac_vol_tlv),
372 /* IN1/IN2/IN3 Control */
373 SOC_SINGLE_TLV("IN1 Boost", RT5651_IN1_IN2,
374 RT5651_BST_SFT1, 8, 0, bst_tlv),
375 SOC_SINGLE_TLV("IN2 Boost", RT5651_IN1_IN2,
376 RT5651_BST_SFT2, 8, 0, bst_tlv),
377 SOC_SINGLE_TLV("IN3 Boost", RT5651_IN3,
378 RT5651_BST_SFT1, 8, 0, bst_tlv),
379 /* INL/INR Volume Control */
380 SOC_DOUBLE_TLV("IN Capture Volume", RT5651_INL1_INR1_VOL,
381 RT5651_INL_VOL_SFT, RT5651_INR_VOL_SFT,
382 31, 1, in_vol_tlv),
383 /* ADC Digital Volume Control */
384 SOC_DOUBLE("ADC Capture Switch", RT5651_ADC_DIG_VOL,
385 RT5651_L_MUTE_SFT, RT5651_R_MUTE_SFT, 1, 1),
386 SOC_DOUBLE_TLV("ADC Capture Volume", RT5651_ADC_DIG_VOL,
387 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
388 127, 0, adc_vol_tlv),
389 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5651_ADC_DATA,
390 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
391 127, 0, adc_vol_tlv),
392 /* ADC Boost Volume Control */
393 SOC_DOUBLE_TLV("ADC Boost Gain", RT5651_ADC_BST_VOL,
394 RT5651_ADC_L_BST_SFT, RT5651_ADC_R_BST_SFT,
395 3, 0, adc_bst_tlv),
396
397 /* RT5651 ASRC Switch */
398 SOC_ENUM_EXT("RT5651 ASRC Switch", rt5651_asrc_enum,
399 rt5651_asrc_get, rt5651_asrc_put),
400 /* ASRC */
401 SOC_SINGLE("IF1 ASRC Switch", RT5651_PLL_MODE_1,
402 RT5651_STO1_T_SFT, 1, 0),
403 SOC_SINGLE("IF2 ASRC Switch", RT5651_PLL_MODE_1,
404 RT5651_STO2_T_SFT, 1, 0),
405 SOC_SINGLE("DMIC ASRC Switch", RT5651_PLL_MODE_1,
406 RT5651_DMIC_1_M_SFT, 1, 0),
407
408 SOC_ENUM("ADC IF2 Data Switch", rt5651_if2_adc_enum),
409 SOC_ENUM("DAC IF2 Data Switch", rt5651_if2_dac_enum),
410 };
411
412 /**
413 * set_dmic_clk - Set parameter of dmic.
414 *
415 * @w: DAPM widget.
416 * @kcontrol: The kcontrol of this widget.
417 * @event: Event id.
418 *
419 */
set_dmic_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)420 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
421 struct snd_kcontrol *kcontrol, int event)
422 {
423 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
424 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
425 int idx, rate;
426
427 rate = rt5651->sysclk / rl6231_get_pre_div(rt5651->regmap,
428 RT5651_ADDA_CLK1, RT5651_I2S_PD1_SFT);
429 idx = rl6231_calc_dmic_clk(rate);
430 if (idx < 0)
431 dev_err(component->dev, "Failed to set DMIC clock\n");
432 else
433 snd_soc_component_update_bits(component, RT5651_DMIC, RT5651_DMIC_CLK_MASK,
434 idx << RT5651_DMIC_CLK_SFT);
435
436 return idx;
437 }
438
439 /* Digital Mixer */
440 static const struct snd_kcontrol_new rt5651_sto1_adc_l_mix[] = {
441 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER,
442 RT5651_M_STO1_ADC_L1_SFT, 1, 1),
443 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER,
444 RT5651_M_STO1_ADC_L2_SFT, 1, 1),
445 };
446
447 static const struct snd_kcontrol_new rt5651_sto1_adc_r_mix[] = {
448 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER,
449 RT5651_M_STO1_ADC_R1_SFT, 1, 1),
450 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER,
451 RT5651_M_STO1_ADC_R2_SFT, 1, 1),
452 };
453
454 static const struct snd_kcontrol_new rt5651_sto2_adc_l_mix[] = {
455 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER,
456 RT5651_M_STO2_ADC_L1_SFT, 1, 1),
457 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER,
458 RT5651_M_STO2_ADC_L2_SFT, 1, 1),
459 };
460
461 static const struct snd_kcontrol_new rt5651_sto2_adc_r_mix[] = {
462 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER,
463 RT5651_M_STO2_ADC_R1_SFT, 1, 1),
464 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER,
465 RT5651_M_STO2_ADC_R2_SFT, 1, 1),
466 };
467
468 static const struct snd_kcontrol_new rt5651_dac_l_mix[] = {
469 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER,
470 RT5651_M_ADCMIX_L_SFT, 1, 1),
471 SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER,
472 RT5651_M_IF1_DAC_L_SFT, 1, 1),
473 };
474
475 static const struct snd_kcontrol_new rt5651_dac_r_mix[] = {
476 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER,
477 RT5651_M_ADCMIX_R_SFT, 1, 1),
478 SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER,
479 RT5651_M_IF1_DAC_R_SFT, 1, 1),
480 };
481
482 static const struct snd_kcontrol_new rt5651_sto_dac_l_mix[] = {
483 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER,
484 RT5651_M_DAC_L1_MIXL_SFT, 1, 1),
485 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_STO_DAC_MIXER,
486 RT5651_M_DAC_L2_MIXL_SFT, 1, 1),
487 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
488 RT5651_M_DAC_R1_MIXL_SFT, 1, 1),
489 };
490
491 static const struct snd_kcontrol_new rt5651_sto_dac_r_mix[] = {
492 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
493 RT5651_M_DAC_R1_MIXR_SFT, 1, 1),
494 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_STO_DAC_MIXER,
495 RT5651_M_DAC_R2_MIXR_SFT, 1, 1),
496 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER,
497 RT5651_M_DAC_L1_MIXR_SFT, 1, 1),
498 };
499
500 static const struct snd_kcontrol_new rt5651_dd_dac_l_mix[] = {
501 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_DD_MIXER,
502 RT5651_M_STO_DD_L1_SFT, 1, 1),
503 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
504 RT5651_M_STO_DD_L2_SFT, 1, 1),
505 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
506 RT5651_M_STO_DD_R2_L_SFT, 1, 1),
507 };
508
509 static const struct snd_kcontrol_new rt5651_dd_dac_r_mix[] = {
510 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_DD_MIXER,
511 RT5651_M_STO_DD_R1_SFT, 1, 1),
512 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
513 RT5651_M_STO_DD_R2_SFT, 1, 1),
514 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
515 RT5651_M_STO_DD_L2_R_SFT, 1, 1),
516 };
517
518 /* Analog Input Mixer */
519 static const struct snd_kcontrol_new rt5651_rec_l_mix[] = {
520 SOC_DAPM_SINGLE("INL1 Switch", RT5651_REC_L2_MIXER,
521 RT5651_M_IN1_L_RM_L_SFT, 1, 1),
522 SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_L2_MIXER,
523 RT5651_M_BST3_RM_L_SFT, 1, 1),
524 SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_L2_MIXER,
525 RT5651_M_BST2_RM_L_SFT, 1, 1),
526 SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_L2_MIXER,
527 RT5651_M_BST1_RM_L_SFT, 1, 1),
528 };
529
530 static const struct snd_kcontrol_new rt5651_rec_r_mix[] = {
531 SOC_DAPM_SINGLE("INR1 Switch", RT5651_REC_R2_MIXER,
532 RT5651_M_IN1_R_RM_R_SFT, 1, 1),
533 SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_R2_MIXER,
534 RT5651_M_BST3_RM_R_SFT, 1, 1),
535 SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_R2_MIXER,
536 RT5651_M_BST2_RM_R_SFT, 1, 1),
537 SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_R2_MIXER,
538 RT5651_M_BST1_RM_R_SFT, 1, 1),
539 };
540
541 /* Analog Output Mixer */
542
543 static const struct snd_kcontrol_new rt5651_out_l_mix[] = {
544 SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_L3_MIXER,
545 RT5651_M_BST1_OM_L_SFT, 1, 1),
546 SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_L3_MIXER,
547 RT5651_M_BST2_OM_L_SFT, 1, 1),
548 SOC_DAPM_SINGLE("INL1 Switch", RT5651_OUT_L3_MIXER,
549 RT5651_M_IN1_L_OM_L_SFT, 1, 1),
550 SOC_DAPM_SINGLE("REC MIXL Switch", RT5651_OUT_L3_MIXER,
551 RT5651_M_RM_L_OM_L_SFT, 1, 1),
552 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_OUT_L3_MIXER,
553 RT5651_M_DAC_L1_OM_L_SFT, 1, 1),
554 };
555
556 static const struct snd_kcontrol_new rt5651_out_r_mix[] = {
557 SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_R3_MIXER,
558 RT5651_M_BST2_OM_R_SFT, 1, 1),
559 SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_R3_MIXER,
560 RT5651_M_BST1_OM_R_SFT, 1, 1),
561 SOC_DAPM_SINGLE("INR1 Switch", RT5651_OUT_R3_MIXER,
562 RT5651_M_IN1_R_OM_R_SFT, 1, 1),
563 SOC_DAPM_SINGLE("REC MIXR Switch", RT5651_OUT_R3_MIXER,
564 RT5651_M_RM_R_OM_R_SFT, 1, 1),
565 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_OUT_R3_MIXER,
566 RT5651_M_DAC_R1_OM_R_SFT, 1, 1),
567 };
568
569 static const struct snd_kcontrol_new rt5651_hpo_mix[] = {
570 SOC_DAPM_SINGLE("HPO MIX DAC1 Switch", RT5651_HPO_MIXER,
571 RT5651_M_DAC1_HM_SFT, 1, 1),
572 SOC_DAPM_SINGLE("HPO MIX HPVOL Switch", RT5651_HPO_MIXER,
573 RT5651_M_HPVOL_HM_SFT, 1, 1),
574 };
575
576 static const struct snd_kcontrol_new rt5651_lout_mix[] = {
577 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_LOUT_MIXER,
578 RT5651_M_DAC_L1_LM_SFT, 1, 1),
579 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_LOUT_MIXER,
580 RT5651_M_DAC_R1_LM_SFT, 1, 1),
581 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5651_LOUT_MIXER,
582 RT5651_M_OV_L_LM_SFT, 1, 1),
583 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5651_LOUT_MIXER,
584 RT5651_M_OV_R_LM_SFT, 1, 1),
585 };
586
587 static const struct snd_kcontrol_new outvol_l_control =
588 SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1,
589 RT5651_VOL_L_SFT, 1, 1);
590
591 static const struct snd_kcontrol_new outvol_r_control =
592 SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1,
593 RT5651_VOL_R_SFT, 1, 1);
594
595 static const struct snd_kcontrol_new lout_l_mute_control =
596 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1,
597 RT5651_L_MUTE_SFT, 1, 1);
598
599 static const struct snd_kcontrol_new lout_r_mute_control =
600 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1,
601 RT5651_R_MUTE_SFT, 1, 1);
602
603 static const struct snd_kcontrol_new hpovol_l_control =
604 SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL,
605 RT5651_VOL_L_SFT, 1, 1);
606
607 static const struct snd_kcontrol_new hpovol_r_control =
608 SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL,
609 RT5651_VOL_R_SFT, 1, 1);
610
611 static const struct snd_kcontrol_new hpo_l_mute_control =
612 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL,
613 RT5651_L_MUTE_SFT, 1, 1);
614
615 static const struct snd_kcontrol_new hpo_r_mute_control =
616 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL,
617 RT5651_R_MUTE_SFT, 1, 1);
618
619 /* Stereo ADC source */
620 static const char * const rt5651_stereo1_adc1_src[] = {"DD MIX", "ADC"};
621
622 static SOC_ENUM_SINGLE_DECL(
623 rt5651_stereo1_adc1_enum, RT5651_STO1_ADC_MIXER,
624 RT5651_STO1_ADC_1_SRC_SFT, rt5651_stereo1_adc1_src);
625
626 static const struct snd_kcontrol_new rt5651_sto1_adc_l1_mux =
627 SOC_DAPM_ENUM("Stereo1 ADC L1 source", rt5651_stereo1_adc1_enum);
628
629 static const struct snd_kcontrol_new rt5651_sto1_adc_r1_mux =
630 SOC_DAPM_ENUM("Stereo1 ADC R1 source", rt5651_stereo1_adc1_enum);
631
632 static const char * const rt5651_stereo1_adc2_src[] = {"DMIC", "DD MIX"};
633
634 static SOC_ENUM_SINGLE_DECL(
635 rt5651_stereo1_adc2_enum, RT5651_STO1_ADC_MIXER,
636 RT5651_STO1_ADC_2_SRC_SFT, rt5651_stereo1_adc2_src);
637
638 static const struct snd_kcontrol_new rt5651_sto1_adc_l2_mux =
639 SOC_DAPM_ENUM("Stereo1 ADC L2 source", rt5651_stereo1_adc2_enum);
640
641 static const struct snd_kcontrol_new rt5651_sto1_adc_r2_mux =
642 SOC_DAPM_ENUM("Stereo1 ADC R2 source", rt5651_stereo1_adc2_enum);
643
644 /* Mono ADC source */
645 static const char * const rt5651_sto2_adc_l1_src[] = {"DD MIXL", "ADCL"};
646
647 static SOC_ENUM_SINGLE_DECL(
648 rt5651_sto2_adc_l1_enum, RT5651_STO1_ADC_MIXER,
649 RT5651_STO2_ADC_L1_SRC_SFT, rt5651_sto2_adc_l1_src);
650
651 static const struct snd_kcontrol_new rt5651_sto2_adc_l1_mux =
652 SOC_DAPM_ENUM("Stereo2 ADC1 left source", rt5651_sto2_adc_l1_enum);
653
654 static const char * const rt5651_sto2_adc_l2_src[] = {"DMIC L", "DD MIXL"};
655
656 static SOC_ENUM_SINGLE_DECL(
657 rt5651_sto2_adc_l2_enum, RT5651_STO1_ADC_MIXER,
658 RT5651_STO2_ADC_L2_SRC_SFT, rt5651_sto2_adc_l2_src);
659
660 static const struct snd_kcontrol_new rt5651_sto2_adc_l2_mux =
661 SOC_DAPM_ENUM("Stereo2 ADC2 left source", rt5651_sto2_adc_l2_enum);
662
663 static const char * const rt5651_sto2_adc_r1_src[] = {"DD MIXR", "ADCR"};
664
665 static SOC_ENUM_SINGLE_DECL(
666 rt5651_sto2_adc_r1_enum, RT5651_STO1_ADC_MIXER,
667 RT5651_STO2_ADC_R1_SRC_SFT, rt5651_sto2_adc_r1_src);
668
669 static const struct snd_kcontrol_new rt5651_sto2_adc_r1_mux =
670 SOC_DAPM_ENUM("Stereo2 ADC1 right source", rt5651_sto2_adc_r1_enum);
671
672 static const char * const rt5651_sto2_adc_r2_src[] = {"DMIC R", "DD MIXR"};
673
674 static SOC_ENUM_SINGLE_DECL(
675 rt5651_sto2_adc_r2_enum, RT5651_STO1_ADC_MIXER,
676 RT5651_STO2_ADC_R2_SRC_SFT, rt5651_sto2_adc_r2_src);
677
678 static const struct snd_kcontrol_new rt5651_sto2_adc_r2_mux =
679 SOC_DAPM_ENUM("Stereo2 ADC2 right source", rt5651_sto2_adc_r2_enum);
680
681 /* DAC2 channel source */
682
683 static const char * const rt5651_dac_src[] = {"IF1", "IF2"};
684
685 static SOC_ENUM_SINGLE_DECL(rt5651_dac_l2_enum, RT5651_DAC2_CTRL,
686 RT5651_SEL_DAC_L2_SFT, rt5651_dac_src);
687
688 static const struct snd_kcontrol_new rt5651_dac_l2_mux =
689 SOC_DAPM_ENUM("DAC2 left channel source", rt5651_dac_l2_enum);
690
691 static SOC_ENUM_SINGLE_DECL(
692 rt5651_dac_r2_enum, RT5651_DAC2_CTRL,
693 RT5651_SEL_DAC_R2_SFT, rt5651_dac_src);
694
695 static const struct snd_kcontrol_new rt5651_dac_r2_mux =
696 SOC_DAPM_ENUM("DAC2 right channel source", rt5651_dac_r2_enum);
697
698 /* IF2_ADC channel source */
699
700 static const char * const rt5651_adc_src[] = {"IF1 ADC1", "IF1 ADC2"};
701
702 static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_src_enum, RT5651_DIG_INF_DATA,
703 RT5651_IF2_ADC_SRC_SFT, rt5651_adc_src);
704
705 static const struct snd_kcontrol_new rt5651_if2_adc_src_mux =
706 SOC_DAPM_ENUM("IF2 ADC channel source", rt5651_if2_adc_src_enum);
707
708 /* PDM select */
709 static const char * const rt5651_pdm_sel[] = {"DD MIX", "Stereo DAC MIX"};
710
711 static SOC_ENUM_SINGLE_DECL(
712 rt5651_pdm_l_sel_enum, RT5651_PDM_CTL,
713 RT5651_PDM_L_SEL_SFT, rt5651_pdm_sel);
714
715 static SOC_ENUM_SINGLE_DECL(
716 rt5651_pdm_r_sel_enum, RT5651_PDM_CTL,
717 RT5651_PDM_R_SEL_SFT, rt5651_pdm_sel);
718
719 static const struct snd_kcontrol_new rt5651_pdm_l_mux =
720 SOC_DAPM_ENUM("PDM L select", rt5651_pdm_l_sel_enum);
721
722 static const struct snd_kcontrol_new rt5651_pdm_r_mux =
723 SOC_DAPM_ENUM("PDM R select", rt5651_pdm_r_sel_enum);
724
rt5651_amp_power_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)725 static int rt5651_amp_power_event(struct snd_soc_dapm_widget *w,
726 struct snd_kcontrol *kcontrol, int event)
727 {
728 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
729 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
730
731 switch (event) {
732 case SND_SOC_DAPM_POST_PMU:
733 /* depop parameters */
734 regmap_update_bits(rt5651->regmap, RT5651_PR_BASE +
735 RT5651_CHPUMP_INT_REG1, 0x0700, 0x0200);
736 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2,
737 RT5651_DEPOP_MASK, RT5651_DEPOP_MAN);
738 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1,
739 RT5651_HP_CP_MASK | RT5651_HP_SG_MASK |
740 RT5651_HP_CB_MASK, RT5651_HP_CP_PU |
741 RT5651_HP_SG_DIS | RT5651_HP_CB_PU);
742 regmap_write(rt5651->regmap, RT5651_PR_BASE +
743 RT5651_HP_DCC_INT1, 0x9f00);
744 /* headphone amp power on */
745 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
746 RT5651_PWR_FV1 | RT5651_PWR_FV2, 0);
747 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
748 RT5651_PWR_HA,
749 RT5651_PWR_HA);
750 usleep_range(10000, 15000);
751 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
752 RT5651_PWR_FV1 | RT5651_PWR_FV2 ,
753 RT5651_PWR_FV1 | RT5651_PWR_FV2);
754 break;
755
756 default:
757 return 0;
758 }
759
760 return 0;
761 }
762
rt5651_hp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)763 static int rt5651_hp_event(struct snd_soc_dapm_widget *w,
764 struct snd_kcontrol *kcontrol, int event)
765 {
766 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
767 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
768
769 switch (event) {
770 case SND_SOC_DAPM_POST_PMU:
771 /* headphone unmute sequence */
772 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2,
773 RT5651_DEPOP_MASK | RT5651_DIG_DP_MASK,
774 RT5651_DEPOP_AUTO | RT5651_DIG_DP_EN);
775 regmap_update_bits(rt5651->regmap, RT5651_CHARGE_PUMP,
776 RT5651_PM_HP_MASK, RT5651_PM_HP_HV);
777
778 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M3,
779 RT5651_CP_FQ1_MASK | RT5651_CP_FQ2_MASK |
780 RT5651_CP_FQ3_MASK,
781 (RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ1_SFT) |
782 (RT5651_CP_FQ_12_KHZ << RT5651_CP_FQ2_SFT) |
783 (RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ3_SFT));
784
785 regmap_write(rt5651->regmap, RT5651_PR_BASE +
786 RT5651_MAMP_INT_REG2, 0x1c00);
787 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1,
788 RT5651_HP_CP_MASK | RT5651_HP_SG_MASK,
789 RT5651_HP_CP_PD | RT5651_HP_SG_EN);
790 regmap_update_bits(rt5651->regmap, RT5651_PR_BASE +
791 RT5651_CHPUMP_INT_REG1, 0x0700, 0x0400);
792 rt5651->hp_mute = false;
793 break;
794
795 case SND_SOC_DAPM_PRE_PMD:
796 rt5651->hp_mute = true;
797 usleep_range(70000, 75000);
798 break;
799
800 default:
801 return 0;
802 }
803
804 return 0;
805 }
806
rt5651_hp_post_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)807 static int rt5651_hp_post_event(struct snd_soc_dapm_widget *w,
808 struct snd_kcontrol *kcontrol, int event)
809 {
810
811 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
812 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
813
814 switch (event) {
815 case SND_SOC_DAPM_POST_PMU:
816 if (!rt5651->hp_mute)
817 usleep_range(80000, 85000);
818
819 break;
820
821 default:
822 return 0;
823 }
824
825 return 0;
826 }
827
rt5651_bst1_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)828 static int rt5651_bst1_event(struct snd_soc_dapm_widget *w,
829 struct snd_kcontrol *kcontrol, int event)
830 {
831 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
832
833 switch (event) {
834 case SND_SOC_DAPM_POST_PMU:
835 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
836 RT5651_PWR_BST1_OP2, RT5651_PWR_BST1_OP2);
837 break;
838
839 case SND_SOC_DAPM_PRE_PMD:
840 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
841 RT5651_PWR_BST1_OP2, 0);
842 break;
843
844 default:
845 return 0;
846 }
847
848 return 0;
849 }
850
rt5651_bst2_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)851 static int rt5651_bst2_event(struct snd_soc_dapm_widget *w,
852 struct snd_kcontrol *kcontrol, int event)
853 {
854 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
855
856 switch (event) {
857 case SND_SOC_DAPM_POST_PMU:
858 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
859 RT5651_PWR_BST2_OP2, RT5651_PWR_BST2_OP2);
860 break;
861
862 case SND_SOC_DAPM_PRE_PMD:
863 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
864 RT5651_PWR_BST2_OP2, 0);
865 break;
866
867 default:
868 return 0;
869 }
870
871 return 0;
872 }
873
rt5651_bst3_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)874 static int rt5651_bst3_event(struct snd_soc_dapm_widget *w,
875 struct snd_kcontrol *kcontrol, int event)
876 {
877 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
878
879 switch (event) {
880 case SND_SOC_DAPM_POST_PMU:
881 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
882 RT5651_PWR_BST3_OP2, RT5651_PWR_BST3_OP2);
883 break;
884
885 case SND_SOC_DAPM_PRE_PMD:
886 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
887 RT5651_PWR_BST3_OP2, 0);
888 break;
889
890 default:
891 return 0;
892 }
893
894 return 0;
895 }
896
897 static const struct snd_soc_dapm_widget rt5651_dapm_widgets[] = {
898 /* ASRC */
899 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5651_PLL_MODE_2,
900 15, 0, NULL, 0),
901 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5651_PLL_MODE_2,
902 14, 0, NULL, 0),
903 SND_SOC_DAPM_SUPPLY_S("STO1 DAC ASRC", 1, RT5651_PLL_MODE_2,
904 13, 0, NULL, 0),
905 SND_SOC_DAPM_SUPPLY_S("STO2 DAC ASRC", 1, RT5651_PLL_MODE_2,
906 12, 0, NULL, 0),
907 SND_SOC_DAPM_SUPPLY_S("ADC ASRC", 1, RT5651_PLL_MODE_2,
908 11, 0, NULL, 0),
909
910 /* micbias */
911 SND_SOC_DAPM_SUPPLY("LDO", RT5651_PWR_ANLG1,
912 RT5651_PWR_LDO_BIT, 0, NULL, 0),
913 SND_SOC_DAPM_SUPPLY("micbias1", RT5651_PWR_ANLG2,
914 RT5651_PWR_MB1_BIT, 0, NULL, 0),
915 /* Input Lines */
916 SND_SOC_DAPM_INPUT("MIC1"),
917 SND_SOC_DAPM_INPUT("MIC2"),
918 SND_SOC_DAPM_INPUT("MIC3"),
919
920 SND_SOC_DAPM_INPUT("IN1P"),
921 SND_SOC_DAPM_INPUT("IN2P"),
922 SND_SOC_DAPM_INPUT("IN2N"),
923 SND_SOC_DAPM_INPUT("IN3P"),
924 SND_SOC_DAPM_INPUT("DMIC L1"),
925 SND_SOC_DAPM_INPUT("DMIC R1"),
926 SND_SOC_DAPM_SUPPLY("DMIC CLK", RT5651_DMIC, RT5651_DMIC_1_EN_SFT,
927 0, set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
928 /* Boost */
929 SND_SOC_DAPM_PGA_E("BST1", RT5651_PWR_ANLG2,
930 RT5651_PWR_BST1_BIT, 0, NULL, 0, rt5651_bst1_event,
931 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
932 SND_SOC_DAPM_PGA_E("BST2", RT5651_PWR_ANLG2,
933 RT5651_PWR_BST2_BIT, 0, NULL, 0, rt5651_bst2_event,
934 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
935 SND_SOC_DAPM_PGA_E("BST3", RT5651_PWR_ANLG2,
936 RT5651_PWR_BST3_BIT, 0, NULL, 0, rt5651_bst3_event,
937 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
938 /* Input Volume */
939 SND_SOC_DAPM_PGA("INL1 VOL", RT5651_PWR_VOL,
940 RT5651_PWR_IN1_L_BIT, 0, NULL, 0),
941 SND_SOC_DAPM_PGA("INR1 VOL", RT5651_PWR_VOL,
942 RT5651_PWR_IN1_R_BIT, 0, NULL, 0),
943 SND_SOC_DAPM_PGA("INL2 VOL", RT5651_PWR_VOL,
944 RT5651_PWR_IN2_L_BIT, 0, NULL, 0),
945 SND_SOC_DAPM_PGA("INR2 VOL", RT5651_PWR_VOL,
946 RT5651_PWR_IN2_R_BIT, 0, NULL, 0),
947
948 /* REC Mixer */
949 SND_SOC_DAPM_MIXER("RECMIXL", RT5651_PWR_MIXER, RT5651_PWR_RM_L_BIT, 0,
950 rt5651_rec_l_mix, ARRAY_SIZE(rt5651_rec_l_mix)),
951 SND_SOC_DAPM_MIXER("RECMIXR", RT5651_PWR_MIXER, RT5651_PWR_RM_R_BIT, 0,
952 rt5651_rec_r_mix, ARRAY_SIZE(rt5651_rec_r_mix)),
953 /* ADCs */
954 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
955 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
956 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5651_PWR_DIG1,
957 RT5651_PWR_ADC_L_BIT, 0, NULL, 0),
958 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5651_PWR_DIG1,
959 RT5651_PWR_ADC_R_BIT, 0, NULL, 0),
960 /* ADC Mux */
961 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
962 &rt5651_sto1_adc_l2_mux),
963 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
964 &rt5651_sto1_adc_r2_mux),
965 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
966 &rt5651_sto1_adc_l1_mux),
967 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
968 &rt5651_sto1_adc_r1_mux),
969 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
970 &rt5651_sto2_adc_l2_mux),
971 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
972 &rt5651_sto2_adc_l1_mux),
973 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
974 &rt5651_sto2_adc_r1_mux),
975 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
976 &rt5651_sto2_adc_r2_mux),
977 /* ADC Mixer */
978 SND_SOC_DAPM_SUPPLY("Stereo1 Filter", RT5651_PWR_DIG2,
979 RT5651_PWR_ADC_STO1_F_BIT, 0, NULL, 0),
980 SND_SOC_DAPM_SUPPLY("Stereo2 Filter", RT5651_PWR_DIG2,
981 RT5651_PWR_ADC_STO2_F_BIT, 0, NULL, 0),
982 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0,
983 rt5651_sto1_adc_l_mix,
984 ARRAY_SIZE(rt5651_sto1_adc_l_mix)),
985 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0,
986 rt5651_sto1_adc_r_mix,
987 ARRAY_SIZE(rt5651_sto1_adc_r_mix)),
988 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0,
989 rt5651_sto2_adc_l_mix,
990 ARRAY_SIZE(rt5651_sto2_adc_l_mix)),
991 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0,
992 rt5651_sto2_adc_r_mix,
993 ARRAY_SIZE(rt5651_sto2_adc_r_mix)),
994
995 /* Digital Interface */
996 SND_SOC_DAPM_SUPPLY("I2S1", RT5651_PWR_DIG1,
997 RT5651_PWR_I2S1_BIT, 0, NULL, 0),
998 SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
999 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1000 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1001 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1002 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1003 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1004 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1005 SND_SOC_DAPM_SUPPLY("I2S2", RT5651_PWR_DIG1,
1006 RT5651_PWR_I2S2_BIT, 0, NULL, 0),
1007 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1008 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1009 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1010 SND_SOC_DAPM_MUX("IF2 ADC", SND_SOC_NOPM, 0, 0,
1011 &rt5651_if2_adc_src_mux),
1012
1013 /* Digital Interface Select */
1014
1015 SND_SOC_DAPM_MUX("PDM L Mux", RT5651_PDM_CTL,
1016 RT5651_M_PDM_L_SFT, 1, &rt5651_pdm_l_mux),
1017 SND_SOC_DAPM_MUX("PDM R Mux", RT5651_PDM_CTL,
1018 RT5651_M_PDM_R_SFT, 1, &rt5651_pdm_r_mux),
1019 /* Audio Interface */
1020 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1021 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1022 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1023 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1024
1025 /* Audio DSP */
1026 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
1027
1028 /* Output Side */
1029 /* DAC mixer before sound effect */
1030 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1031 rt5651_dac_l_mix, ARRAY_SIZE(rt5651_dac_l_mix)),
1032 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1033 rt5651_dac_r_mix, ARRAY_SIZE(rt5651_dac_r_mix)),
1034
1035 /* DAC2 channel Mux */
1036 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_l2_mux),
1037 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_r2_mux),
1038 SND_SOC_DAPM_PGA("DAC L2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
1039 SND_SOC_DAPM_PGA("DAC R2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
1040
1041 SND_SOC_DAPM_SUPPLY("Stero1 DAC Power", RT5651_PWR_DIG2,
1042 RT5651_PWR_DAC_STO1_F_BIT, 0, NULL, 0),
1043 SND_SOC_DAPM_SUPPLY("Stero2 DAC Power", RT5651_PWR_DIG2,
1044 RT5651_PWR_DAC_STO2_F_BIT, 0, NULL, 0),
1045 /* DAC Mixer */
1046 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1047 rt5651_sto_dac_l_mix,
1048 ARRAY_SIZE(rt5651_sto_dac_l_mix)),
1049 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1050 rt5651_sto_dac_r_mix,
1051 ARRAY_SIZE(rt5651_sto_dac_r_mix)),
1052 SND_SOC_DAPM_MIXER("DD MIXL", SND_SOC_NOPM, 0, 0,
1053 rt5651_dd_dac_l_mix,
1054 ARRAY_SIZE(rt5651_dd_dac_l_mix)),
1055 SND_SOC_DAPM_MIXER("DD MIXR", SND_SOC_NOPM, 0, 0,
1056 rt5651_dd_dac_r_mix,
1057 ARRAY_SIZE(rt5651_dd_dac_r_mix)),
1058
1059 /* DACs */
1060 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
1061 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
1062 SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT5651_PWR_DIG1,
1063 RT5651_PWR_DAC_L1_BIT, 0, NULL, 0),
1064 SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5651_PWR_DIG1,
1065 RT5651_PWR_DAC_R1_BIT, 0, NULL, 0),
1066 /* OUT Mixer */
1067 SND_SOC_DAPM_MIXER("OUT MIXL", RT5651_PWR_MIXER, RT5651_PWR_OM_L_BIT,
1068 0, rt5651_out_l_mix, ARRAY_SIZE(rt5651_out_l_mix)),
1069 SND_SOC_DAPM_MIXER("OUT MIXR", RT5651_PWR_MIXER, RT5651_PWR_OM_R_BIT,
1070 0, rt5651_out_r_mix, ARRAY_SIZE(rt5651_out_r_mix)),
1071 /* Ouput Volume */
1072 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5651_PWR_VOL,
1073 RT5651_PWR_OV_L_BIT, 0, &outvol_l_control),
1074 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5651_PWR_VOL,
1075 RT5651_PWR_OV_R_BIT, 0, &outvol_r_control),
1076 SND_SOC_DAPM_SWITCH("HPOVOL L", RT5651_PWR_VOL,
1077 RT5651_PWR_HV_L_BIT, 0, &hpovol_l_control),
1078 SND_SOC_DAPM_SWITCH("HPOVOL R", RT5651_PWR_VOL,
1079 RT5651_PWR_HV_R_BIT, 0, &hpovol_r_control),
1080 SND_SOC_DAPM_PGA("INL1", RT5651_PWR_VOL,
1081 RT5651_PWR_IN1_L_BIT, 0, NULL, 0),
1082 SND_SOC_DAPM_PGA("INR1", RT5651_PWR_VOL,
1083 RT5651_PWR_IN1_R_BIT, 0, NULL, 0),
1084 SND_SOC_DAPM_PGA("INL2", RT5651_PWR_VOL,
1085 RT5651_PWR_IN2_L_BIT, 0, NULL, 0),
1086 SND_SOC_DAPM_PGA("INR2", RT5651_PWR_VOL,
1087 RT5651_PWR_IN2_R_BIT, 0, NULL, 0),
1088 /* HPO/LOUT/Mono Mixer */
1089 SND_SOC_DAPM_MIXER("HPOL MIX", SND_SOC_NOPM, 0, 0,
1090 rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)),
1091 SND_SOC_DAPM_MIXER("HPOR MIX", SND_SOC_NOPM, 0, 0,
1092 rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)),
1093 SND_SOC_DAPM_SUPPLY("HP L Amp", RT5651_PWR_ANLG1,
1094 RT5651_PWR_HP_L_BIT, 0, NULL, 0),
1095 SND_SOC_DAPM_SUPPLY("HP R Amp", RT5651_PWR_ANLG1,
1096 RT5651_PWR_HP_R_BIT, 0, NULL, 0),
1097 SND_SOC_DAPM_MIXER("LOUT MIX", RT5651_PWR_ANLG1, RT5651_PWR_LM_BIT, 0,
1098 rt5651_lout_mix, ARRAY_SIZE(rt5651_lout_mix)),
1099
1100 SND_SOC_DAPM_SUPPLY("Amp Power", RT5651_PWR_ANLG1,
1101 RT5651_PWR_HA_BIT, 0, rt5651_amp_power_event,
1102 SND_SOC_DAPM_POST_PMU),
1103 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5651_hp_event,
1104 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1105 SND_SOC_DAPM_SWITCH("HPO L Playback", SND_SOC_NOPM, 0, 0,
1106 &hpo_l_mute_control),
1107 SND_SOC_DAPM_SWITCH("HPO R Playback", SND_SOC_NOPM, 0, 0,
1108 &hpo_r_mute_control),
1109 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
1110 &lout_l_mute_control),
1111 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
1112 &lout_r_mute_control),
1113 SND_SOC_DAPM_POST("HP Post", rt5651_hp_post_event),
1114
1115 /* Output Lines */
1116 SND_SOC_DAPM_OUTPUT("HPOL"),
1117 SND_SOC_DAPM_OUTPUT("HPOR"),
1118 SND_SOC_DAPM_OUTPUT("LOUTL"),
1119 SND_SOC_DAPM_OUTPUT("LOUTR"),
1120 SND_SOC_DAPM_OUTPUT("PDML"),
1121 SND_SOC_DAPM_OUTPUT("PDMR"),
1122 };
1123
1124 static const struct snd_soc_dapm_route rt5651_dapm_routes[] = {
1125 {"Stero1 DAC Power", NULL, "STO1 DAC ASRC"},
1126 {"Stero2 DAC Power", NULL, "STO2 DAC ASRC"},
1127 {"I2S1", NULL, "I2S1 ASRC"},
1128 {"I2S2", NULL, "I2S2 ASRC"},
1129
1130 {"IN1P", NULL, "LDO"},
1131 {"IN2P", NULL, "LDO"},
1132 {"IN3P", NULL, "LDO"},
1133
1134 {"IN1P", NULL, "MIC1"},
1135 {"IN2P", NULL, "MIC2"},
1136 {"IN2N", NULL, "MIC2"},
1137 {"IN3P", NULL, "MIC3"},
1138
1139 {"BST1", NULL, "IN1P"},
1140 {"BST2", NULL, "IN2P"},
1141 {"BST2", NULL, "IN2N"},
1142 {"BST3", NULL, "IN3P"},
1143
1144 {"INL1 VOL", NULL, "IN2P"},
1145 {"INR1 VOL", NULL, "IN2N"},
1146
1147 {"RECMIXL", "INL1 Switch", "INL1 VOL"},
1148 {"RECMIXL", "BST3 Switch", "BST3"},
1149 {"RECMIXL", "BST2 Switch", "BST2"},
1150 {"RECMIXL", "BST1 Switch", "BST1"},
1151
1152 {"RECMIXR", "INR1 Switch", "INR1 VOL"},
1153 {"RECMIXR", "BST3 Switch", "BST3"},
1154 {"RECMIXR", "BST2 Switch", "BST2"},
1155 {"RECMIXR", "BST1 Switch", "BST1"},
1156
1157 {"ADC L", NULL, "RECMIXL"},
1158 {"ADC L", NULL, "ADC L Power"},
1159 {"ADC R", NULL, "RECMIXR"},
1160 {"ADC R", NULL, "ADC R Power"},
1161
1162 {"DMIC L1", NULL, "DMIC CLK"},
1163 {"DMIC R1", NULL, "DMIC CLK"},
1164
1165 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1166 {"Stereo1 ADC L2 Mux", "DD MIX", "DD MIXL"},
1167 {"Stereo1 ADC L1 Mux", "ADC", "ADC L"},
1168 {"Stereo1 ADC L1 Mux", "DD MIX", "DD MIXL"},
1169
1170 {"Stereo1 ADC R1 Mux", "ADC", "ADC R"},
1171 {"Stereo1 ADC R1 Mux", "DD MIX", "DD MIXR"},
1172 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1173 {"Stereo1 ADC R2 Mux", "DD MIX", "DD MIXR"},
1174
1175 {"Stereo2 ADC L2 Mux", "DMIC L", "DMIC L1"},
1176 {"Stereo2 ADC L2 Mux", "DD MIXL", "DD MIXL"},
1177 {"Stereo2 ADC L1 Mux", "DD MIXL", "DD MIXL"},
1178 {"Stereo2 ADC L1 Mux", "ADCL", "ADC L"},
1179
1180 {"Stereo2 ADC R1 Mux", "DD MIXR", "DD MIXR"},
1181 {"Stereo2 ADC R1 Mux", "ADCR", "ADC R"},
1182 {"Stereo2 ADC R2 Mux", "DMIC R", "DMIC R1"},
1183 {"Stereo2 ADC R2 Mux", "DD MIXR", "DD MIXR"},
1184
1185 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1186 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1187 {"Stereo1 ADC MIXL", NULL, "Stereo1 Filter"},
1188 {"Stereo1 Filter", NULL, "ADC ASRC"},
1189
1190 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1191 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1192 {"Stereo1 ADC MIXR", NULL, "Stereo1 Filter"},
1193
1194 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
1195 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
1196 {"Stereo2 ADC MIXL", NULL, "Stereo2 Filter"},
1197 {"Stereo2 Filter", NULL, "ADC ASRC"},
1198
1199 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
1200 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
1201 {"Stereo2 ADC MIXR", NULL, "Stereo2 Filter"},
1202
1203 {"IF1 ADC2", NULL, "Stereo2 ADC MIXL"},
1204 {"IF1 ADC2", NULL, "Stereo2 ADC MIXR"},
1205 {"IF1 ADC1", NULL, "Stereo1 ADC MIXL"},
1206 {"IF1 ADC1", NULL, "Stereo1 ADC MIXR"},
1207
1208 {"IF1 ADC1", NULL, "I2S1"},
1209
1210 {"IF2 ADC", "IF1 ADC1", "IF1 ADC1"},
1211 {"IF2 ADC", "IF1 ADC2", "IF1 ADC2"},
1212 {"IF2 ADC", NULL, "I2S2"},
1213
1214 {"AIF1TX", NULL, "IF1 ADC1"},
1215 {"AIF1TX", NULL, "IF1 ADC2"},
1216 {"AIF2TX", NULL, "IF2 ADC"},
1217
1218 {"IF1 DAC", NULL, "AIF1RX"},
1219 {"IF1 DAC", NULL, "I2S1"},
1220 {"IF2 DAC", NULL, "AIF2RX"},
1221 {"IF2 DAC", NULL, "I2S2"},
1222
1223 {"IF1 DAC1 L", NULL, "IF1 DAC"},
1224 {"IF1 DAC1 R", NULL, "IF1 DAC"},
1225 {"IF1 DAC2 L", NULL, "IF1 DAC"},
1226 {"IF1 DAC2 R", NULL, "IF1 DAC"},
1227 {"IF2 DAC L", NULL, "IF2 DAC"},
1228 {"IF2 DAC R", NULL, "IF2 DAC"},
1229
1230 {"DAC MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1231 {"DAC MIXL", "INF1 Switch", "IF1 DAC1 L"},
1232 {"DAC MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1233 {"DAC MIXR", "INF1 Switch", "IF1 DAC1 R"},
1234
1235 {"Audio DSP", NULL, "DAC MIXL"},
1236 {"Audio DSP", NULL, "DAC MIXR"},
1237
1238 {"DAC L2 Mux", "IF1", "IF1 DAC2 L"},
1239 {"DAC L2 Mux", "IF2", "IF2 DAC L"},
1240 {"DAC L2 Volume", NULL, "DAC L2 Mux"},
1241
1242 {"DAC R2 Mux", "IF1", "IF1 DAC2 R"},
1243 {"DAC R2 Mux", "IF2", "IF2 DAC R"},
1244 {"DAC R2 Volume", NULL, "DAC R2 Mux"},
1245
1246 {"Stereo DAC MIXL", "DAC L1 Switch", "Audio DSP"},
1247 {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
1248 {"Stereo DAC MIXL", "DAC R1 Switch", "DAC MIXR"},
1249 {"Stereo DAC MIXL", NULL, "Stero1 DAC Power"},
1250 {"Stereo DAC MIXL", NULL, "Stero2 DAC Power"},
1251 {"Stereo DAC MIXR", "DAC R1 Switch", "Audio DSP"},
1252 {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
1253 {"Stereo DAC MIXR", "DAC L1 Switch", "DAC MIXL"},
1254 {"Stereo DAC MIXR", NULL, "Stero1 DAC Power"},
1255 {"Stereo DAC MIXR", NULL, "Stero2 DAC Power"},
1256
1257 {"PDM L Mux", "Stereo DAC MIX", "Stereo DAC MIXL"},
1258 {"PDM L Mux", "DD MIX", "DAC MIXL"},
1259 {"PDM R Mux", "Stereo DAC MIX", "Stereo DAC MIXR"},
1260 {"PDM R Mux", "DD MIX", "DAC MIXR"},
1261
1262 {"DAC L1", NULL, "Stereo DAC MIXL"},
1263 {"DAC L1", NULL, "DAC L1 Power"},
1264 {"DAC R1", NULL, "Stereo DAC MIXR"},
1265 {"DAC R1", NULL, "DAC R1 Power"},
1266
1267 {"DD MIXL", "DAC L1 Switch", "DAC MIXL"},
1268 {"DD MIXL", "DAC L2 Switch", "DAC L2 Volume"},
1269 {"DD MIXL", "DAC R2 Switch", "DAC R2 Volume"},
1270 {"DD MIXL", NULL, "Stero2 DAC Power"},
1271
1272 {"DD MIXR", "DAC R1 Switch", "DAC MIXR"},
1273 {"DD MIXR", "DAC R2 Switch", "DAC R2 Volume"},
1274 {"DD MIXR", "DAC L2 Switch", "DAC L2 Volume"},
1275 {"DD MIXR", NULL, "Stero2 DAC Power"},
1276
1277 {"OUT MIXL", "BST1 Switch", "BST1"},
1278 {"OUT MIXL", "BST2 Switch", "BST2"},
1279 {"OUT MIXL", "INL1 Switch", "INL1 VOL"},
1280 {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
1281 {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
1282
1283 {"OUT MIXR", "BST2 Switch", "BST2"},
1284 {"OUT MIXR", "BST1 Switch", "BST1"},
1285 {"OUT MIXR", "INR1 Switch", "INR1 VOL"},
1286 {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
1287 {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
1288
1289 {"HPOVOL L", "Switch", "OUT MIXL"},
1290 {"HPOVOL R", "Switch", "OUT MIXR"},
1291 {"OUTVOL L", "Switch", "OUT MIXL"},
1292 {"OUTVOL R", "Switch", "OUT MIXR"},
1293
1294 {"HPOL MIX", "HPO MIX DAC1 Switch", "DAC L1"},
1295 {"HPOL MIX", "HPO MIX HPVOL Switch", "HPOVOL L"},
1296 {"HPOL MIX", NULL, "HP L Amp"},
1297 {"HPOR MIX", "HPO MIX DAC1 Switch", "DAC R1"},
1298 {"HPOR MIX", "HPO MIX HPVOL Switch", "HPOVOL R"},
1299 {"HPOR MIX", NULL, "HP R Amp"},
1300
1301 {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
1302 {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
1303 {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
1304 {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
1305
1306 {"HP Amp", NULL, "HPOL MIX"},
1307 {"HP Amp", NULL, "HPOR MIX"},
1308 {"HP Amp", NULL, "Amp Power"},
1309 {"HPO L Playback", "Switch", "HP Amp"},
1310 {"HPO R Playback", "Switch", "HP Amp"},
1311 {"HPOL", NULL, "HPO L Playback"},
1312 {"HPOR", NULL, "HPO R Playback"},
1313
1314 {"LOUT L Playback", "Switch", "LOUT MIX"},
1315 {"LOUT R Playback", "Switch", "LOUT MIX"},
1316 {"LOUTL", NULL, "LOUT L Playback"},
1317 {"LOUTL", NULL, "Amp Power"},
1318 {"LOUTR", NULL, "LOUT R Playback"},
1319 {"LOUTR", NULL, "Amp Power"},
1320
1321 {"PDML", NULL, "PDM L Mux"},
1322 {"PDMR", NULL, "PDM R Mux"},
1323 };
1324
rt5651_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1325 static int rt5651_hw_params(struct snd_pcm_substream *substream,
1326 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1327 {
1328 struct snd_soc_component *component = dai->component;
1329 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
1330 unsigned int val_len = 0, val_clk, mask_clk;
1331 int pre_div, bclk_ms, frame_size;
1332
1333 rt5651->lrck[dai->id] = params_rate(params);
1334 pre_div = rl6231_get_clk_info(rt5651->sysclk, rt5651->lrck[dai->id]);
1335
1336 if (pre_div < 0) {
1337 dev_err(component->dev, "Unsupported clock setting\n");
1338 return -EINVAL;
1339 }
1340 frame_size = snd_soc_params_to_frame_size(params);
1341 if (frame_size < 0) {
1342 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
1343 return -EINVAL;
1344 }
1345 bclk_ms = frame_size > 32 ? 1 : 0;
1346 rt5651->bclk[dai->id] = rt5651->lrck[dai->id] * (32 << bclk_ms);
1347
1348 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
1349 rt5651->bclk[dai->id], rt5651->lrck[dai->id]);
1350 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1351 bclk_ms, pre_div, dai->id);
1352
1353 switch (params_width(params)) {
1354 case 16:
1355 break;
1356 case 20:
1357 val_len |= RT5651_I2S_DL_20;
1358 break;
1359 case 24:
1360 val_len |= RT5651_I2S_DL_24;
1361 break;
1362 case 8:
1363 val_len |= RT5651_I2S_DL_8;
1364 break;
1365 default:
1366 return -EINVAL;
1367 }
1368
1369 switch (dai->id) {
1370 case RT5651_AIF1:
1371 mask_clk = RT5651_I2S_PD1_MASK;
1372 val_clk = pre_div << RT5651_I2S_PD1_SFT;
1373 snd_soc_component_update_bits(component, RT5651_I2S1_SDP,
1374 RT5651_I2S_DL_MASK, val_len);
1375 snd_soc_component_update_bits(component, RT5651_ADDA_CLK1, mask_clk, val_clk);
1376 break;
1377 case RT5651_AIF2:
1378 mask_clk = RT5651_I2S_BCLK_MS2_MASK | RT5651_I2S_PD2_MASK;
1379 val_clk = pre_div << RT5651_I2S_PD2_SFT;
1380 snd_soc_component_update_bits(component, RT5651_I2S2_SDP,
1381 RT5651_I2S_DL_MASK, val_len);
1382 snd_soc_component_update_bits(component, RT5651_ADDA_CLK1, mask_clk, val_clk);
1383 break;
1384 default:
1385 dev_err(component->dev, "Wrong dai->id: %d\n", dai->id);
1386 return -EINVAL;
1387 }
1388
1389 return 0;
1390 }
1391
rt5651_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)1392 static int rt5651_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1393 {
1394 struct snd_soc_component *component = dai->component;
1395 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
1396 unsigned int reg_val = 0;
1397
1398 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1399 case SND_SOC_DAIFMT_CBM_CFM:
1400 rt5651->master[dai->id] = 1;
1401 break;
1402 case SND_SOC_DAIFMT_CBS_CFS:
1403 reg_val |= RT5651_I2S_MS_S;
1404 rt5651->master[dai->id] = 0;
1405 break;
1406 default:
1407 return -EINVAL;
1408 }
1409
1410 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1411 case SND_SOC_DAIFMT_NB_NF:
1412 break;
1413 case SND_SOC_DAIFMT_IB_NF:
1414 reg_val |= RT5651_I2S_BP_INV;
1415 break;
1416 default:
1417 return -EINVAL;
1418 }
1419
1420 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1421 case SND_SOC_DAIFMT_I2S:
1422 break;
1423 case SND_SOC_DAIFMT_LEFT_J:
1424 reg_val |= RT5651_I2S_DF_LEFT;
1425 break;
1426 case SND_SOC_DAIFMT_DSP_A:
1427 reg_val |= RT5651_I2S_DF_PCM_A;
1428 break;
1429 case SND_SOC_DAIFMT_DSP_B:
1430 reg_val |= RT5651_I2S_DF_PCM_B;
1431 break;
1432 default:
1433 return -EINVAL;
1434 }
1435
1436 switch (dai->id) {
1437 case RT5651_AIF1:
1438 snd_soc_component_update_bits(component, RT5651_I2S1_SDP,
1439 RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK |
1440 RT5651_I2S_DF_MASK, reg_val);
1441 break;
1442 case RT5651_AIF2:
1443 snd_soc_component_update_bits(component, RT5651_I2S2_SDP,
1444 RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK |
1445 RT5651_I2S_DF_MASK, reg_val);
1446 break;
1447 default:
1448 dev_err(component->dev, "Wrong dai->id: %d\n", dai->id);
1449 return -EINVAL;
1450 }
1451 return 0;
1452 }
1453
rt5651_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)1454 static int rt5651_set_dai_sysclk(struct snd_soc_dai *dai,
1455 int clk_id, unsigned int freq, int dir)
1456 {
1457 struct snd_soc_component *component = dai->component;
1458 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
1459 unsigned int reg_val = 0;
1460 unsigned int pll_bit = 0;
1461
1462 if (freq == rt5651->sysclk && clk_id == rt5651->sysclk_src)
1463 return 0;
1464
1465 switch (clk_id) {
1466 case RT5651_SCLK_S_MCLK:
1467 reg_val |= RT5651_SCLK_SRC_MCLK;
1468 break;
1469 case RT5651_SCLK_S_PLL1:
1470 reg_val |= RT5651_SCLK_SRC_PLL1;
1471 pll_bit |= RT5651_PWR_PLL;
1472 break;
1473 case RT5651_SCLK_S_RCCLK:
1474 reg_val |= RT5651_SCLK_SRC_RCCLK;
1475 break;
1476 default:
1477 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
1478 return -EINVAL;
1479 }
1480 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
1481 RT5651_PWR_PLL, pll_bit);
1482 snd_soc_component_update_bits(component, RT5651_GLB_CLK,
1483 RT5651_SCLK_SRC_MASK, reg_val);
1484 rt5651->sysclk = freq;
1485 rt5651->sysclk_src = clk_id;
1486
1487 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
1488
1489 return 0;
1490 }
1491
rt5651_set_dai_pll(struct snd_soc_dai * dai,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)1492 static int rt5651_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
1493 unsigned int freq_in, unsigned int freq_out)
1494 {
1495 struct snd_soc_component *component = dai->component;
1496 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
1497 struct rl6231_pll_code pll_code;
1498 int ret;
1499
1500 if (source == rt5651->pll_src && freq_in == rt5651->pll_in &&
1501 freq_out == rt5651->pll_out)
1502 return 0;
1503
1504 if (!freq_in || !freq_out) {
1505 dev_dbg(component->dev, "PLL disabled\n");
1506
1507 rt5651->pll_in = 0;
1508 rt5651->pll_out = 0;
1509 snd_soc_component_update_bits(component, RT5651_GLB_CLK,
1510 RT5651_SCLK_SRC_MASK, RT5651_SCLK_SRC_MCLK);
1511 return 0;
1512 }
1513
1514 switch (source) {
1515 case RT5651_PLL1_S_MCLK:
1516 snd_soc_component_update_bits(component, RT5651_GLB_CLK,
1517 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_MCLK);
1518 break;
1519 case RT5651_PLL1_S_BCLK1:
1520 snd_soc_component_update_bits(component, RT5651_GLB_CLK,
1521 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK1);
1522 break;
1523 case RT5651_PLL1_S_BCLK2:
1524 snd_soc_component_update_bits(component, RT5651_GLB_CLK,
1525 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK2);
1526 break;
1527 default:
1528 dev_err(component->dev, "Unknown PLL source %d\n", source);
1529 return -EINVAL;
1530 }
1531
1532 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1533 if (ret < 0) {
1534 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
1535 return ret;
1536 }
1537
1538 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
1539 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
1540 pll_code.n_code, pll_code.k_code);
1541
1542 snd_soc_component_write(component, RT5651_PLL_CTRL1,
1543 pll_code.n_code << RT5651_PLL_N_SFT | pll_code.k_code);
1544 snd_soc_component_write(component, RT5651_PLL_CTRL2,
1545 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5651_PLL_M_SFT |
1546 pll_code.m_bp << RT5651_PLL_M_BP_SFT);
1547
1548 rt5651->pll_in = freq_in;
1549 rt5651->pll_out = freq_out;
1550 rt5651->pll_src = source;
1551
1552 return 0;
1553 }
1554
rt5651_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)1555 static int rt5651_set_bias_level(struct snd_soc_component *component,
1556 enum snd_soc_bias_level level)
1557 {
1558 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
1559
1560 switch (level) {
1561 case SND_SOC_BIAS_PREPARE:
1562 if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
1563 if (!IS_ERR(rt5651->mclk))
1564 clk_prepare_enable(rt5651->mclk);
1565 if (snd_soc_component_read(component, RT5651_PLL_MODE_1) & 0x9200)
1566 snd_soc_component_update_bits(component, RT5651_D_MISC,
1567 0xc00, 0xc00);
1568 }
1569 break;
1570 case SND_SOC_BIAS_STANDBY:
1571 if (SND_SOC_BIAS_OFF == snd_soc_component_get_bias_level(component)) {
1572 snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
1573 RT5651_PWR_VREF1 | RT5651_PWR_MB |
1574 RT5651_PWR_BG | RT5651_PWR_VREF2,
1575 RT5651_PWR_VREF1 | RT5651_PWR_MB |
1576 RT5651_PWR_BG | RT5651_PWR_VREF2);
1577 usleep_range(10000, 15000);
1578 snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
1579 RT5651_PWR_FV1 | RT5651_PWR_FV2,
1580 RT5651_PWR_FV1 | RT5651_PWR_FV2);
1581 snd_soc_component_update_bits(component, RT5651_D_MISC, 0x1, 0x1);
1582 } else if (SND_SOC_BIAS_PREPARE == snd_soc_component_get_bias_level(component)) {
1583 if (!IS_ERR(rt5651->mclk))
1584 clk_disable_unprepare(rt5651->mclk);
1585 }
1586 break;
1587
1588 case SND_SOC_BIAS_OFF:
1589 snd_soc_component_write(component, RT5651_D_MISC, 0x0010);
1590 snd_soc_component_write(component, RT5651_PWR_DIG1, 0x0000);
1591 snd_soc_component_write(component, RT5651_PWR_DIG2, 0x0000);
1592 snd_soc_component_write(component, RT5651_PWR_VOL, 0x0000);
1593 snd_soc_component_write(component, RT5651_PWR_MIXER, 0x0000);
1594 /* Do not touch the LDO voltage select bits on bias-off */
1595 snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
1596 ~RT5651_PWR_LDO_DVO_MASK, 0);
1597 /* Leave PLL1 and jack-detect power as is, all others off */
1598 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
1599 ~(RT5651_PWR_PLL | RT5651_PWR_JD_M), 0);
1600 break;
1601
1602 default:
1603 break;
1604 }
1605
1606 return 0;
1607 }
1608
rt5651_enable_micbias1_for_ovcd(struct snd_soc_component * component)1609 static void rt5651_enable_micbias1_for_ovcd(struct snd_soc_component *component)
1610 {
1611 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1612
1613 snd_soc_dapm_mutex_lock(dapm);
1614 snd_soc_dapm_force_enable_pin_unlocked(dapm, "LDO");
1615 snd_soc_dapm_force_enable_pin_unlocked(dapm, "micbias1");
1616 /* OVCD is unreliable when used with RCCLK as sysclk-source */
1617 snd_soc_dapm_force_enable_pin_unlocked(dapm, "Platform Clock");
1618 snd_soc_dapm_sync_unlocked(dapm);
1619 snd_soc_dapm_mutex_unlock(dapm);
1620 }
1621
rt5651_disable_micbias1_for_ovcd(struct snd_soc_component * component)1622 static void rt5651_disable_micbias1_for_ovcd(struct snd_soc_component *component)
1623 {
1624 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1625
1626 snd_soc_dapm_mutex_lock(dapm);
1627 snd_soc_dapm_disable_pin_unlocked(dapm, "Platform Clock");
1628 snd_soc_dapm_disable_pin_unlocked(dapm, "micbias1");
1629 snd_soc_dapm_disable_pin_unlocked(dapm, "LDO");
1630 snd_soc_dapm_sync_unlocked(dapm);
1631 snd_soc_dapm_mutex_unlock(dapm);
1632 }
1633
rt5651_enable_micbias1_ovcd_irq(struct snd_soc_component * component)1634 static void rt5651_enable_micbias1_ovcd_irq(struct snd_soc_component *component)
1635 {
1636 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
1637
1638 snd_soc_component_update_bits(component, RT5651_IRQ_CTRL2,
1639 RT5651_IRQ_MB1_OC_MASK, RT5651_IRQ_MB1_OC_NOR);
1640 rt5651->ovcd_irq_enabled = true;
1641 }
1642
rt5651_disable_micbias1_ovcd_irq(struct snd_soc_component * component)1643 static void rt5651_disable_micbias1_ovcd_irq(struct snd_soc_component *component)
1644 {
1645 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
1646
1647 snd_soc_component_update_bits(component, RT5651_IRQ_CTRL2,
1648 RT5651_IRQ_MB1_OC_MASK, RT5651_IRQ_MB1_OC_BP);
1649 rt5651->ovcd_irq_enabled = false;
1650 }
1651
rt5651_clear_micbias1_ovcd(struct snd_soc_component * component)1652 static void rt5651_clear_micbias1_ovcd(struct snd_soc_component *component)
1653 {
1654 snd_soc_component_update_bits(component, RT5651_IRQ_CTRL2,
1655 RT5651_MB1_OC_CLR, 0);
1656 }
1657
rt5651_micbias1_ovcd(struct snd_soc_component * component)1658 static bool rt5651_micbias1_ovcd(struct snd_soc_component *component)
1659 {
1660 int val;
1661
1662 val = snd_soc_component_read(component, RT5651_IRQ_CTRL2);
1663 dev_dbg(component->dev, "irq ctrl2 %#04x\n", val);
1664
1665 return (val & RT5651_MB1_OC_CLR);
1666 }
1667
rt5651_jack_inserted(struct snd_soc_component * component)1668 static bool rt5651_jack_inserted(struct snd_soc_component *component)
1669 {
1670 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
1671 int val;
1672
1673 if (rt5651->gpiod_hp_det) {
1674 val = gpiod_get_value_cansleep(rt5651->gpiod_hp_det);
1675 dev_dbg(component->dev, "jack-detect gpio %d\n", val);
1676 return val;
1677 }
1678
1679 val = snd_soc_component_read(component, RT5651_INT_IRQ_ST);
1680 dev_dbg(component->dev, "irq status %#04x\n", val);
1681
1682 switch (rt5651->jd_src) {
1683 case RT5651_JD1_1:
1684 val &= 0x1000;
1685 break;
1686 case RT5651_JD1_2:
1687 val &= 0x2000;
1688 break;
1689 case RT5651_JD2:
1690 val &= 0x4000;
1691 break;
1692 default:
1693 break;
1694 }
1695
1696 if (rt5651->jd_active_high)
1697 return val != 0;
1698 else
1699 return val == 0;
1700 }
1701
1702 /* Jack detect and button-press timings */
1703 #define JACK_SETTLE_TIME 100 /* milli seconds */
1704 #define JACK_DETECT_COUNT 5
1705 #define JACK_DETECT_MAXCOUNT 20 /* Aprox. 2 seconds worth of tries */
1706 #define JACK_UNPLUG_TIME 80 /* milli seconds */
1707 #define BP_POLL_TIME 10 /* milli seconds */
1708 #define BP_POLL_MAXCOUNT 200 /* assume something is wrong after this */
1709 #define BP_THRESHOLD 3
1710
rt5651_start_button_press_work(struct snd_soc_component * component)1711 static void rt5651_start_button_press_work(struct snd_soc_component *component)
1712 {
1713 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
1714
1715 rt5651->poll_count = 0;
1716 rt5651->press_count = 0;
1717 rt5651->release_count = 0;
1718 rt5651->pressed = false;
1719 rt5651->press_reported = false;
1720 rt5651_clear_micbias1_ovcd(component);
1721 schedule_delayed_work(&rt5651->bp_work, msecs_to_jiffies(BP_POLL_TIME));
1722 }
1723
rt5651_button_press_work(struct work_struct * work)1724 static void rt5651_button_press_work(struct work_struct *work)
1725 {
1726 struct rt5651_priv *rt5651 =
1727 container_of(work, struct rt5651_priv, bp_work.work);
1728 struct snd_soc_component *component = rt5651->component;
1729
1730 /* Check the jack was not removed underneath us */
1731 if (!rt5651_jack_inserted(component))
1732 return;
1733
1734 if (rt5651_micbias1_ovcd(component)) {
1735 rt5651->release_count = 0;
1736 rt5651->press_count++;
1737 /* Remember till after JACK_UNPLUG_TIME wait */
1738 if (rt5651->press_count >= BP_THRESHOLD)
1739 rt5651->pressed = true;
1740 rt5651_clear_micbias1_ovcd(component);
1741 } else {
1742 rt5651->press_count = 0;
1743 rt5651->release_count++;
1744 }
1745
1746 /*
1747 * The pins get temporarily shorted on jack unplug, so we poll for
1748 * at least JACK_UNPLUG_TIME milli-seconds before reporting a press.
1749 */
1750 rt5651->poll_count++;
1751 if (rt5651->poll_count < (JACK_UNPLUG_TIME / BP_POLL_TIME)) {
1752 schedule_delayed_work(&rt5651->bp_work,
1753 msecs_to_jiffies(BP_POLL_TIME));
1754 return;
1755 }
1756
1757 if (rt5651->pressed && !rt5651->press_reported) {
1758 dev_dbg(component->dev, "headset button press\n");
1759 snd_soc_jack_report(rt5651->hp_jack, SND_JACK_BTN_0,
1760 SND_JACK_BTN_0);
1761 rt5651->press_reported = true;
1762 }
1763
1764 if (rt5651->release_count >= BP_THRESHOLD) {
1765 if (rt5651->press_reported) {
1766 dev_dbg(component->dev, "headset button release\n");
1767 snd_soc_jack_report(rt5651->hp_jack, 0, SND_JACK_BTN_0);
1768 }
1769 /* Re-enable OVCD IRQ to detect next press */
1770 rt5651_enable_micbias1_ovcd_irq(component);
1771 return; /* Stop polling */
1772 }
1773
1774 schedule_delayed_work(&rt5651->bp_work, msecs_to_jiffies(BP_POLL_TIME));
1775 }
1776
rt5651_detect_headset(struct snd_soc_component * component)1777 static int rt5651_detect_headset(struct snd_soc_component *component)
1778 {
1779 int i, headset_count = 0, headphone_count = 0;
1780
1781 /*
1782 * We get the insertion event before the jack is fully inserted at which
1783 * point the second ring on a TRRS connector may short the 2nd ring and
1784 * sleeve contacts, also the overcurrent detection is not entirely
1785 * reliable. So we try several times with a wait in between until we
1786 * detect the same type JACK_DETECT_COUNT times in a row.
1787 */
1788 for (i = 0; i < JACK_DETECT_MAXCOUNT; i++) {
1789 /* Clear any previous over-current status flag */
1790 rt5651_clear_micbias1_ovcd(component);
1791
1792 msleep(JACK_SETTLE_TIME);
1793
1794 /* Check the jack is still connected before checking ovcd */
1795 if (!rt5651_jack_inserted(component))
1796 return 0;
1797
1798 if (rt5651_micbias1_ovcd(component)) {
1799 /*
1800 * Over current detected, there is a short between the
1801 * 2nd ring contact and the ground, so a TRS connector
1802 * without a mic contact and thus plain headphones.
1803 */
1804 dev_dbg(component->dev, "mic-gnd shorted\n");
1805 headset_count = 0;
1806 headphone_count++;
1807 if (headphone_count == JACK_DETECT_COUNT)
1808 return SND_JACK_HEADPHONE;
1809 } else {
1810 dev_dbg(component->dev, "mic-gnd open\n");
1811 headphone_count = 0;
1812 headset_count++;
1813 if (headset_count == JACK_DETECT_COUNT)
1814 return SND_JACK_HEADSET;
1815 }
1816 }
1817
1818 dev_err(component->dev, "Error detecting headset vs headphones, bad contact?, assuming headphones\n");
1819 return SND_JACK_HEADPHONE;
1820 }
1821
rt5651_support_button_press(struct rt5651_priv * rt5651)1822 static bool rt5651_support_button_press(struct rt5651_priv *rt5651)
1823 {
1824 if (!rt5651->hp_jack)
1825 return false;
1826
1827 /* Button press support only works with internal jack-detection */
1828 return (rt5651->hp_jack->status & SND_JACK_MICROPHONE) &&
1829 rt5651->gpiod_hp_det == NULL;
1830 }
1831
rt5651_jack_detect_work(struct work_struct * work)1832 static void rt5651_jack_detect_work(struct work_struct *work)
1833 {
1834 struct rt5651_priv *rt5651 =
1835 container_of(work, struct rt5651_priv, jack_detect_work);
1836 struct snd_soc_component *component = rt5651->component;
1837 int report = 0;
1838
1839 if (!rt5651_jack_inserted(component)) {
1840 /* Jack removed, or spurious IRQ? */
1841 if (rt5651->hp_jack->status & SND_JACK_HEADPHONE) {
1842 if (rt5651->hp_jack->status & SND_JACK_MICROPHONE) {
1843 cancel_delayed_work_sync(&rt5651->bp_work);
1844 rt5651_disable_micbias1_ovcd_irq(component);
1845 rt5651_disable_micbias1_for_ovcd(component);
1846 }
1847 snd_soc_jack_report(rt5651->hp_jack, 0,
1848 SND_JACK_HEADSET | SND_JACK_BTN_0);
1849 dev_dbg(component->dev, "jack unplugged\n");
1850 }
1851 } else if (!(rt5651->hp_jack->status & SND_JACK_HEADPHONE)) {
1852 /* Jack inserted */
1853 WARN_ON(rt5651->ovcd_irq_enabled);
1854 rt5651_enable_micbias1_for_ovcd(component);
1855 report = rt5651_detect_headset(component);
1856 dev_dbg(component->dev, "detect report %#02x\n", report);
1857 snd_soc_jack_report(rt5651->hp_jack, report, SND_JACK_HEADSET);
1858 if (rt5651_support_button_press(rt5651)) {
1859 /* Enable ovcd IRQ for button press detect. */
1860 rt5651_enable_micbias1_ovcd_irq(component);
1861 } else {
1862 /* No more need for overcurrent detect. */
1863 rt5651_disable_micbias1_for_ovcd(component);
1864 }
1865 } else if (rt5651->ovcd_irq_enabled && rt5651_micbias1_ovcd(component)) {
1866 dev_dbg(component->dev, "OVCD IRQ\n");
1867
1868 /*
1869 * The ovcd IRQ keeps firing while the button is pressed, so
1870 * we disable it and start polling the button until released.
1871 *
1872 * The disable will make the IRQ pin 0 again and since we get
1873 * IRQs on both edges (so as to detect both jack plugin and
1874 * unplug) this means we will immediately get another IRQ.
1875 * The ovcd_irq_enabled check above makes the 2ND IRQ a NOP.
1876 */
1877 rt5651_disable_micbias1_ovcd_irq(component);
1878 rt5651_start_button_press_work(component);
1879
1880 /*
1881 * If the jack-detect IRQ flag goes high (unplug) after our
1882 * above rt5651_jack_inserted() check and before we have
1883 * disabled the OVCD IRQ, the IRQ pin will stay high and as
1884 * we react to edges, we miss the unplug event -> recheck.
1885 */
1886 queue_work(system_long_wq, &rt5651->jack_detect_work);
1887 }
1888 }
1889
rt5651_irq(int irq,void * data)1890 static irqreturn_t rt5651_irq(int irq, void *data)
1891 {
1892 struct rt5651_priv *rt5651 = data;
1893
1894 queue_work(system_power_efficient_wq, &rt5651->jack_detect_work);
1895
1896 return IRQ_HANDLED;
1897 }
1898
rt5651_cancel_work(void * data)1899 static void rt5651_cancel_work(void *data)
1900 {
1901 struct rt5651_priv *rt5651 = data;
1902
1903 cancel_work_sync(&rt5651->jack_detect_work);
1904 cancel_delayed_work_sync(&rt5651->bp_work);
1905 }
1906
rt5651_enable_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * hp_jack,struct gpio_desc * gpiod_hp_det)1907 static void rt5651_enable_jack_detect(struct snd_soc_component *component,
1908 struct snd_soc_jack *hp_jack,
1909 struct gpio_desc *gpiod_hp_det)
1910 {
1911 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
1912 bool using_internal_jack_detect = true;
1913
1914 /* Select jack detect source */
1915 switch (rt5651->jd_src) {
1916 case RT5651_JD_NULL:
1917 rt5651->gpiod_hp_det = gpiod_hp_det;
1918 if (!rt5651->gpiod_hp_det)
1919 return; /* No jack detect */
1920 using_internal_jack_detect = false;
1921 break;
1922 case RT5651_JD1_1:
1923 snd_soc_component_update_bits(component, RT5651_JD_CTRL2,
1924 RT5651_JD_TRG_SEL_MASK, RT5651_JD_TRG_SEL_JD1_1);
1925 /* active-low is normal, set inv flag for active-high */
1926 if (rt5651->jd_active_high)
1927 snd_soc_component_update_bits(component,
1928 RT5651_IRQ_CTRL1,
1929 RT5651_JD1_1_IRQ_EN | RT5651_JD1_1_INV,
1930 RT5651_JD1_1_IRQ_EN | RT5651_JD1_1_INV);
1931 else
1932 snd_soc_component_update_bits(component,
1933 RT5651_IRQ_CTRL1,
1934 RT5651_JD1_1_IRQ_EN | RT5651_JD1_1_INV,
1935 RT5651_JD1_1_IRQ_EN);
1936 break;
1937 case RT5651_JD1_2:
1938 snd_soc_component_update_bits(component, RT5651_JD_CTRL2,
1939 RT5651_JD_TRG_SEL_MASK, RT5651_JD_TRG_SEL_JD1_2);
1940 /* active-low is normal, set inv flag for active-high */
1941 if (rt5651->jd_active_high)
1942 snd_soc_component_update_bits(component,
1943 RT5651_IRQ_CTRL1,
1944 RT5651_JD1_2_IRQ_EN | RT5651_JD1_2_INV,
1945 RT5651_JD1_2_IRQ_EN | RT5651_JD1_2_INV);
1946 else
1947 snd_soc_component_update_bits(component,
1948 RT5651_IRQ_CTRL1,
1949 RT5651_JD1_2_IRQ_EN | RT5651_JD1_2_INV,
1950 RT5651_JD1_2_IRQ_EN);
1951 break;
1952 case RT5651_JD2:
1953 snd_soc_component_update_bits(component, RT5651_JD_CTRL2,
1954 RT5651_JD_TRG_SEL_MASK, RT5651_JD_TRG_SEL_JD2);
1955 /* active-low is normal, set inv flag for active-high */
1956 if (rt5651->jd_active_high)
1957 snd_soc_component_update_bits(component,
1958 RT5651_IRQ_CTRL1,
1959 RT5651_JD2_IRQ_EN | RT5651_JD2_INV,
1960 RT5651_JD2_IRQ_EN | RT5651_JD2_INV);
1961 else
1962 snd_soc_component_update_bits(component,
1963 RT5651_IRQ_CTRL1,
1964 RT5651_JD2_IRQ_EN | RT5651_JD2_INV,
1965 RT5651_JD2_IRQ_EN);
1966 break;
1967 default:
1968 dev_err(component->dev, "Currently only JD1_1 / JD1_2 / JD2 are supported\n");
1969 return;
1970 }
1971
1972 if (using_internal_jack_detect) {
1973 /* IRQ output on GPIO1 */
1974 snd_soc_component_update_bits(component, RT5651_GPIO_CTRL1,
1975 RT5651_GP1_PIN_MASK, RT5651_GP1_PIN_IRQ);
1976
1977 /* Enable jack detect power */
1978 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
1979 RT5651_PWR_JD_M, RT5651_PWR_JD_M);
1980 }
1981
1982 /* Set OVCD threshold current and scale-factor */
1983 snd_soc_component_write(component, RT5651_PR_BASE + RT5651_BIAS_CUR4,
1984 0xa800 | rt5651->ovcd_sf);
1985
1986 snd_soc_component_update_bits(component, RT5651_MICBIAS,
1987 RT5651_MIC1_OVCD_MASK |
1988 RT5651_MIC1_OVTH_MASK |
1989 RT5651_PWR_CLK12M_MASK |
1990 RT5651_PWR_MB_MASK,
1991 RT5651_MIC1_OVCD_EN |
1992 rt5651->ovcd_th |
1993 RT5651_PWR_MB_PU |
1994 RT5651_PWR_CLK12M_PU);
1995
1996 /*
1997 * The over-current-detect is only reliable in detecting the absence
1998 * of over-current, when the mic-contact in the jack is short-circuited,
1999 * the hardware periodically retries if it can apply the bias-current
2000 * leading to the ovcd status flip-flopping 1-0-1 with it being 0 about
2001 * 10% of the time, as we poll the ovcd status bit we might hit that
2002 * 10%, so we enable sticky mode and when checking OVCD we clear the
2003 * status, msleep() a bit and then check to get a reliable reading.
2004 */
2005 snd_soc_component_update_bits(component, RT5651_IRQ_CTRL2,
2006 RT5651_MB1_OC_STKY_MASK, RT5651_MB1_OC_STKY_EN);
2007
2008 rt5651->hp_jack = hp_jack;
2009 if (rt5651_support_button_press(rt5651)) {
2010 rt5651_enable_micbias1_for_ovcd(component);
2011 rt5651_enable_micbias1_ovcd_irq(component);
2012 }
2013
2014 enable_irq(rt5651->irq);
2015 /* sync initial jack state */
2016 queue_work(system_power_efficient_wq, &rt5651->jack_detect_work);
2017 }
2018
rt5651_disable_jack_detect(struct snd_soc_component * component)2019 static void rt5651_disable_jack_detect(struct snd_soc_component *component)
2020 {
2021 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
2022
2023 disable_irq(rt5651->irq);
2024 rt5651_cancel_work(rt5651);
2025
2026 if (rt5651_support_button_press(rt5651)) {
2027 rt5651_disable_micbias1_ovcd_irq(component);
2028 rt5651_disable_micbias1_for_ovcd(component);
2029 snd_soc_jack_report(rt5651->hp_jack, 0, SND_JACK_BTN_0);
2030 }
2031
2032 rt5651->hp_jack = NULL;
2033 }
2034
rt5651_set_jack(struct snd_soc_component * component,struct snd_soc_jack * jack,void * data)2035 static int rt5651_set_jack(struct snd_soc_component *component,
2036 struct snd_soc_jack *jack, void *data)
2037 {
2038 if (jack)
2039 rt5651_enable_jack_detect(component, jack, data);
2040 else
2041 rt5651_disable_jack_detect(component);
2042
2043 return 0;
2044 }
2045
2046 /*
2047 * Note on some platforms the platform code may need to add device-properties,
2048 * rather then relying only on properties set by the firmware. Therefor the
2049 * property parsing MUST be done from the component driver's probe function,
2050 * rather then from the i2c driver's probe function, so that the platform-code
2051 * can attach extra properties before calling snd_soc_register_card().
2052 */
rt5651_apply_properties(struct snd_soc_component * component)2053 static void rt5651_apply_properties(struct snd_soc_component *component)
2054 {
2055 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
2056 u32 val;
2057
2058 if (device_property_read_bool(component->dev, "realtek,in2-differential"))
2059 snd_soc_component_update_bits(component, RT5651_IN1_IN2,
2060 RT5651_IN_DF2, RT5651_IN_DF2);
2061
2062 if (device_property_read_bool(component->dev, "realtek,dmic-en"))
2063 snd_soc_component_update_bits(component, RT5651_GPIO_CTRL1,
2064 RT5651_GP2_PIN_MASK, RT5651_GP2_PIN_DMIC1_SCL);
2065
2066 if (device_property_read_u32(component->dev,
2067 "realtek,jack-detect-source", &val) == 0)
2068 rt5651->jd_src = val;
2069
2070 if (device_property_read_bool(component->dev, "realtek,jack-detect-not-inverted"))
2071 rt5651->jd_active_high = true;
2072
2073 /*
2074 * Testing on various boards has shown that good defaults for the OVCD
2075 * threshold and scale-factor are 2000µA and 0.75. For an effective
2076 * limit of 1500µA, this seems to be more reliable then 1500µA and 1.0.
2077 */
2078 rt5651->ovcd_th = RT5651_MIC1_OVTH_2000UA;
2079 rt5651->ovcd_sf = RT5651_MIC_OVCD_SF_0P75;
2080
2081 if (device_property_read_u32(component->dev,
2082 "realtek,over-current-threshold-microamp", &val) == 0) {
2083 switch (val) {
2084 case 600:
2085 rt5651->ovcd_th = RT5651_MIC1_OVTH_600UA;
2086 break;
2087 case 1500:
2088 rt5651->ovcd_th = RT5651_MIC1_OVTH_1500UA;
2089 break;
2090 case 2000:
2091 rt5651->ovcd_th = RT5651_MIC1_OVTH_2000UA;
2092 break;
2093 default:
2094 dev_warn(component->dev, "Warning: Invalid over-current-threshold-microamp value: %d, defaulting to 2000uA\n",
2095 val);
2096 }
2097 }
2098
2099 if (device_property_read_u32(component->dev,
2100 "realtek,over-current-scale-factor", &val) == 0) {
2101 if (val <= RT5651_OVCD_SF_1P5)
2102 rt5651->ovcd_sf = val << RT5651_MIC_OVCD_SF_SFT;
2103 else
2104 dev_warn(component->dev, "Warning: Invalid over-current-scale-factor value: %d, defaulting to 0.75\n",
2105 val);
2106 }
2107 }
2108
rt5651_probe(struct snd_soc_component * component)2109 static int rt5651_probe(struct snd_soc_component *component)
2110 {
2111 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
2112
2113 rt5651->component = component;
2114
2115 rt5651->mclk = devm_clk_get(component->dev, "mclk");
2116 if (PTR_ERR(rt5651->mclk) == -EPROBE_DEFER)
2117 return -EPROBE_DEFER;
2118
2119 snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
2120 RT5651_PWR_LDO_DVO_MASK, RT5651_PWR_LDO_DVO_1_2V);
2121
2122 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
2123
2124 rt5651_apply_properties(component);
2125
2126 return 0;
2127 }
2128
rt5651_enable_spk(struct rt5651_priv * rt5651,bool enable)2129 static void rt5651_enable_spk(struct rt5651_priv *rt5651, bool enable)
2130 {
2131 if (!rt5651 || !rt5651->gpiod_spk_ctl)
2132 return;
2133 gpiod_set_value(rt5651->gpiod_spk_ctl, enable);
2134 }
2135
rt5651_mute(struct snd_soc_dai * dai,int mute,int stream)2136 static int rt5651_mute(struct snd_soc_dai *dai, int mute, int stream)
2137 {
2138 struct snd_soc_component *component = dai->component;
2139 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
2140
2141 if (mute)
2142 rt5651_enable_spk(rt5651, false);
2143 else
2144 rt5651_enable_spk(rt5651, true);
2145 return 0;
2146 }
2147
2148 #ifdef CONFIG_PM
rt5651_suspend(struct snd_soc_component * component)2149 static int rt5651_suspend(struct snd_soc_component *component)
2150 {
2151 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
2152
2153 regcache_cache_only(rt5651->regmap, true);
2154 regcache_mark_dirty(rt5651->regmap);
2155 return 0;
2156 }
2157
rt5651_resume(struct snd_soc_component * component)2158 static int rt5651_resume(struct snd_soc_component *component)
2159 {
2160 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
2161
2162 regcache_cache_only(rt5651->regmap, false);
2163 snd_soc_component_cache_sync(component);
2164
2165 return 0;
2166 }
2167 #else
2168 #define rt5651_suspend NULL
2169 #define rt5651_resume NULL
2170 #endif
2171
2172 #define RT5651_STEREO_RATES SNDRV_PCM_RATE_8000_96000
2173 #define RT5651_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2174 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2175
2176 static const struct snd_soc_dai_ops rt5651_aif_dai_ops = {
2177 .hw_params = rt5651_hw_params,
2178 .set_fmt = rt5651_set_dai_fmt,
2179 .set_sysclk = rt5651_set_dai_sysclk,
2180 .set_pll = rt5651_set_dai_pll,
2181 .mute_stream = rt5651_mute,
2182 .no_capture_mute = 1,
2183 };
2184
2185 static struct snd_soc_dai_driver rt5651_dai[] = {
2186 {
2187 .name = "rt5651-aif1",
2188 .id = RT5651_AIF1,
2189 .playback = {
2190 .stream_name = "AIF1 Playback",
2191 .channels_min = 1,
2192 .channels_max = 2,
2193 .rates = RT5651_STEREO_RATES,
2194 .formats = RT5651_FORMATS,
2195 },
2196 .capture = {
2197 .stream_name = "AIF1 Capture",
2198 .channels_min = 1,
2199 .channels_max = 2,
2200 .rates = RT5651_STEREO_RATES,
2201 .formats = RT5651_FORMATS,
2202 },
2203 .ops = &rt5651_aif_dai_ops,
2204 },
2205 {
2206 .name = "rt5651-aif2",
2207 .id = RT5651_AIF2,
2208 .playback = {
2209 .stream_name = "AIF2 Playback",
2210 .channels_min = 1,
2211 .channels_max = 2,
2212 .rates = RT5651_STEREO_RATES,
2213 .formats = RT5651_FORMATS,
2214 },
2215 .capture = {
2216 .stream_name = "AIF2 Capture",
2217 .channels_min = 1,
2218 .channels_max = 2,
2219 .rates = RT5651_STEREO_RATES,
2220 .formats = RT5651_FORMATS,
2221 },
2222 .ops = &rt5651_aif_dai_ops,
2223 },
2224 };
2225
2226 static const struct snd_soc_component_driver soc_component_dev_rt5651 = {
2227 .probe = rt5651_probe,
2228 .suspend = rt5651_suspend,
2229 .resume = rt5651_resume,
2230 .set_bias_level = rt5651_set_bias_level,
2231 .set_jack = rt5651_set_jack,
2232 .controls = rt5651_snd_controls,
2233 .num_controls = ARRAY_SIZE(rt5651_snd_controls),
2234 .dapm_widgets = rt5651_dapm_widgets,
2235 .num_dapm_widgets = ARRAY_SIZE(rt5651_dapm_widgets),
2236 .dapm_routes = rt5651_dapm_routes,
2237 .num_dapm_routes = ARRAY_SIZE(rt5651_dapm_routes),
2238 .use_pmdown_time = 1,
2239 .endianness = 1,
2240 .non_legacy_dai_naming = 1,
2241 };
2242
2243 static const struct regmap_config rt5651_regmap = {
2244 .reg_bits = 8,
2245 .val_bits = 16,
2246
2247 .max_register = RT5651_DEVICE_ID + 1 + (ARRAY_SIZE(rt5651_ranges) *
2248 RT5651_PR_SPACING),
2249 .volatile_reg = rt5651_volatile_register,
2250 .readable_reg = rt5651_readable_register,
2251
2252 .cache_type = REGCACHE_RBTREE,
2253 .reg_defaults = rt5651_reg,
2254 .num_reg_defaults = ARRAY_SIZE(rt5651_reg),
2255 .ranges = rt5651_ranges,
2256 .num_ranges = ARRAY_SIZE(rt5651_ranges),
2257 .use_single_read = true,
2258 .use_single_write = true,
2259 };
2260
2261 #if defined(CONFIG_OF)
2262 static const struct of_device_id rt5651_of_match[] = {
2263 { .compatible = "realtek,rt5651", },
2264 {},
2265 };
2266 MODULE_DEVICE_TABLE(of, rt5651_of_match);
2267 #endif
2268
2269 #ifdef CONFIG_ACPI
2270 static const struct acpi_device_id rt5651_acpi_match[] = {
2271 { "10EC5651", 0 },
2272 { "10EC5640", 0 },
2273 { },
2274 };
2275 MODULE_DEVICE_TABLE(acpi, rt5651_acpi_match);
2276 #endif
2277
2278 static const struct i2c_device_id rt5651_i2c_id[] = {
2279 { "rt5651", 0 },
2280 { }
2281 };
2282 MODULE_DEVICE_TABLE(i2c, rt5651_i2c_id);
2283
2284 /*
2285 * Note this function MUST not look at device-properties, see the comment
2286 * above rt5651_apply_properties().
2287 */
rt5651_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)2288 static int rt5651_i2c_probe(struct i2c_client *i2c,
2289 const struct i2c_device_id *id)
2290 {
2291 struct rt5651_priv *rt5651;
2292 int ret;
2293 int err;
2294
2295 rt5651 = devm_kzalloc(&i2c->dev, sizeof(*rt5651),
2296 GFP_KERNEL);
2297 if (NULL == rt5651)
2298 return -ENOMEM;
2299
2300 i2c_set_clientdata(i2c, rt5651);
2301
2302 rt5651->regmap = devm_regmap_init_i2c(i2c, &rt5651_regmap);
2303 if (IS_ERR(rt5651->regmap)) {
2304 ret = PTR_ERR(rt5651->regmap);
2305 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2306 ret);
2307 return ret;
2308 }
2309
2310 err = regmap_read(rt5651->regmap, RT5651_DEVICE_ID, &ret);
2311 if (err)
2312 return err;
2313
2314 if (ret != RT5651_DEVICE_ID_VALUE) {
2315 dev_err(&i2c->dev,
2316 "Device with ID register %#x is not rt5651\n", ret);
2317 return -ENODEV;
2318 }
2319
2320 regmap_write(rt5651->regmap, RT5651_RESET, 0);
2321
2322 ret = regmap_register_patch(rt5651->regmap, init_list,
2323 ARRAY_SIZE(init_list));
2324 if (ret != 0)
2325 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2326
2327 rt5651->irq = i2c->irq;
2328 rt5651->hp_mute = true;
2329
2330 INIT_DELAYED_WORK(&rt5651->bp_work, rt5651_button_press_work);
2331 INIT_WORK(&rt5651->jack_detect_work, rt5651_jack_detect_work);
2332
2333 /* Make sure work is stopped on probe-error / remove */
2334 ret = devm_add_action_or_reset(&i2c->dev, rt5651_cancel_work, rt5651);
2335 if (ret)
2336 return ret;
2337
2338 ret = devm_request_irq(&i2c->dev, rt5651->irq, rt5651_irq,
2339 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2340 | IRQF_ONESHOT, "rt5651", rt5651);
2341 if (ret == 0) {
2342 /* Gets re-enabled by rt5651_set_jack() */
2343 disable_irq(rt5651->irq);
2344 } else {
2345 dev_warn(&i2c->dev, "Failed to reguest IRQ %d: %d\n",
2346 rt5651->irq, ret);
2347 rt5651->irq = -ENXIO;
2348 }
2349 rt5651->gpiod_spk_ctl = devm_gpiod_get(&i2c->dev,
2350 "spk-con",
2351 GPIOD_OUT_LOW);
2352 if (IS_ERR(rt5651->gpiod_spk_ctl)) {
2353 ret = IS_ERR(rt5651->gpiod_spk_ctl);
2354 rt5651->gpiod_spk_ctl = NULL;
2355 dev_warn(&i2c->dev, "cannot get spk-con-gpio %d\n", ret);
2356 }
2357 ret = devm_snd_soc_register_component(&i2c->dev,
2358 &soc_component_dev_rt5651,
2359 rt5651_dai, ARRAY_SIZE(rt5651_dai));
2360
2361 return ret;
2362 }
2363
2364 static struct i2c_driver rt5651_i2c_driver = {
2365 .driver = {
2366 .name = "rt5651",
2367 .acpi_match_table = ACPI_PTR(rt5651_acpi_match),
2368 .of_match_table = of_match_ptr(rt5651_of_match),
2369 },
2370 .probe = rt5651_i2c_probe,
2371 .id_table = rt5651_i2c_id,
2372 };
2373 module_i2c_driver(rt5651_i2c_driver);
2374
2375 MODULE_DESCRIPTION("ASoC RT5651 driver");
2376 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2377 MODULE_LICENSE("GPL v2");
2378