1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * include/linux/mfd/serdes/gpio.h -- GPIO for different serdes chip 4 * 5 * Copyright (c) 2023-2028 Rockchip Electronics Co. Ltd. 6 * 7 * Author: luowei <lw@rock-chips.com> 8 * 9 */ 10 11 #ifndef __MFD_SERDES_ROHM_BU18TL82_H__ 12 #define __MFD_SERDES_ROHM_BU18TL82_H__ 13 14 #define BU18TL82_REG_SWRST_INTERNAL 0x0011 15 #define BU18TL82_REG_SWRST_MIPIRX 0x0012 16 17 #define BU18TL82_REG_SWRST_INTERNAL 0x0011 18 #define BU18TL82_REG_SWRST_MIPIRX 0x0012 19 20 #define BU18TL82_BLOCK_EN_MIPIRX0 0x0013 //h [0] 1’b0 21 #define BU18TL82_BLOCK_EN_LVDSRX0 0x0013 //h [1] 1’b0 22 #define BU18TL82_BLOCK_EN_CLLTX0 0x0013 //h [3] 1’b0 23 #define BU18TL82_BLOCK_EN_VPLL0 0x0013 //h [4] 1’b0 24 #define BU18TL82_BLOCK_EN_SSCG0 0x0013 //h [5] 1’b0 25 #define BU18TL82_BLOCK_EN_MIPIRX1 0x0014 //h [0] 1’b0 26 #define BU18TL82_BLOCK_EN_LVDSRX1 0x0014 //h [1] 1’b0 27 #define BU18TL82_BLOCK_EN_CLLTX1 0x0014 //h [3] 1’b0 28 #define BU18TL82_BLOCK_EN_VPLL1 0x0014 //h [4] 1’b0 29 #define BU18TL82_BLOCK_EN_SSCG1 0x0014 //h [5] 1’b0 30 31 /*gpio register for driver/direction/pull-down*/ 32 #define BU18TL82_IO_SW_GPIO0 0x002A //h [2:1] 2’b00 33 #define BU18TL82_IO_OEN_GPIO0 0x002A //h [3] 1’b1 34 #define BU18TL82_IO_PDEN_GPIO0 0x002A //h [4] 1’b1 35 #define BU18TL82_IO_SW_GPIO1 0x002D //h [2:1] 2’b00 36 #define BU18TL82_IO_OEN_GPIO1 0x002D //h [3] 1’b1 37 #define BU18TL82_IO_PDEN_GPIO1 0x002D //h [4] 1’b1 38 #define BU18TL82_IO_SW_GPIO2 0x0030 //h [2:1] 2’b00 39 #define BU18TL82_IO_OEN_GPIO2 0x0030 //h [3] 1’b1 40 #define BU18TL82_IO_PDEN_GPIO2 0x0030 //h [4] 1’b1 41 #define BU18TL82_IO_SW_GPIO3 0x0033 //h [2:1] 2’b00 42 #define BU18TL82_IO_OEN_GPIO3 0x0033 //h [3] 1’b1 43 #define BU18TL82_IO_PDEN_GPIO3 0x0033 //h [4] 1’b1 44 #define BU18TL82_IO_SW_GPIO4 0x0036 //h [2:1] 2’b00 45 #define BU18TL82_IO_OEN_GPIO4 0x0036 //h [3] 1’b1 46 #define BU18TL82_IO_PDEN_GPIO4 0x0036 //h [4] 1’b1 47 #define BU18TL82_IO_SW_GPIO5 0x0039 //h [2:1] 2’b00 48 #define BU18TL82_IO_OEN_GPIO5 0x0039 //h [3] 1’b1 49 #define BU18TL82_IO_PDEN_GPIO5 0x0039 //h [4] 1’b1 50 #define BU18TL82_IO_SW_GPIO6 0x003C //h [2:1] 2’b00 51 #define BU18TL82_IO_OEN_GPIO6 0x003C //h [3] 1’b1 52 #define BU18TL82_IO_PDEN_GPIO6 0x003C //h [4] 1’b1 53 #define BU18TL82_IO_SW_GPIO7 0x003F //h [2:1] 2’b00 54 #define BU18TL82_IO_OEN_GPIO7 0x003F //h [3] 1’b1 55 #define BU18TL82_IO_PDEN_GPIO7 0x003F //h [4] 1’b1 56 57 /* 58 * gpio register for define connection with des gpiox, 59 * 11bits such as 0x002c:002b=[b2..b0 b7...b0] 60 * default value: 61 * ser gpio0-->des gpio0 62 * ser gpio1-->des gpio1 63 * ser gpio2-->des gpio2 64 * ser gpio3-->des gpio3 65 */ 66 #define BU18TL82_GPIO_SEL0_HIGH 0x002C //h [2:0], 67 #define BU18TL82_GPIO_SEL0_LOW 0x002B //h [7:0] 11’h002 68 #define BU18TL82_GPIO_SEL1_HIGH 0x002F //h [2:0], 69 #define BU18TL82_GPIO_SEL1_LOW 0x002E //h [7:0] 11’h003 70 #define BU18TL82_GPIO_SEL2_HIGH 0x0032 //h [2:0], 71 #define BU18TL82_GPIO_SEL2_LOW 0x0031 //h [7:0] 11’h004 72 #define BU18TL82_GPIO_SEL3_HIGH 0x0035 //h [2:0], 73 #define BU18TL82_GPIO_SEL3_LOW 0x0034 //h [7:0] 11’h005 74 #define BU18TL82_GPIO_SEL4_HIGH 0x0038 //h [2:0], 75 #define BU18TL82_GPIO_SEL4_LOW 0x0037 //h [7:0] 11’h006 76 #define BU18TL82_GPIO_SEL5_HIGH 0x003B //h [2:0], 77 #define BU18TL82_GPIO_SEL5_LOW 0x003A //h [7:0] 11’h007 78 /*datasheet about gpio6/7 need modify*/ 79 #define BU18TL82_GPIO_SEL6_LOW 0x003E //h [2:0], 80 #define BU18TL82_GPIO_SEL6_HIGH 0x003D //h [7:0] 11’h008 81 #define BU18TL82_GPIO_SEL7_LOW 0x0041 //h [2:0], 82 #define BU18TL82_GPIO_SEL7_HIGH 0x0040 //h [7:0] 11’h009 83 84 /*gpio register for define bu18tl82 gpio pin, and gpio0 to gpio0 default*/ 85 #define BU18TL82_FCCTX0_SEL_GPI0 0x02A7 //h [4:0] 5’h02 86 #define BU18TL82_FCCTX0_SEL_GPI1 0x02A8 //h [4:0] 5’h03 87 #define BU18TL82_FCCTX0_SEL_GPI2 0x02A9 //h [4:0] 5’h04 88 #define BU18TL82_FCCTX0_SEL_GPI3 0x02AA //h [4:0] 5’h05 89 #define BU18TL82_FCCTX0_SEL_GPI4 0x02AB //h [4:0] 5’h06 90 #define BU18TL82_FCCTX0_SEL_GPI5 0x02AC //h [4:0] 5’h07 91 #define BU18TL82_FCCTX0_SEL_GPI6 0x02AD //h [4:0] 5’h08 92 #define BU18TL82_FCCTX0_SEL_GPI7 0x02AE //h [4:0] 5’h09 93 #define BU18TL82_CLLTX0_SEL_GPI0 0x02AF //h [4:0] 5’h04 94 #define BU18TL82_CLLTX0_SEL_GPI1 0x02B0 //h [4:0] 5’h05 95 96 #define BU18TL82_FCCTX1_SEL_GPI0 0x03A7 //h [4:0] 5’h02 97 #define BU18TL82_FCCTX1_SEL_GPI1 0x03A8 //h [4:0] 5’h03 98 #define BU18TL82_FCCTX1_SEL_GPI2 0x03A9 //h [4:0] 5’h04 99 #define BU18TL82_FCCTX1_SEL_GPI3 0x03AA //h [4:0] 5’h05 100 #define BU18TL82_FCCTX1_SEL_GPI4 0x03AB //h [4:0] 5’h06 101 #define BU18TL82_FCCTX1_SEL_GPI5 0x03AC //h [4:0] 5’h07 102 #define BU18TL82_FCCTX1_SEL_GPI6 0x03AD //h [4:0] 5’h08 103 #define BU18TL82_FCCTX1_SEL_GPI7 0x03AE //h [4:0] 5’h09 104 #define BU18TL82_CLLTX1_SEL_GPI0 0x03AF //h [4:0] 5’h04 105 #define BU18TL82_CLLTX1_SEL_GPI1 0x03B0 //h [4:0] 5’h05 106 107 /*write 1'b0 to this register to clear all isr register value8*/ 108 #define BU18TL82_ISR_CLEAR_ALL 0x0105 //h[0] 109 110 #define BU18TL82_ISR_BCCDES0_ERR_CRC 0x0131 //h [3] 1’b0 111 #define BU18TL82_ISR_BCCRX0_STATUS_NEAR_LOST 0x0131 //h[7] 112 #define BU18TL82_ISR_BCCDES1_ERR_CRC 0x0132 //h [3] 1’b0 113 #define BU18TL82_ISR_BCCRX1_STATUS_NEAR_LOST 0x0132 //h[7] 114 #define BU18TL82_ISR_MIPIRX0_SOT_ERR 0x0133 //h[0] 115 #define BU18TL82_ISR_MIPIRX0_SOT_SYNC_ERR 0x0133 //h[1] 116 #define BU18TL82_ISR_MIPIRX0_EOT_SYNC_ERR 0x0133 //h[2] 117 #define BU18TL82_ISR_MIPIRX0_ECC1BIT_ERR 0x0134 //h[0] 118 #define BU18TL82_ISR_MIPIRX0_ECCMULT_ERR 0x0134 //h[1] 119 #define BU18TL82_ISR_MIPIRX0_CRC_ERR 0x0134 //h[2] 120 #define BU18TL82_ISR_MIPIRX1_SOT_ERR 0x0135 //h[0] 121 #define BU18TL82_ISR_MIPIRX1_SOT_SYNC_ERR 0x0135 //h[1] 122 #define BU18TL82_ISR_MIPIRX1_EOT_SYNC_ERR 0x0135 //h[2] 123 #define BU18TL82_ISR_MIPIRX1_ECC1BIT_ERR 0x0136 //h[0] 124 #define BU18TL82_ISR_MIPIRX1_ECCMULT_ERR 0x0136 //h[1] 125 #define BU18TL82_ISR_MIPIRX1_CRC_ERR 0x0136 //h[2] 126 #define BU18TL82_ISR_LVDSRX0_V_TOTAL_MAX_ERR 0x0137 //h[0] 127 #define BU18TL82_ISR_LVDSRX0_V_TOTAL_MIN_ERR 0x0137 //h[1] 128 #define BU18TL82_ISR_LVDSRX0_V_ACTIVE_MAX_ERR 0x0137 //h[2] 129 #define BU18TL82_ISR_LVDSRX0_V_ACTIVE_MIN_ERR 0x0137 //h[3] 130 #define BU18TL82_ISR_LVDSRX0_H_TOTAL_MAX_ERR 0x0137 //h[4] 131 #define BU18TL82_ISR_LVDSRX0_H_TOTAL_MIN_ERR 0x0137 //h[5] 132 #define BU18TL82_ISR_LVDSRX0_H_ACTIVE_MAX_ERR 0x0137 //h[6] 133 #define BU18TL82_ISR_LVDSRX0_H_ACTIVE_MIN_ERR 0x0137 //h[7] 134 #define BU18TL82_ISR_LVDSRX1_V_TOTAL_MAX_ERR 0x0138 //h[0] 135 #define BU18TL82_ISR_LVDSRX1_V_TOTAL_MIN_ERR 0x0138 //h[1] 136 #define BU18TL82_ISR_LVDSRX1_V_ACTIVE_MAX_ERR 0x0138 //h[2] 137 #define BU18TL82_ISR_LVDSRX1_V_ACTIVE_MIN_ERR 0x0138 //h[3] 138 #define BU18TL82_ISR_LVDSRX1_H_TOTAL_MAX_ERR 0x0138 //h[4] 139 #define BU18TL82_ISR_LVDSRX1_H_TOTAL_MIN_ERR 0x0138 //h[5] 140 #define BU18TL82_ISR_LVDSRX1_H_ACTIVE_MAX_ERR 0x0138 //h[6] 141 #define BU18TL82_ISR_LVDSRX1_H_ACTIVE_MIN_ERR 0x0138 //h[7] 142 #define BU18TL82_ISR_IO_STUCK_GPIO0 0x0139 //h[0] 143 #define BU18TL82_ISR_IO_STUCK_GPIO1 0x0139 //h[1] 144 #define BU18TL82_ISR_IO_STUCK_GPIO2 0x0139 //h[2] 145 #define BU18TL82_ISR_IO_STUCK_GPIO3 0x0139 //h[3] 146 #define BU18TL82_ISR_IO_STUCK_GPIO4 0x0139 //h[4] 147 #define BU18TL82_ISR_IO_STUCK_GPIO5 0x0139 //h[5] 148 #define BU18TL82_ISR_IO_STUCK_GPIO6 0x0139 //h[6] 149 #define BU18TL82_ISR_IO_STUCK_GPIO7 0x0139 //h[7] 150 #define BU18TL82_ISR_IO_STUCK_IRQ 0x013a //h[1] 151 #define BU18TL82_ISR_IDS_UNSTABLE 0x013a //h [7] 1’b0 152 #define BU18TL82_ISR_I2C_A_TIMEOUT 0x013b //h [0] 1’b0 153 #define BU18TL82_ISR_I2C_A_XMIT_ERR 0x013b //h [1] 1’b0 154 #define BU18TL82_ISR_I2C_B_TIMEOUT 0x013c //h [0] 1’b0 155 #define BU18TL82_ISR_I2C_B_XMIT_ERR 0x013c //h [1] 1’b0 156 #define BU18TL82_ISR_REGCRC_ERR_PAGE0 0x013d //h[0] 157 #define BU18TL82_ISR_REGCRC_ERR_PAGE1 0x013d //h[1] 158 #define BU18TL82_ISR_REGCRC_ERR_PAGE2 0x013d //h[2] 159 #define BU18TL82_ISR_REGCRC_ERR_PAGE3 0x013d //h[3] 160 #define BU18TL82_ISR_REGCRC_ERR_PAGE4 0x013d //h[4] 161 #define BU18TL82_ISR_REGCRC_ERR_PAGE5 0x013d //h[5] 162 #define BU18TL82_ISR_CLKDETECT_CLKIN0_STOP 0x013e //h [0] 1’b0 163 #define BU18TL82_ISR_CLKDETECT_CLKIN0_UNLOCK 0x013e //h [1] 1’b0 164 #define BU18TL82_ISR_CLKDETECT_OSC_STOP 0x013e //h [4] 1’b0 165 #define BU18TL82_ISR_CLKDETECT_OSC_UNLOCK 0x013e //h [5] 1’b0 166 #define BU18TL82_ISR_CLKDETECT_CLKIN1_STOP 0x013f //h [0] 1’b0 167 #define BU18TL82_ISR_CLKDETECT_CLKIN1_UNLOCK 0x013f //h [1] 1’b0 168 #define BU18TL82_ISR_CLKDETECT_LVDSRX0_STOP 0x0140 //h [0] 1’b0 169 #define BU18TL82_ISR_CLKDETECT_LVDSRX0_UNLOCK 0x0140 //h [1] 1’b0 170 #define BU18TL82_ISR_CLKDETECT_MIPIRX0_STOP 0x0140 //h [4] 1’b0 171 #define BU18TL82_ISR_CLKDETECT_MIPIRX0_UNLOCK 0x0140 //h [5] 1’b0 172 #define BU18TL82_ISR_CLKDETECT_LVDSRX1_STOP 0x0141 //h [0] 1’b0 173 #define BU18TL82_ISR_CLKDETECT_LVDSRX1_UNLOCK 0x0141 //h [1] 1’b0 174 #define BU18TL82_ISR_CLKDETECT_MIPIRX1_STOP 0x0141 //h [4] 1’b0 175 #define BU18TL82_ISR_CLKDETECT_MIPIRX1_UNLOCK 0x0141 //h [5] 1’b0 176 #define BU18TL82_ISR_CLKDETECT_CLLTX0_SCLK_STOP 0x0142 //h [0] 1’b0 177 #define BU18TL82_ISR_CLKDETECT_CLLTX0_SCLK_UNLOCK 0x0142 //h [1] 1’b0 178 #define BU18TL82_ISR_CLKDETECT_CLLTX0_PLLREF_STOP 0x0142 //h [4] 1’b0 179 #define BU18TL82_ISR_CLKDETECT_CLLTX0_PLLREF_UNLOCK 0x0142 //h [5] 1’b0 180 #define BU18TL82_ISR_CLKDETECT_CLLTX1_SCLK_STOP 0x0143 //h [0] 1’b0 181 #define BU18TL82_ISR_CLKDETECT_CLLTX1_SCLK_UNLOCK 0x0143 //h [1] 1’b0 182 #define BU18TL82_ISR_CLKDETECT_CLLTX1_PLLREF_STOP 0x0143 //h [4] 1’b0 183 #define BU18TL82_ISR_CLKDETECT_CLLTX1_PLLREF_UNLOCK 0x0143 //h [5] 1’b0 184 #define BU18TL82_ISR_STATUS_RX0_ISR00 0x0149 //h [0] 1’b0 185 #define BU18TL82_ISR_STATUS_RX0_ISR01 0x0149 //h [1] 1’b0 186 #define BU18TL82_ISR_STATUS_RX0_ISR02 0x0149 //h [2] 1’b0 187 #define BU18TL82_ISR_STATUS_RX0_ISR03 0x0149 //h [3] 1’b0 188 #define BU18TL82_ISR_STATUS_RX0_ISR04 0x0149 //h [4] 1’b0 189 #define BU18TL82_ISR_STATUS_RX0_ISR05 0x0149 //h [5] 1’b0 190 #define BU18TL82_ISR_STATUS_RX0_ISR06 0x0149 //h [6] 1’b0 191 #define BU18TL82_ISR_STATUS_RX0_ISR07 0x0149 //h [7] 1’b0 192 #define BU18TL82_ISR_STATUS_RX0_ISR08 0x014a //h [0] 1’b0 193 #define BU18TL82_ISR_STATUS_RX0_ISR09 0x014a //h [1] 1’b0 194 #define BU18TL82_ISR_STATUS_RX0_ISR10 0x014a //h [2] 1’b0 195 196 #define BU18TL82_IEN_BCCDES0_ERR_CRC 0x0109 //h [3] 1’b0 197 #define BU18TL82_IEN_BCCRX0_STATUS_NEAR_LOST 0x0109 //h[7] 198 #define BU18TL82_IEN_BCCDES1_ERR_CRC 0x010A //h [3] 1’b0 199 #define BU18TL82_IEN_BCCRX1_STATUS_NEAR_LOST 0x010A //h[7] 200 #define BU18TL82_IEN_MIPIRX0_SOT_ERR 0x010B //h[0] 201 #define BU18TL82_IEN_MIPIRX0_SOT_SYNC_ERR 0x010B //h[1] 202 #define BU18TL82_IEN_MIPIRX0_EOT_SYNC_ERR 0x010B //h[2] 203 #define BU18TL82_IEN_MIPIRX0_ECC1BIT_ERR 0x010C //h[0] 204 #define BU18TL82_IEN_MIPIRX0_ECCMULT_ERR 0x010C //h[1] 205 #define BU18TL82_IEN_MIPIRX0_CRC_ERR 0x010C //h[2] 206 #define BU18TL82_IEN_MIPIRX1_SOT_ERR 0x010D //h[0] 207 #define BU18TL82_IEN_MIPIRX1_SOT_SYNC_ERR 0x010D //h[1] 208 #define BU18TL82_IEN_MIPIRX1_EOT_SYNC_ERR 0x010D //h[2] 209 #define BU18TL82_IEN_MIPIRX1_ECC1BIT_ERR 0x010E //h[0] 210 #define BU18TL82_IEN_MIPIRX1_ECCMULT_ERR 0x010E //h[1] 211 #define BU18TL82_IEN_MIPIRX1_CRC_ERR 0x010E //h[2] 212 #define BU18TL82_IEN_LVDSRX0_V_TOTAL_MAX_ERR 0x010F //h[0] 213 #define BU18TL82_IEN_LVDSRX0_V_TOTAL_MIN_ERR 0x010F //h[1] 214 #define BU18TL82_IEN_LVDSRX0_V_ACTIVE_MAX_ERR 0x010F //h[2] 215 #define BU18TL82_IEN_LVDSRX0_V_ACTIVE_MIN_ERR 0x010F //h[3] 216 #define BU18TL82_IEN_LVDSRX0_H_TOTAL_MAX_ERR 0x010F //h[4] 217 #define BU18TL82_IEN_LVDSRX0_H_TOTAL_MIN_ERR 0x010F //h[5] 218 #define BU18TL82_IEN_LVDSRX0_H_ACTIVE_MAX_ERR 0x010F //h[6] 219 #define BU18TL82_IEN_LVDSRX0_H_ACTIVE_MIN_ERR 0x010F //h[7] 220 #define BU18TL82_IEN_LVDSRX1_V_TOTAL_MAX_ERR 0x0110 //h[0] 221 #define BU18TL82_IEN_LVDSRX1_V_TOTAL_MIN_ERR 0x0110 //h[1] 222 #define BU18TL82_IEN_LVDSRX1_V_ACTIVE_MAX_ERR 0x0110 //h[2] 223 #define BU18TL82_IEN_LVDSRX1_V_ACTIVE_MIN_ERR 0x0110 //h[3] 224 #define BU18TL82_IEN_LVDSRX1_H_TOTAL_MAX_ERR 0x0110 //h[4] 225 #define BU18TL82_IEN_LVDSRX1_H_TOTAL_MIN_ERR 0x0110 //h[5] 226 #define BU18TL82_IEN_LVDSRX1_H_ACTIVE_MAX_ERR 0x0110 //h[6] 227 #define BU18TL82_IEN_LVDSRX1_H_ACTIVE_MIN_ERR 0x0110 //h[7] 228 #define BU18TL82_IEN_IO_STUCK_GPIO0 0x0111 //h[0] 229 #define BU18TL82_IEN_IO_STUCK_GPIO1 0x0111 //h[1] 230 #define BU18TL82_IEN_IO_STUCK_GPIO2 0x0111 //h[2] 231 #define BU18TL82_IEN_IO_STUCK_GPIO3 0x0111 //h[3] 232 #define BU18TL82_IEN_IO_STUCK_GPIO4 0x0111 //h[4] 233 #define BU18TL82_IEN_IO_STUCK_GPIO5 0x0111 //h[5] 234 #define BU18TL82_IEN_IO_STUCK_GPIO6 0x0111 //h[6] 235 #define BU18TL82_IEN_IO_STUCK_GPIO7 0x0111 //h[7] 236 #define BU18TL82_IEN_IO_STUCK_IRQ 0x0112 //h[1] 237 #define BU18TL82_IEN_IDS_UNSTABLE 0x0112 //h [7] 1’b0 238 #define BU18TL82_IEN_I2C_A_TIMEOUT 0x0113 //h [0] 1’b0 239 #define BU18TL82_IEN_I2C_A_XMIT_ERR 0x0113 //h [1] 1’b0 240 #define BU18TL82_IEN_I2C_B_TIMEOUT 0x0114 //h [0] 1’b0 241 #define BU18TL82_IEN_I2C_B_XMIT_ERR 0x0114 //h [1] 1’b0 242 #define BU18TL82_IEN_REGCRC_ERR_PAGE0 0x0115 //h[0] 243 #define BU18TL82_IEN_REGCRC_ERR_PAGE1 0x0115 //h[1] 244 #define BU18TL82_IEN_REGCRC_ERR_PAGE2 0x0115 //h[2] 245 #define BU18TL82_IEN_REGCRC_ERR_PAGE3 0x0115 //h[3] 246 #define BU18TL82_IEN_REGCRC_ERR_PAGE4 0x0115 //h[4] 247 #define BU18TL82_IEN_REGCRC_ERR_PAGE5 0x0115 //h[5] 248 #define BU18TL82_IEN_CLKDETECT_CLKIN0_STOP 0x0116 //h [0] 1’b0 249 #define BU18TL82_IEN_CLKDETECT_CLKIN0_UNLOCK 0x0116 //h [1] 1’b0 250 #define BU18TL82_IEN_CLKDETECT_OSC_STOP 0x0116 //h [4] 1’b0 251 #define BU18TL82_IEN_CLKDETECT_OSC_UNLOCK 0x0116 //h [5] 1’b0 252 #define BU18TL82_IEN_CLKDETECT_CLKIN1_STOP 0x0117 //h [0] 1’b0 253 #define BU18TL82_IEN_CLKDETECT_CLKIN1_UNLOCK 0x0117 //h [1] 1’b0 254 #define BU18TL82_IEN_CLKDETECT_LVDSRX0_STOP 0x0118 //h [0] 1’b0 255 #define BU18TL82_IEN_CLKDETECT_LVDSRX0_UNLOCK 0x0118 //h [1] 1’b0 256 #define BU18TL82_IEN_CLKDETECT_MIPIRX0_STOP 0x0118 //h [4] 1’b0 257 #define BU18TL82_IEN_CLKDETECT_MIPIRX0_UNLOCK 0x0118 //h [5] 1’b0 258 #define BU18TL82_IEN_CLKDETECT_LVDSRX1_STOP 0x0119 //h [0] 1’b0 259 #define BU18TL82_IEN_CLKDETECT_LVDSRX1_UNLOCK 0x0119 //h [1] 1’b0 260 #define BU18TL82_IEN_CLKDETECT_MIPIRX1_STOP 0x0119 //h [4] 1’b0 261 #define BU18TL82_IEN_CLKDETECT_MIPIRX1_UNLOCK 0x0119 //h [5] 1’b0 262 #define BU18TL82_IEN_CLKDETECT_CLLTX0_SCLK_STOP 0x011A //h [0] 1’b0 263 #define BU18TL82_IEN_CLKDETECT_CLLTX0_SCLK_UNLOCK 0x011A //h [1] 1’b0 264 #define BU18TL82_IEN_CLKDETECT_CLLTX0_PLLREF_STOP 0x011A //h [4] 1’b0 265 #define BU18TL82_IEN_CLKDETECT_CLLTX0_PLLREF_UNLOCK 0x011A //h [5] 1’b0 266 #define BU18TL82_IEN_CLKDETECT_CLLTX1_SCLK_STOP 0x011B //h [0] 1’b0 267 #define BU18TL82_IEN_CLKDETECT_CLLTX1_SCLK_UNLOCK 0x011B //h [1] 1’b0 268 #define BU18TL82_IEN_CLKDETECT_CLLTX1_PLLREF_STOP 0x011B //h [4] 1’b0 269 #define BU18TL82_IEN_CLKDETECT_CLLTX1_PLLREF_UNLOCK 0x011B //h [5] 1’b0 270 #define BU18TL82_IEN_STATUS_RX0_ISR00 0x0121 //h [0] 1’b0 271 #define BU18TL82_IEN_STATUS_RX0_ISR01 0x0121 //h [1] 1’b0 272 #define BU18TL82_IEN_STATUS_RX0_ISR02 0x0121 //h [2] 1’b0 273 #define BU18TL82_IEN_STATUS_RX0_ISR03 0x0121 //h [3] 1’b0 274 #define BU18TL82_IEN_STATUS_RX0_ISR04 0x0121 //h [4] 1’b0 275 #define BU18TL82_IEN_STATUS_RX0_ISR05 0x0121 //h [5] 1’b0 276 #define BU18TL82_IEN_STATUS_RX0_ISR06 0x0121 //h [6] 1’b0 277 #define BU18TL82_IEN_STATUS_RX0_ISR07 0x0121 //h [7] 1’b0 278 #define BU18TL82_IEN_STATUS_RX0_ISR08 0x0122 //h [0] 1’b0 279 #define BU18TL82_IEN_STATUS_RX0_ISR09 0x0122 //h [1] 1’b0 280 #define BU18TL82_IEN_STATUS_RX0_ISR10 0x0122 //h [2] 1’b0 281 282 struct bu18tl82_gpio_sw_reg { 283 unsigned int reg; 284 unsigned int mask; //2/4/6/8ma 285 }; 286 287 struct bu18tl82_gpio_oen_reg { 288 unsigned int reg; 289 unsigned int mask; //0:output 1:input 290 }; 291 292 struct bu18tl82_gpio_pden_reg { 293 unsigned int reg; 294 unsigned int mask; //0:no pulldown 1:connect pulldown 295 }; 296 297 struct bu18tl82_gpio_id_low_reg { 298 unsigned int reg; 299 unsigned int mask; //b2b1b0 300 }; 301 302 struct bu18tl82_gpio_id_high_reg { 303 unsigned int reg; 304 unsigned int mask; //b11b10b9b8b7b6b5b4b3 305 }; 306 307 static const struct bu18tl82_gpio_sw_reg bu18tl82_gpio_sw[8] = { 308 {BU18TL82_IO_SW_GPIO0, BIT(2) | BIT(1)}, 309 {BU18TL82_IO_SW_GPIO1, BIT(2) | BIT(1)}, 310 {BU18TL82_IO_SW_GPIO2, BIT(2) | BIT(1)}, 311 {BU18TL82_IO_SW_GPIO3, BIT(2) | BIT(1)}, 312 {BU18TL82_IO_SW_GPIO4, BIT(2) | BIT(1)}, 313 {BU18TL82_IO_SW_GPIO5, BIT(2) | BIT(1)}, 314 {BU18TL82_IO_SW_GPIO6, BIT(2) | BIT(1)}, 315 {BU18TL82_IO_SW_GPIO7, BIT(2) | BIT(1)}, 316 }; 317 318 static const struct bu18tl82_gpio_oen_reg bu18tl82_gpio_oen[8] = { 319 {BU18TL82_IO_OEN_GPIO0, BIT(3)}, 320 {BU18TL82_IO_OEN_GPIO1, BIT(3)}, 321 {BU18TL82_IO_OEN_GPIO2, BIT(3)}, 322 {BU18TL82_IO_OEN_GPIO3, BIT(3)}, 323 {BU18TL82_IO_OEN_GPIO4, BIT(3)}, 324 {BU18TL82_IO_OEN_GPIO5, BIT(3)}, 325 {BU18TL82_IO_OEN_GPIO6, BIT(3)}, 326 {BU18TL82_IO_OEN_GPIO7, BIT(3)}, 327 }; 328 329 static const struct bu18tl82_gpio_pden_reg bu18tl82_gpio_pden[8] = { 330 {BU18TL82_IO_PDEN_GPIO0, BIT(4)}, 331 {BU18TL82_IO_PDEN_GPIO1, BIT(4)}, 332 {BU18TL82_IO_PDEN_GPIO2, BIT(4)}, 333 {BU18TL82_IO_PDEN_GPIO3, BIT(4)}, 334 {BU18TL82_IO_PDEN_GPIO4, BIT(4)}, 335 {BU18TL82_IO_PDEN_GPIO5, BIT(4)}, 336 {BU18TL82_IO_PDEN_GPIO6, BIT(4)}, 337 {BU18TL82_IO_PDEN_GPIO7, BIT(4)}, 338 }; 339 340 static const struct bu18tl82_gpio_id_low_reg bu18tl82_gpio_id_low[8] = { 341 {BU18TL82_GPIO_SEL0_LOW, GENMASK(7, 0)}, 342 {BU18TL82_GPIO_SEL1_LOW, GENMASK(7, 0)}, 343 {BU18TL82_GPIO_SEL2_LOW, GENMASK(7, 0)}, 344 {BU18TL82_GPIO_SEL3_LOW, GENMASK(7, 0)}, 345 {BU18TL82_GPIO_SEL4_LOW, GENMASK(7, 0)}, 346 {BU18TL82_GPIO_SEL5_LOW, GENMASK(7, 0)}, 347 {BU18TL82_GPIO_SEL6_LOW, GENMASK(7, 0)}, 348 {BU18TL82_GPIO_SEL7_LOW, GENMASK(7, 0)}, 349 }; 350 351 static const struct bu18tl82_gpio_id_high_reg bu18tl82_gpio_id_high[8] = { 352 {BU18TL82_GPIO_SEL0_HIGH, GENMASK(2, 0)}, 353 {BU18TL82_GPIO_SEL1_HIGH, GENMASK(2, 0)}, 354 {BU18TL82_GPIO_SEL2_HIGH, GENMASK(2, 0)}, 355 {BU18TL82_GPIO_SEL3_HIGH, GENMASK(2, 0)}, 356 {BU18TL82_GPIO_SEL4_HIGH, GENMASK(2, 0)}, 357 {BU18TL82_GPIO_SEL5_HIGH, GENMASK(2, 0)}, 358 {BU18TL82_GPIO_SEL6_HIGH, GENMASK(2, 0)}, 359 {BU18TL82_GPIO_SEL7_HIGH, GENMASK(2, 0)}, 360 }; 361 362 struct bu18tl82_ien_reg { 363 unsigned int reg; 364 unsigned int ien; 365 }; 366 367 struct bu18tl82_isr_reg { 368 unsigned int reg; 369 unsigned int isr; 370 }; 371 372 static const struct bu18tl82_ien_reg bu18tl82_reg_ien[21] = { 373 {BU18TL82_IEN_BCCRX0_STATUS_NEAR_LOST, BIT(3) | BIT(7)}, 374 {BU18TL82_IEN_BCCRX1_STATUS_NEAR_LOST, BIT(3) | BIT(7)}, 375 376 {BU18TL82_IEN_MIPIRX0_SOT_ERR, 377 BIT(0) | BIT(0) | BIT(2)}, 378 {BU18TL82_IEN_MIPIRX0_ECC1BIT_ERR, 379 BIT(0) | BIT(0) | BIT(2)}, 380 381 {BU18TL82_IEN_MIPIRX1_SOT_ERR, 382 BIT(0) | BIT(0) | BIT(2)}, 383 {BU18TL82_IEN_MIPIRX1_ECC1BIT_ERR, 384 BIT(0) | BIT(0) | BIT(2)}, 385 386 {BU18TL82_IEN_LVDSRX0_V_TOTAL_MAX_ERR, 0XFF}, 387 {BU18TL82_IEN_LVDSRX1_V_TOTAL_MAX_ERR, 0XFF}, 388 389 {BU18TL82_IEN_IO_STUCK_GPIO0, 0XFF}, 390 {BU18TL82_IEN_IO_STUCK_IRQ, BIT(1) | BIT(7)}, 391 {BU18TL82_IEN_I2C_A_TIMEOUT, BIT(0) | BIT(1)}, 392 {BU18TL82_IEN_I2C_B_TIMEOUT, BIT(0) | BIT(1)}, 393 394 {BU18TL82_IEN_REGCRC_ERR_PAGE0, 0x3F}, 395 396 {BU18TL82_IEN_CLKDETECT_CLKIN0_STOP, 397 BIT(0) | BIT(1) | BIT(4) | BIT(5)}, 398 {BU18TL82_IEN_CLKDETECT_CLKIN1_STOP, 399 BIT(0) | BIT(1)}, 400 401 {BU18TL82_IEN_CLKDETECT_LVDSRX0_STOP, 402 BIT(0) | BIT(1) | BIT(4) | BIT(5)}, 403 {BU18TL82_IEN_CLKDETECT_LVDSRX1_STOP, 404 BIT(0) | BIT(1) | BIT(4) | BIT(5)}, 405 {BU18TL82_IEN_CLKDETECT_CLLTX0_SCLK_STOP, 406 BIT(0) | BIT(1) | BIT(4) | BIT(5)}, 407 {BU18TL82_IEN_CLKDETECT_CLLTX1_SCLK_STOP, 408 BIT(0) | BIT(1) | BIT(4) | BIT(5)}, 409 410 {BU18TL82_IEN_STATUS_RX0_ISR00, 0xff}, 411 {BU18TL82_IEN_STATUS_RX0_ISR08, BIT(0) | BIT(1) | BIT(2)}, 412 }; 413 414 static const struct bu18tl82_isr_reg bu18tl82_reg_isr[21] = { 415 {BU18TL82_ISR_BCCRX0_STATUS_NEAR_LOST, BIT(3) | BIT(7)}, 416 {BU18TL82_ISR_BCCRX1_STATUS_NEAR_LOST, BIT(3) | BIT(7)}, 417 418 {BU18TL82_ISR_MIPIRX0_SOT_ERR, BIT(0) | BIT(0) | BIT(2)}, 419 {BU18TL82_ISR_MIPIRX0_ECC1BIT_ERR, BIT(0) | BIT(0) | BIT(2)}, 420 421 {BU18TL82_ISR_MIPIRX1_SOT_ERR, BIT(0) | BIT(0) | BIT(2)}, 422 {BU18TL82_ISR_MIPIRX1_ECC1BIT_ERR, BIT(0) | BIT(0) | BIT(2)}, 423 424 {BU18TL82_ISR_LVDSRX0_V_TOTAL_MAX_ERR, 0XFF}, 425 {BU18TL82_ISR_LVDSRX1_V_TOTAL_MAX_ERR, 0XFF}, 426 427 {BU18TL82_ISR_IO_STUCK_GPIO0, 0XFF}, 428 {BU18TL82_ISR_IO_STUCK_IRQ, BIT(1) | BIT(7)}, 429 {BU18TL82_ISR_I2C_A_TIMEOUT, BIT(0) | BIT(1)}, 430 {BU18TL82_ISR_I2C_B_TIMEOUT, BIT(0) | BIT(1)}, 431 432 {BU18TL82_ISR_REGCRC_ERR_PAGE0, 0x3F}, 433 434 {BU18TL82_ISR_CLKDETECT_CLKIN0_STOP, 435 BIT(0) | BIT(1) | BIT(4) | BIT(5)}, 436 {BU18TL82_ISR_CLKDETECT_CLKIN1_STOP, 437 BIT(0) | BIT(1)}, 438 439 {BU18TL82_ISR_CLKDETECT_LVDSRX0_STOP, 440 BIT(0) | BIT(1) | BIT(4) | BIT(5)}, 441 {BU18TL82_ISR_CLKDETECT_LVDSRX1_STOP, 442 BIT(0) | BIT(1) | BIT(4) | BIT(5)}, 443 {BU18TL82_ISR_CLKDETECT_CLLTX0_SCLK_STOP, 444 BIT(0) | BIT(1) | BIT(4) | BIT(5)}, 445 {BU18TL82_ISR_CLKDETECT_CLLTX1_SCLK_STOP, 446 BIT(0) | BIT(1) | BIT(4) | BIT(5)}, 447 448 {BU18TL82_ISR_STATUS_RX0_ISR00, 0xff}, 449 {BU18TL82_ISR_STATUS_RX0_ISR08, BIT(0) | BIT(1) | BIT(2)}, 450 }; 451 452 #endif 453