1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Rockchip VAD driver 4 * 5 * Copyright (C) 2018 Fuzhou Rockchip Electronics Co., Ltd 6 * 7 */ 8 9 #ifndef _ROCKCHIP_VAD_H 10 #define _ROCKCHIP_VAD_H 11 12 #define VAD_CTRL 0x00 13 #define VAD_DET_CHNL_SHIFT 29 14 #define VAD_DET_CHNL_MASK GENMASK(31, 29) 15 #define VAD_DET_CHNL(x) ((x) << VAD_DET_CHNL_SHIFT) 16 #define AUDIO_24BIT_SAT_SHIFT 28 17 #define AUDIO_24BIT_SAT_MASK BIT(28) 18 #define AUDIO_H16B 0 19 #define AUDIO_SAT_24TO16 BIT(28) 20 #define AUDIO_24BIT_ALIGN_MODE_SHIFT 27 21 #define AUDIO_24BIT_ALIGN_MODE_MASK BIT(27) 22 #define AUDIO_24BIT_ALIGN_8_31B 0 23 #define AUDIO_24BIT_ALIGN_0_23B BIT(27) 24 #define AUDIO_CHNL_BW_SHIFT 26 25 #define AUDIO_CHNL_BW_MASK BIT(26) 26 #define AUDIO_CHNL_16B 0 27 #define AUDIO_CHNL_24B BIT(26) 28 #define AUDIO_CHNL_NUM_SHIFT 23 29 #define AUDIO_CHNL_NUM_MASK GENMASK(25, 23) 30 #define AUDIO_CHNL_NUM(x) ((x - 1) << AUDIO_CHNL_NUM_SHIFT) 31 #define CFG_ACODE_AFTER_DET_EN_SHIFT 22 32 #define CFG_ACODE_AFTER_DET_EN_MASK BIT(22) 33 #define CFG_ACODE_AFTER_DET_EN BIT(22) 34 #define VAD_MODE_SHIFT 20 35 #define VAD_MODE_MASK GENMASK(21, 20) 36 #define STORE_DATA_VAD_DET_ONLY 0 37 #define STORE_DATA_ALL (1 << VAD_MODE_SHIFT) 38 #define NO_STORE_DATA (2 << VAD_MODE_SHIFT) 39 #define ACODE_CFG_REG_NUM_SHIFT 15 40 #define ACODE_CFG_REG_NUM_MASK GENMASK(19, 15) 41 #define ACODE_CFG_REG_NUM(x) ((x - 1) << ACODE_CFG_REG_NUM_SHIFT) 42 #define SRC_ADDR_MODE_SHIFT 14 43 #define SRC_ADDR_MODE_MASK BIT(14) 44 #define SRC_ADDR_MODE_INC 0 45 #define SRC_ADDR_MODE_FIXED BIT(14) 46 #define INCR_BURST_LEN_SHIFT 10 47 #define INCR_BURST_LEN_MASK GENMASK(13, 10) 48 #define INCR_BURST_LEN(x) ((x - 1) << INCR_BURST_LEN_SHIFT) 49 #define SRC_BURST_NUM_SHIFT 7 50 #define SRC_BURST_NUM_MASK GENMASK(9, 7) 51 #define SRC_BURST_NUM(x) ((x - 1) << SRC_BURST_NUM_SHIFT) 52 #define SRC_BURST_SHIFT 4 53 #define SRC_BURST_MASK GENMASK(6, 4) 54 #define SRC_BURST_SIGNLE 0 55 #define SRC_BURST_INCR (1 << SRC_BURST_SHIFT) 56 #define SRC_BURST_INCR4 (3 << SRC_BURST_SHIFT) 57 #define SRC_BURST_INCR8 (5 << SRC_BURST_SHIFT) 58 #define SRC_BURST_INCR16 (7 << SRC_BURST_SHIFT) 59 #define AUDIO_SRC_SEL_SHIFT 1 60 #define AUDIO_SRC_SEL_MASK GENMASK(3, 1) 61 #define AUDIO_SRC_SEL_I2S0 0 62 #define AUDIO_SRC_SEL_I2S1 (1 << AUDIO_SRC_SEL_MASK) 63 #define AUDIO_SRC_SEL_I2S2 (2 << AUDIO_SRC_SEL_MASK) 64 #define AUDIO_SRC_SEL_I2S3 (3 << AUDIO_SRC_SEL_MASK) 65 #define AUDIO_SRC_SEL_PDM (4 << AUDIO_SRC_SEL_MASK) 66 #define VAD_EN_SHIFT 0 67 #define VAD_EN_MASK BIT(0) 68 #define VAD_EN BIT(0) 69 #define VAD_DISABLE 0 70 #define VAD_IS_ADDR 4 71 #define VAD_ID_ADDR 8 72 #define VAD_OD_ADDR0 0x0c 73 #define VAD_OD_ADDR1 0x10 74 #define VAD_OD_ADDR2 0x14 75 #define VAD_OD_ADDR3 0x18 76 #define VAD_OD_ADDR4 0x1c 77 #define VAD_OD_ADDR5 0x20 78 #define VAD_OD_ADDR6 0x24 79 #define VAD_OD_ADDR7 0x28 80 #define VAD_D_DATA0 0x2c 81 #define VAD_D_DATA1 0x30 82 #define VAD_D_DATA2 0x34 83 #define VAD_D_DATA3 0x38 84 #define VAD_D_DATA4 0x3c 85 #define VAD_D_DATA5 0x40 86 #define VAD_D_DATA6 0x44 87 #define VAD_D_DATA7 0x48 88 89 #define VAD_TIMEOUT 0x4c 90 #define WORK_TIMEOUT_EN_MASK BIT(31) 91 #define WORK_TIMEOUT_EN BIT(31) 92 #define WORK_TIMEOUT_DISABLE 0 93 #define IDLE_TIMEOUT_EN_MASK BIT(30) 94 #define IDLE_TIMEOUT_EN BIT(30) 95 #define IDLE_TIMEOUT_DISABLE 0 96 #define WORK_TIMEOUT_THD_SHIFT 20 97 #define WORK_TIMEOUT_THD_MASK GENMASK(29, 20) 98 #define WORK_TIMEOUT_THD(x) ((x) << WORK_TIMEOUT_THD_SHIFT) 99 #define IDLE_TIMEOUT_THD_SHIFT 0 100 #define IDLE_TIMEOUT_THD_MASK GENMASK(19, 0) 101 #define IDLE_TIMEOUT_THD(x) ((x) << IDLE_TIMEOUT_THD_SHIFT) 102 103 #define VAD_RAM_BEGIN_ADDR 0x50 104 #define VAD_RAM_END_ADDR 0x54 105 #define VAD_RAM_CUR_ADDR 0x58 106 #define VAD_DET_CON0 0x5c 107 #define VAD_CON_THD_SHIFT 16 108 #define VAD_CON_THD_MASK GENMASK(23, 16) 109 #define VAD_CON_THD(x) ((x) << VAD_CON_THD_SHIFT) 110 #define NOISE_LEVEL_SHIFT 12 111 #define NOISE_LEVEL_MASK GENMASK(14, 12) 112 #define NOISE_LEVEL(x) ((x) << NOISE_LEVEL_SHIFT) 113 #define GAIN_SHIFT 0 114 #define GAIN_MASK GENMASK(9, 0) 115 #define GAIN(x) (x) 116 117 #define VAD_DET_CON1 0x60 118 #define MIN_NOISE_FIND_MODE_SHIFT 30 119 #define MIN_NOISE_FIN_MODE_MASK BIT(30) 120 #define MIN_NOISE_FIND_MODE0 0 121 #define MIN_NOISE_FIND_MODE1 BIT(30) 122 #define NOISE_CLEAN_MODE_SHIFT 29 123 #define NOISE_CLEAN_MODE_MASK BIT(29) 124 #define NOISE_CLEAN_MODE0 0 125 #define NOISE_CLEAN_MODE1 BIT(29) 126 #define NOISE_CLK_FORCE_EN_MASK BIT(28) 127 #define NOISE_CLK_AUTO_GATING 0 128 #define NOISE_CLK_FORCE_EN BIT(28) 129 #define NOISE_SAMPLE_NUM_SHIFT 16 130 #define NOISE_SAMPLE_NUM_MASK GENMASK(25, 16) 131 #define NOISE_SAMPLE_NUM ((x) << NOISE_SAMPLE_NUM_SHIFT) 132 #define SOUND_THD_MASK GENMASK(15, 0) 133 #define SOUND_THD(x) (x) 134 135 #define VAD_DET_CON2 0x64 136 #define IIR_B0_SHIFT 16 137 #define IIR_B0_MASK GENMASK(31, 16) 138 #define IIR_B0(x) ((x) << IIR_B0_SHIFT) 139 #define NOISE_ALPHA_SHIFT 8 140 #define NOISE_ALPHA_MASK GENMASK(15, 8) 141 #define NOISE_ALPHA(x) ((x) << NOISE_ALPHA_SHIFT) 142 #define NOISE_FRM_NUM_MASK GENMASK(6, 0) 143 #define NOISE_FRM_NUM(x) (x) 144 145 #define VAD_DET_CON3 0x68 146 #define IIR_B2_MASK GENMASK(31, 16) 147 #define IIR_B2(x) ((x) << 16) 148 #define IIR_B1_MASK GENMASK(15, 0) 149 #define IIR_B1(x) (x) 150 151 #define VAD_DET_CON4 0x6c 152 #define IIR_A2_MASK GENMASK(31, 16) 153 #define IIR_A2(x) ((x) << 16) 154 #define IIR_A1_MASK GENMASK(15, 0) 155 #define IIR_A1(x) (x) 156 157 #define VAD_DET_CON5 0x70 158 #define IIR_RESULT_SHIFT 16 159 #define IIR_RESULT_MASK GENMASK(31, 16) 160 #define NOISE_ABS_MASK GENMASK(15, 0) 161 #define NOISE_ABS(x) (x) 162 163 #define VAD_INT 0x74 164 #define VAD_DATA_TRANS_INT_FLAG_MASK BIT(11) 165 #define VAD_DATA_TRANS_INT_EN_MASK BIT(10) 166 #define VAD_DATA_TRANS_INT_EN BIT(10) 167 #define VAD_IDLE_MASK BIT(9) 168 #define RAM_LOOP_FLGA_MASK BIT(8) 169 #define WORK_TIMEOUT_FLAG_MASK BIT(7) 170 #define IDLE_TIMEOUT_FLAG_MASK BIT(6) 171 #define ERR_INT_FLAG_MASK BIT(5) 172 #define VAD_DET_INT_FLAG_MASK BIT(4) 173 #define WORK_TIMEOUT_INT_EN_MASK BIT(3) 174 #define WORK_TIMEOUT_INT_EN BIT(3) 175 #define IDLE_TIMEOUT_INT_EN_MASK BIT(2) 176 #define IDLE_TIMEOUT_INT_EN BIT(2) 177 #define ERR_INT_EN_MASK BIT(1) 178 #define ERR_INT_EN BIT(1) 179 #define VAD_DET_INT_EN_MASK BIT(0) 180 #define VAD_DET_INT_EN BIT(0) 181 182 #define VAD_AUX_CONTROL 0x78 183 #define SAMPLE_CNT_EN_MASK BIT(29) 184 #define SAMPLE_CNT_EN BIT(29) 185 #define SAMPLE_CNT_DIS 0 186 #define INT_TRIG_CTRL_EN_MASK BIT(28) 187 #define INT_TRIG_CTRL_EN BIT(28) 188 #define INT_TRIG_CTRL_DIS 0 189 #define INT_TRIG_VALID_THD_MASK GENMASK(27, 16) 190 #define INT_TRIG_VALID_THD(x) (((x) - 1) << 16) 191 #define DATA_TRANS_KBYTE_THD_MASK GENMASK(11, 4) 192 #define DATA_TRANS_KBYTE_THD(x) (((x) - 1) << 4) 193 #define DATA_TRANS_TRIG_INT_EN_MASK BIT(2) 194 #define DATA_TRANS_TRIG_INT_EN BIT(2) 195 #define DATA_TRANS_TRIG_INT_DIS 0 196 #define RAM_ITF_EN_MASK BIT(1) 197 #define RAM_ITF_EN 0 198 #define RAM_ITF_DIS BIT(1) 199 #define BUS_WRITE_EN_MASK BIT(0) 200 #define BUS_WRITE_EN BIT(0) 201 #define BUS_WRITE_DIS 0 202 203 #define VAD_SAMPLE_CNT 0x7c 204 #define VAD_NOISE_DATA 0x100 205 206 /* RK1808 SOC */ 207 #define RK1808_I2S0 0xff7e0800 208 #define RK1808_I2S1 0xff7f0800 209 #define RK1808_PDM 0xff800400 210 211 /* RK3308 SOC */ 212 #define ACODEC_BASE 0xff560000 213 #define ACODEC_ADC_ANA_CON0 0X340 214 215 #define RK3308_I2S_8CH_0 0xff300800 216 #define RK3308_I2S_8CH_1 0xff310800 217 #define RK3308_I2S_8CH_2 0xff320800 218 #define RK3308_I2S_8CH_3 0xff330800 219 #define RK3308_PDM_8CH 0xff380400 220 221 /* RK3568 SOC */ 222 #define RK3568_I2S_8CH_1 0xfe410800 223 #define RK3568_I2S_2CH_2 0xfe420800 224 #define RK3568_I2S_2CH_3 0xfe430800 225 #define RK3568_PDM 0xfe440400 226 227 /* RK3588 SOC */ 228 #define RK3588_I2S1_8CH 0xfe480800 229 #define RK3588_PDM0 0xfe4b0400 230 231 #endif 232