1 /* 2 * SPDX-License-Identifier: GPL-2.0+ 3 * (C) Copyright 2008-2015 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 #ifndef __ROCKCHIP_TVE_H__ 6 #define __ROCKCHIP_TVE_H__ 7 8 #define RK3036_GRF_SOC_CON3 0x0154 9 #define RK312X_GRF_TVE_CON 0x0170 10 #define m_EXTREF_EN BIT(0) 11 #define m_VBG_EN BIT(1) 12 #define m_DAC_EN BIT(2) 13 #define m_SENSE_EN BIT(3) 14 #define m_BIAS_EN (7 << 4) 15 #define m_DAC_GAIN (0x3f << 7) 16 #define v_DAC_GAIN(x) (((x) & 0x3f) << 7) 17 18 #define TV_CTRL (0x00) 19 #define m_CVBS_MODE BIT(24) 20 #define m_CLK_UPSTREAM_EN (3 << 18) 21 #define m_TIMING_EN (3 << 16) 22 #define m_LUMA_FILTER_GAIN (3 << 9) 23 #define m_LUMA_FILTER_BW BIT(8) 24 #define m_CSC_PATH (3 << 1) 25 26 #define v_CVBS_MODE(x) (((x) & 1) << 24) 27 #define v_CLK_UPSTREAM_EN(x) (((x) & 3) << 18) 28 #define v_TIMING_EN(x) (((x) & 3) << 16) 29 #define v_LUMA_FILTER_GAIN(x) (((x) & 3) << 9) 30 #define v_LUMA_FILTER_UPSAMPLE(x) (((x) & 1) << 8) 31 #define v_CSC_PATH(x) (((x) & 3) << 1) 32 33 #define TV_SYNC_TIMING (0x04) 34 #define TV_ACT_TIMING (0x08) 35 #define TV_ADJ_TIMING (0x0c) 36 #define TV_FREQ_SC (0x10) 37 #define TV_LUMA_FILTER0 (0x14) 38 #define TV_LUMA_FILTER1 (0x18) 39 #define TV_LUMA_FILTER2 (0x1C) 40 #define TV_ACT_ST (0x34) 41 #define TV_ROUTING (0x38) 42 #define m_DAC_SENSE_EN BIT(27) 43 #define m_Y_IRE_7_5 BIT(19) 44 #define m_Y_AGC_PULSE_ON BIT(15) 45 #define m_Y_VIDEO_ON BIT(11) 46 #define m_Y_SYNC_ON BIT(7) 47 #define m_YPP_MODE BIT(3) 48 #define m_MONO_EN BIT(2) 49 #define m_PIC_MODE BIT(1) 50 51 #define v_DAC_SENSE_EN(x) (((x) & 1) << 27) 52 #define v_Y_IRE_7_5(x) (((x) & 1) << 19) 53 #define v_Y_AGC_PULSE_ON(x) (((x) & 1) << 15) 54 #define v_Y_VIDEO_ON(x) (((x) & 1) << 11) 55 #define v_Y_SYNC_ON(x) (((x) & 1) << 7) 56 #define v_YPP_MODE(x) (((x) & 1) << 3) 57 #define v_MONO_EN(x) (((x) & 1) << 2) 58 #define v_PIC_MODE(x) (((x) & 1) << 1) 59 60 #define TV_SYNC_ADJUST (0x50) 61 #define TV_STATUS (0x54) 62 #define TV_RESET (0x68) 63 #define m_RESET BIT(1) 64 #define v_RESET(x) (((x) & 1) << 1) 65 #define TV_SATURATION (0x78) 66 #define TV_BW_CTRL (0x8C) 67 #define m_CHROMA_BW (3 << 4) 68 #define m_COLOR_DIFF_BW (0xf) 69 70 enum { 71 BP_FILTER_PASS = 0, 72 BP_FILTER_NTSC, 73 BP_FILTER_PAL, 74 }; 75 enum { 76 COLOR_DIFF_FILTER_OFF = 0, 77 COLOR_DIFF_FILTER_BW_0_6, 78 COLOR_DIFF_FILTER_BW_1_3, 79 COLOR_DIFF_FILTER_BW_2_0 80 }; 81 82 #define v_CHROMA_BW(x) ((3 & (x)) << 4) 83 #define v_COLOR_DIFF_BW(x) (0xF & (x)) 84 85 #define TV_BRIGHTNESS_CONTRAST (0x90) 86 87 #define VDAC_VDAC0 (0x00) 88 #define m_RST_ANA BIT(7) 89 #define m_RST_DIG BIT(6) 90 91 #define v_RST_ANA(x) (((x) & 1) << 7) 92 #define v_RST_DIG(x) (((x) & 1) << 6) 93 #define VDAC_VDAC1 (0x280) 94 #define m_CUR_REG (0xf << 4) 95 #define m_DR_PWR_DOWN BIT(1) 96 #define m_BG_PWR_DOWN BIT(0) 97 98 #define v_CUR_REG(x) (((x) & 0xf) << 4) 99 #define v_DR_PWR_DOWN(x) (((x) & 1) << 1) 100 #define v_BG_PWR_DOWN(x) (((x) & 1) << 0) 101 #define VDAC_VDAC2 (0x284) 102 #define m_CUR_CTR (0X3f) 103 104 #define v_CUR_CTR(x) (((x) & 0x3f)) 105 #define VDAC_VDAC3 (0x288) 106 #define m_CAB_EN BIT(5) 107 #define m_CAB_REF BIT(4) 108 #define m_CAB_FLAG BIT(0) 109 110 #define v_CAB_EN(x) (((x) & 1) << 5) 111 #define v_CAB_REF(x) (((x) & 1) << 4) 112 #define v_CAB_FLAG(x) (((x) & 1) << 0) 113 114 // RK3528 CVBS GRF 115 #define RK3528_VO_GRF_VDAC_DIS 0x60000 116 #define m_VDAC_DIS_NEGE_ST BIT(2) 117 #define m_VDAC_DIS_POSE_ST BIT(1) 118 #define m_STAT_VDAC_DISDET BIT(0) 119 120 #define v_VDAC_DIS_NEGE_ST(x) (((x) & 1) << 2) 121 #define v_VDAC_DIS_POSE_ST(x) (((x) & 1) << 1) 122 #define v_STAT_VDAC_DISDET(x) (((x) & 1) << 0) 123 124 #define RK3528_VO_GRF_CVBS_CON 0x60010 125 #define m_VDAC_DIS_INT_EN BIT(8) 126 #define m_VDAC_DIS_NEGE_MASK BIT(7) 127 #define m_VDAC_DIS_POSE_MASK BIT(6) 128 #define m_TVE_DCLK_POL BIT(5) 129 #define m_TVE_DCLK_EN BIT(4) 130 #define m_DCLK_UPSAMPLE_2X4X BIT(3) 131 #define m_DCLK_UPSAMPLE_EN BIT(2) 132 #define m_TVE_MODE BIT(1) 133 #define m_TVE_EN BIT(0) 134 135 #define v_VDAC_DIS_INT_EN(x) (((x) & 1) << 8) 136 #define v_VDAC_DIS_NEGE_MASK(x) (((x) & 1) << 7) 137 #define v_VDAC_DIS_POSE_MASK(x) (((x) & 1) << 6) 138 #define v_TVE_DCLK_POL(x) (((x) & 1) << 5) 139 #define v_TVE_DCLK_EN(x) (((x) & 1) << 4) 140 #define v_DCLK_UPSAMPLE_2X4X(x) (((x) & 1) << 3) 141 #define v_DCLK_UPSAMPLE_EN(x) (((x) & 1) << 2) 142 #define v_TVE_MODE(x) (((x) & 1) << 1) 143 #define v_TVE_EN(x) (((x) & 1) << 0) 144 145 // RK3528 CVBS TVE 146 #define BT656_DECODER_CTRL (0x3D00) 147 #define BT656_DECODER_CROP (0x3D04) 148 #define BT656_DECODER_SIZE (0x3D08) 149 #define BT656_DECODER_HTOTAL_HS_END (0x3D0C) 150 #define BT656_DECODER_VACT_ST_HACT_ST (0x3D10) 151 #define BT656_DECODER_VTOTAL_VS_END (0x3D14) 152 #define BT656_DECODER_VS_ST_END_F1 (0x3D18) 153 #define BT656_DECODER_DBG_REG (0x3D1C) 154 #define TVE_MODE_CTRL (0x3E00) 155 #define TVE_HOR_TIMING1 (0x3E04) 156 #define TVE_HOR_TIMING2 (0x3E08) 157 #define TVE_HOR_TIMING3 (0x3E0C) 158 #define TVE_SUB_CAR_FRQ (0x3E10) 159 #define TVE_LUMA_FILTER1 (0x3E14) 160 #define TVE_LUMA_FILTER2 (0x3E18) 161 #define TVE_LUMA_FILTER3 (0x3E1C) 162 #define TVE_LUMA_FILTER4 (0x3E20) 163 #define TVE_LUMA_FILTER5 (0x3E24) 164 #define TVE_LUMA_FILTER6 (0x3E28) 165 #define TVE_LUMA_FILTER7 (0x3E2C) 166 #define TVE_LUMA_FILTER8 (0x3E30) 167 #define TVE_IMAGE_POSITION (0x3E34) 168 #define TVE_ROUTING (0x3E38) 169 #define TVE_SYNC_ADJUST (0x3E50) 170 #define TVE_STATUS (0x3E54) 171 #define TVE_CTRL (0x3E68) 172 #define TVE_INTR_STATUS (0x3E6C) 173 #define TVE_INTR_EN (0x3E70) 174 #define TVE_INTR_CLR (0x3E74) 175 #define TVE_COLOR_BUSRT_SAT (0x3E78) 176 #define TVE_CHROMA_BANDWIDTH (0x3E8C) 177 #define TVE_BRIGHTNESS_CONTRAST (0x3E90) 178 #define TVE_ID (0x3E98) 179 #define TVE_REVISION (0x3E9C) 180 #define TVE_CLAMP (0x3EA0) 181 182 // RK3528 CVBS VDAC 183 #define VDAC_CLK_RST (0x0000) 184 #define m_ANALOG_RST BIT(7) 185 #define m_DIGITAL_RST BIT(6) 186 #define m_INPUT_CLK_INV BIT(0) 187 188 #define v_ANALOG_RST(x) (((x) & 1) << 7) 189 #define v_DIGITAL_RST(x) (((x) & 1) << 6) 190 #define v_INPUT_CLK_INV(x) (((x) & 1) << 0) 191 #define VDAC_SINE_CTRL (0x0004) 192 #define VDAC_SQUARE_CTRL (0x0008) 193 #define VDAC_LEVEL_CTRL0 (0x0018) 194 #define VDAC_LEVEL_CTRL1 (0x001C) 195 #define VDAC_PWM_REF_CTRL (0x0280) 196 #define m_REF_VOLTAGE (0xf << 4) 197 #define m_REF_RESISTOR BIT(3) 198 #define m_SMP_CLK_INV BIT(2) 199 #define m_DAC_PWN BIT(1) 200 #define m_BIAS_PWN BIT(0) 201 202 #define v_REF_VOLTAGE(x) (((x) & 0xf) << 4) 203 #define v_SMP_CLK_INV(x) (((x) & 1) << 2) 204 #define v_REF_RESISTOR(x) (((x) & 1) << 3) 205 #define v_DAC_PWN(x) (((x) & 1) << 1) 206 #define v_BIAS_PWN(x) (((x) & 1) << 0) 207 #define VDAC_CURRENT_CTRL (0x0284) 208 #define m_OUT_CURRENT (0xff << 0) 209 210 #define v_OUT_CURRENT(x) (((x) & 0xff) << 0) 211 #define VDAC_CABLE_CTRL (0x0288) 212 #define VDAC_VOLTAGE_CTRL (0x028C) 213 #define VDAC_BIAS_CLK_CTRL0 (0x0290) 214 #define VDAC_BIAS_CLK_CTRL1 (0x0294) 215 #define VDAC_AUTO_CLK_CTRL0 (0x0298) 216 #define VDAC_AUTO_CLK_CTRL1 (0x029C) 217 218 enum { 219 TVOUT_CVBS_NTSC = 0, 220 TVOUT_CVBS_PAL, 221 }; 222 223 enum { 224 INPUT_FORMAT_RGB = 0, 225 INPUT_FORMAT_YUV 226 }; 227 228 enum { 229 SOC_RK3036 = 0, 230 SOC_RK312X, 231 SOC_RK322X, 232 SOC_RK3328, 233 SOC_RK3528 234 }; 235 236 237 enum { 238 DCLK_UPSAMPLEx1 = 0, 239 DCLK_UPSAMPLEx2, 240 DCLK_UPSAMPLEx4 241 }; 242 243 #define RK30_TVE_REGBASE 0x10118000 + 0x200 244 #define MAX_TVE_COUNT 2 245 246 #ifdef TVEDEBUG 247 #define TVEDBG(format, ...) \ 248 printf("TVE: " format, ## __VA_ARGS__) 249 #else 250 #define TVEDBG(format, ...) 251 #endif 252 253 #endif /* __ROCKCHIP_TVE_H__ */ 254