1 /* 2 * sound/soc/rockchip/rockchip_i2s_tdm.h 3 * 4 * ALSA SoC Audio Layer - Rockchip I2S_TDM Controller driver 5 * 6 * Copyright (c) 2018 Rockchip Electronics Co. Ltd. 7 * Author: Sugar Zhang <sugar.zhang@rock-chips.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #ifndef _ROCKCHIP_I2S_TDM_H 15 #define _ROCKCHIP_I2S_TDM_H 16 17 /* 18 * TXCR 19 * transmit operation control register 20 */ 21 #define I2S_TXCR_PATH_SHIFT(x) (23 + (x) * 2) 22 #define I2S_TXCR_PATH_MASK(x) (0x3 << I2S_TXCR_PATH_SHIFT(x)) 23 #define I2S_TXCR_PATH(x, v) ((v) << I2S_TXCR_PATH_SHIFT(x)) 24 #define I2S_TXCR_RCNT_SHIFT 17 25 #define I2S_TXCR_RCNT_MASK (0x3f << I2S_TXCR_RCNT_SHIFT) 26 #define I2S_TXCR_CSR_SHIFT 15 27 #define I2S_TXCR_CSR(x) ((x) << I2S_TXCR_CSR_SHIFT) 28 #define I2S_TXCR_CSR_MASK (3 << I2S_TXCR_CSR_SHIFT) 29 #define I2S_TXCR_HWT BIT(14) 30 #define I2S_TXCR_SJM_SHIFT 12 31 #define I2S_TXCR_SJM_R (0 << I2S_TXCR_SJM_SHIFT) 32 #define I2S_TXCR_SJM_L (1 << I2S_TXCR_SJM_SHIFT) 33 #define I2S_TXCR_FBM_SHIFT 11 34 #define I2S_TXCR_FBM_MSB (0 << I2S_TXCR_FBM_SHIFT) 35 #define I2S_TXCR_FBM_LSB (1 << I2S_TXCR_FBM_SHIFT) 36 #define I2S_TXCR_IBM_SHIFT 9 37 #define I2S_TXCR_IBM_NORMAL (0 << I2S_TXCR_IBM_SHIFT) 38 #define I2S_TXCR_IBM_LSJM (1 << I2S_TXCR_IBM_SHIFT) 39 #define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR_IBM_SHIFT) 40 #define I2S_TXCR_IBM_MASK (3 << I2S_TXCR_IBM_SHIFT) 41 #define I2S_TXCR_PBM_SHIFT 7 42 #define I2S_TXCR_PBM_MODE(x) ((x) << I2S_TXCR_PBM_SHIFT) 43 #define I2S_TXCR_PBM_MASK (3 << I2S_TXCR_PBM_SHIFT) 44 #define I2S_TXCR_TFS_SHIFT 5 45 #define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT) 46 #define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT) 47 #define I2S_TXCR_TFS_TDM_PCM (2 << I2S_TXCR_TFS_SHIFT) 48 #define I2S_TXCR_TFS_TDM_I2S (3 << I2S_TXCR_TFS_SHIFT) 49 #define I2S_TXCR_TFS_MASK (3 << I2S_TXCR_TFS_SHIFT) 50 #define I2S_TXCR_VDW_SHIFT 0 51 #define I2S_TXCR_VDW(x) (((x) - 1) << I2S_TXCR_VDW_SHIFT) 52 #define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT) 53 54 /* 55 * RXCR 56 * receive operation control register 57 */ 58 #define I2S_RXCR_PATH_SHIFT(x) (17 + (x) * 2) 59 #define I2S_RXCR_PATH_MASK(x) (0x3 << I2S_RXCR_PATH_SHIFT(x)) 60 #define I2S_RXCR_PATH(x, v) ((v) << I2S_RXCR_PATH_SHIFT(x)) 61 #define I2S_RXCR_CSR_SHIFT 15 62 #define I2S_RXCR_CSR(x) ((x) << I2S_RXCR_CSR_SHIFT) 63 #define I2S_RXCR_CSR_MASK (3 << I2S_RXCR_CSR_SHIFT) 64 #define I2S_RXCR_HWT BIT(14) 65 #define I2S_RXCR_SJM_SHIFT 12 66 #define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT) 67 #define I2S_RXCR_SJM_L (1 << I2S_RXCR_SJM_SHIFT) 68 #define I2S_RXCR_FBM_SHIFT 11 69 #define I2S_RXCR_FBM_MSB (0 << I2S_RXCR_FBM_SHIFT) 70 #define I2S_RXCR_FBM_LSB (1 << I2S_RXCR_FBM_SHIFT) 71 #define I2S_RXCR_IBM_SHIFT 9 72 #define I2S_RXCR_IBM_NORMAL (0 << I2S_RXCR_IBM_SHIFT) 73 #define I2S_RXCR_IBM_LSJM (1 << I2S_RXCR_IBM_SHIFT) 74 #define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR_IBM_SHIFT) 75 #define I2S_RXCR_IBM_MASK (3 << I2S_RXCR_IBM_SHIFT) 76 #define I2S_RXCR_PBM_SHIFT 7 77 #define I2S_RXCR_PBM_MODE(x) ((x) << I2S_RXCR_PBM_SHIFT) 78 #define I2S_RXCR_PBM_MASK (3 << I2S_RXCR_PBM_SHIFT) 79 #define I2S_RXCR_TFS_SHIFT 5 80 #define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT) 81 #define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT) 82 #define I2S_RXCR_TFS_TDM_PCM (2 << I2S_RXCR_TFS_SHIFT) 83 #define I2S_RXCR_TFS_TDM_I2S (3 << I2S_RXCR_TFS_SHIFT) 84 #define I2S_RXCR_TFS_MASK (3 << I2S_RXCR_TFS_SHIFT) 85 #define I2S_RXCR_VDW_SHIFT 0 86 #define I2S_RXCR_VDW(x) (((x) - 1) << I2S_RXCR_VDW_SHIFT) 87 #define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT) 88 89 /* 90 * CKR 91 * clock generation register 92 */ 93 #define I2S_CKR_TRCM_SHIFT 28 94 #define I2S_CKR_TRCM(x) ((x) << I2S_CKR_TRCM_SHIFT) 95 #define I2S_CKR_TRCM_TXRX (0 << I2S_CKR_TRCM_SHIFT) 96 #define I2S_CKR_TRCM_TXONLY (1 << I2S_CKR_TRCM_SHIFT) 97 #define I2S_CKR_TRCM_RXONLY (2 << I2S_CKR_TRCM_SHIFT) 98 #define I2S_CKR_TRCM_MASK (3 << I2S_CKR_TRCM_SHIFT) 99 #define I2S_CKR_MSS_SHIFT 27 100 #define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT) 101 #define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT) 102 #define I2S_CKR_MSS_MASK (1 << I2S_CKR_MSS_SHIFT) 103 #define I2S_CKR_CKP_SHIFT 26 104 #define I2S_CKR_CKP_NORMAL (0 << I2S_CKR_CKP_SHIFT) 105 #define I2S_CKR_CKP_INVERTED (1 << I2S_CKR_CKP_SHIFT) 106 #define I2S_CKR_CKP_MASK (1 << I2S_CKR_CKP_SHIFT) 107 #define I2S_CKR_RLP_SHIFT 25 108 #define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT) 109 #define I2S_CKR_RLP_INVERTED (1 << I2S_CKR_RLP_SHIFT) 110 #define I2S_CKR_RLP_MASK (1 << I2S_CKR_RLP_SHIFT) 111 #define I2S_CKR_TLP_SHIFT 24 112 #define I2S_CKR_TLP_NORMAL (0 << I2S_CKR_TLP_SHIFT) 113 #define I2S_CKR_TLP_INVERTED (1 << I2S_CKR_TLP_SHIFT) 114 #define I2S_CKR_TLP_MASK (1 << I2S_CKR_TLP_SHIFT) 115 #define I2S_CKR_MDIV_SHIFT 16 116 #define I2S_CKR_MDIV(x) (((x) - 1) << I2S_CKR_MDIV_SHIFT) 117 #define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT) 118 #define I2S_CKR_RSD_SHIFT 8 119 #define I2S_CKR_RSD(x) (((x) - 1) << I2S_CKR_RSD_SHIFT) 120 #define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT) 121 #define I2S_CKR_TSD_SHIFT 0 122 #define I2S_CKR_TSD(x) (((x) - 1) << I2S_CKR_TSD_SHIFT) 123 #define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT) 124 125 /* 126 * FIFOLR 127 * FIFO level register 128 */ 129 #define I2S_FIFOLR_RFL_SHIFT 24 130 #define I2S_FIFOLR_RFL_MASK (0x3f << I2S_FIFOLR_RFL_SHIFT) 131 #define I2S_FIFOLR_TFL3_SHIFT 18 132 #define I2S_FIFOLR_TFL3_MASK (0x3f << I2S_FIFOLR_TFL3_SHIFT) 133 #define I2S_FIFOLR_TFL2_SHIFT 12 134 #define I2S_FIFOLR_TFL2_MASK (0x3f << I2S_FIFOLR_TFL2_SHIFT) 135 #define I2S_FIFOLR_TFL1_SHIFT 6 136 #define I2S_FIFOLR_TFL1_MASK (0x3f << I2S_FIFOLR_TFL1_SHIFT) 137 #define I2S_FIFOLR_TFL0_SHIFT 0 138 #define I2S_FIFOLR_TFL0_MASK (0x3f << I2S_FIFOLR_TFL0_SHIFT) 139 140 /* 141 * DMACR 142 * DMA control register 143 */ 144 #define I2S_DMACR_RDE_SHIFT 24 145 #define I2S_DMACR_RDE_DISABLE (0 << I2S_DMACR_RDE_SHIFT) 146 #define I2S_DMACR_RDE_ENABLE (1 << I2S_DMACR_RDE_SHIFT) 147 #define I2S_DMACR_RDE_MASK (1 << I2S_DMACR_RDE_SHIFT) 148 #define I2S_DMACR_RDE(x) ((x) << I2S_DMACR_RDE_SHIFT) 149 #define I2S_DMACR_RDL_SHIFT 16 150 #define I2S_DMACR_RDL(x) (((x) - 1) << I2S_DMACR_RDL_SHIFT) 151 #define I2S_DMACR_RDL_MASK (0x1f << I2S_DMACR_RDL_SHIFT) 152 #define I2S_DMACR_TDE_SHIFT 8 153 #define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT) 154 #define I2S_DMACR_TDE_ENABLE (1 << I2S_DMACR_TDE_SHIFT) 155 #define I2S_DMACR_TDE_MASK (1 << I2S_DMACR_TDE_SHIFT) 156 #define I2S_DMACR_TDE(x) ((x) << I2S_DMACR_TDE_SHIFT) 157 #define I2S_DMACR_TDL_SHIFT 0 158 #define I2S_DMACR_TDL(x) ((x) << I2S_DMACR_TDL_SHIFT) 159 #define I2S_DMACR_TDL_MASK (0x1f << I2S_DMACR_TDL_SHIFT) 160 161 /* 162 * INTCR 163 * interrupt control register 164 */ 165 #define I2S_INTCR_RFT_SHIFT 20 166 #define I2S_INTCR_RFT(x) (((x) - 1) << I2S_INTCR_RFT_SHIFT) 167 #define I2S_INTCR_RXOIC BIT(18) 168 #define I2S_INTCR_RXOIE_SHIFT 17 169 #define I2S_INTCR_RXOIE_MASK (1 << I2S_INTCR_RXOIE_SHIFT) 170 #define I2S_INTCR_RXOIE(x) ((x) << I2S_INTCR_RXOIE_SHIFT) 171 #define I2S_INTCR_RXFIE_SHIFT 16 172 #define I2S_INTCR_RXFIE_DISABLE (0 << I2S_INTCR_RXFIE_SHIFT) 173 #define I2S_INTCR_RXFIE_ENABLE (1 << I2S_INTCR_RXFIE_SHIFT) 174 #define I2S_INTCR_TFT_SHIFT 4 175 #define I2S_INTCR_TFT(x) (((x) - 1) << I2S_INTCR_TFT_SHIFT) 176 #define I2S_INTCR_TFT_MASK (0x1f << I2S_INTCR_TFT_SHIFT) 177 #define I2S_INTCR_TXUIC BIT(2) 178 #define I2S_INTCR_TXUIE_SHIFT 1 179 #define I2S_INTCR_TXUIE_MASK (1 << I2S_INTCR_TXUIE_SHIFT) 180 #define I2S_INTCR_TXUIE(x) ((x) << I2S_INTCR_TXUIE_SHIFT) 181 182 /* 183 * INTSR 184 * interrupt status register 185 */ 186 #define I2S_INTSR_TXEIE_SHIFT 0 187 #define I2S_INTSR_TXEIE_DISABLE (0 << I2S_INTSR_TXEIE_SHIFT) 188 #define I2S_INTSR_TXEIE_ENABLE (1 << I2S_INTSR_TXEIE_SHIFT) 189 #define I2S_INTSR_RXOI_SHIFT 17 190 #define I2S_INTSR_RXOI_INA (0 << I2S_INTSR_RXOI_SHIFT) 191 #define I2S_INTSR_RXOI_ACT (1 << I2S_INTSR_RXOI_SHIFT) 192 #define I2S_INTSR_RXFI_SHIFT 16 193 #define I2S_INTSR_RXFI_INA (0 << I2S_INTSR_RXFI_SHIFT) 194 #define I2S_INTSR_RXFI_ACT (1 << I2S_INTSR_RXFI_SHIFT) 195 #define I2S_INTSR_TXUI_SHIFT 1 196 #define I2S_INTSR_TXUI_INA (0 << I2S_INTSR_TXUI_SHIFT) 197 #define I2S_INTSR_TXUI_ACT (1 << I2S_INTSR_TXUI_SHIFT) 198 #define I2S_INTSR_TXEI_SHIFT 0 199 #define I2S_INTSR_TXEI_INA (0 << I2S_INTSR_TXEI_SHIFT) 200 #define I2S_INTSR_TXEI_ACT (1 << I2S_INTSR_TXEI_SHIFT) 201 202 /* 203 * XFER 204 * Transfer start register 205 */ 206 /* 207 * lp mode2 swap: 208 * i2s sdi0_l <- i2s sdo0_l 209 * i2s sdi0_r <- codec sdo_r 210 * 211 * lp mode2: 212 * i2s sdi0_l <- codec sdo_l 213 * i2s sdi0_r <- i2s sdo0_r 214 * 215 * lp mode1: 216 * i2s sdi0_l <- codec sdo_l 217 * i2s sdi0_r <- codec sdo_r 218 * i2s sdi1_l <- i2s sdo0_l 219 * i2s sdi1_r <- i2s sdo0_r 220 * 221 */ 222 #define I2S_XFER_LP_MODE_MASK GENMASK(4, 2) 223 #define I2S_XFER_LP_MODE_2_SWAP (BIT(4) | BIT(3)) 224 #define I2S_XFER_LP_MODE_2 BIT(3) 225 #define I2S_XFER_LP_MODE_1 BIT(2) 226 #define I2S_XFER_LP_MODE_DIS 0 227 #define I2S_XFER_RXS_SHIFT 1 228 #define I2S_XFER_RXS_STOP (0 << I2S_XFER_RXS_SHIFT) 229 #define I2S_XFER_RXS_START (1 << I2S_XFER_RXS_SHIFT) 230 #define I2S_XFER_RXS_MASK (1 << I2S_XFER_RXS_SHIFT) 231 #define I2S_XFER_RXS(x) ((x) << I2S_XFER_RXS_SHIFT) 232 #define I2S_XFER_TXS_SHIFT 0 233 #define I2S_XFER_TXS_STOP (0 << I2S_XFER_TXS_SHIFT) 234 #define I2S_XFER_TXS_START (1 << I2S_XFER_TXS_SHIFT) 235 #define I2S_XFER_TXS_MASK (1 << I2S_XFER_TXS_SHIFT) 236 #define I2S_XFER_TXS(x) ((x) << I2S_XFER_TXS_SHIFT) 237 238 /* 239 * CLR 240 * clear SCLK domain logic register 241 */ 242 #define I2S_CLR_RXC BIT(1) 243 #define I2S_CLR_TXC BIT(0) 244 245 /* 246 * TXDR 247 * Transimt FIFO data register, write only. 248 */ 249 #define I2S_TXDR_MASK (0xff) 250 251 /* 252 * RXDR 253 * Receive FIFO data register, write only. 254 */ 255 #define I2S_RXDR_MASK (0xff) 256 257 /* 258 * TDM_CTRL 259 * TDM ctrl register 260 */ 261 #define TDM_FSYNC_WIDTH_SEL1_MSK GENMASK(20, 18) 262 #define TDM_FSYNC_WIDTH_SEL1(x) (((x) - 1) << 18) 263 #define TDM_FSYNC_WIDTH_SEL0_MSK BIT(17) 264 #define TDM_FSYNC_WIDTH_HALF_FRAME 0 265 #define TDM_FSYNC_WIDTH_ONE_FRAME BIT(17) 266 #define TDM_SHIFT_CTRL_MSK GENMASK(16, 14) 267 #define TDM_SHIFT_CTRL(x) ((x) << 14) 268 #define TDM_SLOT_BIT_WIDTH_MSK GENMASK(13, 9) 269 #define TDM_SLOT_BIT_WIDTH(x) (((x) - 1) << 9) 270 #define TDM_FRAME_WIDTH_MSK GENMASK(8, 0) 271 #define TDM_FRAME_WIDTH(x) (((x) - 1) << 0) 272 273 /* 274 * CLKDIV 275 * Mclk div register 276 */ 277 #define I2S_CLKDIV_TXM_SHIFT 0 278 #define I2S_CLKDIV_TXM(x) (((x) - 1) << I2S_CLKDIV_TXM_SHIFT) 279 #define I2S_CLKDIV_TXM_MASK (0xff << I2S_CLKDIV_TXM_SHIFT) 280 #define I2S_CLKDIV_RXM_SHIFT 8 281 #define I2S_CLKDIV_RXM(x) (((x) - 1) << I2S_CLKDIV_RXM_SHIFT) 282 #define I2S_CLKDIV_RXM_MASK (0xff << I2S_CLKDIV_RXM_SHIFT) 283 284 /* Clock divider id */ 285 enum { 286 ROCKCHIP_DIV_MCLK = 0, 287 ROCKCHIP_DIV_BCLK, 288 }; 289 290 /* channel select */ 291 #define I2S_CSR_SHIFT 15 292 #define I2S_CHN_2 (0 << I2S_CSR_SHIFT) 293 #define I2S_CHN_4 (1 << I2S_CSR_SHIFT) 294 #define I2S_CHN_6 (2 << I2S_CSR_SHIFT) 295 #define I2S_CHN_8 (3 << I2S_CSR_SHIFT) 296 297 /* io direction cfg register */ 298 #define I2S_IO_DIRECTION_MASK (7) 299 #define I2S_IO_8CH_OUT_2CH_IN (7) 300 #define I2S_IO_6CH_OUT_4CH_IN (3) 301 #define I2S_IO_4CH_OUT_6CH_IN (1) 302 #define I2S_IO_2CH_OUT_8CH_IN (0) 303 304 /* I2S REGS */ 305 #define I2S_TXCR (0x0000) 306 #define I2S_RXCR (0x0004) 307 #define I2S_CKR (0x0008) 308 #define I2S_TXFIFOLR (0x000c) 309 #define I2S_DMACR (0x0010) 310 #define I2S_INTCR (0x0014) 311 #define I2S_INTSR (0x0018) 312 #define I2S_XFER (0x001c) 313 #define I2S_CLR (0x0020) 314 #define I2S_TXDR (0x0024) 315 #define I2S_RXDR (0x0028) 316 #define I2S_RXFIFOLR (0x002c) 317 #define I2S_TDM_TXCR (0x0030) 318 #define I2S_TDM_RXCR (0x0034) 319 #define I2S_CLKDIV (0x0038) 320 321 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16)) 322 323 /* PX30 GRF CONFIGS*/ 324 #define PX30_I2S0_CLK_IN_SRC_FROM_TX HIWORD_UPDATE(1, 13, 12) 325 #define PX30_I2S0_CLK_IN_SRC_FROM_RX HIWORD_UPDATE(2, 13, 12) 326 #define PX30_I2S0_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(1, 5, 5) 327 #define PX30_I2S0_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(0, 5, 5) 328 329 #define PX30_I2S0_CLK_TXONLY \ 330 (PX30_I2S0_MCLK_OUT_SRC_FROM_TX | PX30_I2S0_CLK_IN_SRC_FROM_TX) 331 332 #define PX30_I2S0_CLK_RXONLY \ 333 (PX30_I2S0_MCLK_OUT_SRC_FROM_RX | PX30_I2S0_CLK_IN_SRC_FROM_RX) 334 335 /* RK1808 GRF CONFIGS*/ 336 #define RK1808_I2S0_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 2, 2) 337 #define RK1808_I2S0_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 2, 2) 338 #define RK1808_I2S0_CLK_IN_SRC_FROM_TX HIWORD_UPDATE(1, 1, 0) 339 #define RK1808_I2S0_CLK_IN_SRC_FROM_RX HIWORD_UPDATE(2, 1, 0) 340 341 #define RK1808_I2S0_CLK_TXONLY \ 342 (RK1808_I2S0_MCLK_OUT_SRC_FROM_TX | RK1808_I2S0_CLK_IN_SRC_FROM_TX) 343 344 #define RK1808_I2S0_CLK_RXONLY \ 345 (RK1808_I2S0_MCLK_OUT_SRC_FROM_RX | RK1808_I2S0_CLK_IN_SRC_FROM_RX) 346 347 /* RK3308 GRF CONFIGS*/ 348 #define RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 10, 10) 349 #define RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 10, 10) 350 #define RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_TX HIWORD_UPDATE(1, 9, 9) 351 #define RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_RX HIWORD_UPDATE(0, 9, 9) 352 #define RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_RX HIWORD_UPDATE(1, 8, 8) 353 #define RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_TX HIWORD_UPDATE(0, 8, 8) 354 #define RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 2, 2) 355 #define RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 2, 2) 356 #define RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_TX HIWORD_UPDATE(1, 1, 1) 357 #define RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_RX HIWORD_UPDATE(0, 1, 1) 358 #define RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_RX HIWORD_UPDATE(1, 0, 0) 359 #define RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_TX HIWORD_UPDATE(0, 0, 0) 360 361 #define RK3308_I2S0_CLK_TXONLY \ 362 (RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_TX | \ 363 RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_TX | \ 364 RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_TX) 365 366 #define RK3308_I2S0_CLK_RXONLY \ 367 (RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_RX | \ 368 RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_RX | \ 369 RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_RX) 370 371 #define RK3308_I2S1_CLK_TXONLY \ 372 (RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_TX | \ 373 RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_TX | \ 374 RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_TX) 375 376 #define RK3308_I2S1_CLK_RXONLY \ 377 (RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_RX | \ 378 RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_RX | \ 379 RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_RX) 380 381 /* RK3568 GRF CONFIGS*/ 382 #define RK3568_I2S1_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(1, 5, 5) 383 #define RK3568_I2S1_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(0, 5, 5) 384 385 #define RK3568_I2S1_CLK_TXONLY \ 386 RK3568_I2S1_MCLK_OUT_SRC_FROM_TX 387 388 #define RK3568_I2S1_CLK_RXONLY \ 389 RK3568_I2S1_MCLK_OUT_SRC_FROM_RX 390 391 #define RK3568_I2S3_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(1, 15, 15) 392 #define RK3568_I2S3_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(0, 15, 15) 393 #define RK3568_I2S3_SCLK_SRC_FROM_TX HIWORD_UPDATE(1, 7, 7) 394 #define RK3568_I2S3_SCLK_SRC_FROM_RX HIWORD_UPDATE(0, 7, 7) 395 #define RK3568_I2S3_LRCK_SRC_FROM_TX HIWORD_UPDATE(1, 6, 6) 396 #define RK3568_I2S3_LRCK_SRC_FROM_RX HIWORD_UPDATE(0, 6, 6) 397 398 #define RK3568_I2S3_MCLK_TXONLY \ 399 RK3568_I2S3_MCLK_OUT_SRC_FROM_TX 400 401 #define RK3568_I2S3_CLK_TXONLY \ 402 (RK3568_I2S3_SCLK_SRC_FROM_TX | \ 403 RK3568_I2S3_LRCK_SRC_FROM_TX) 404 405 #define RK3568_I2S3_MCLK_RXONLY \ 406 RK3568_I2S3_MCLK_OUT_SRC_FROM_RX 407 408 #define RK3568_I2S3_CLK_RXONLY \ 409 (RK3568_I2S3_SCLK_SRC_FROM_RX | \ 410 RK3568_I2S3_LRCK_SRC_FROM_RX) 411 412 /* RV1126 GRF CONFIGS*/ 413 #define RV1126_I2S0_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 9, 9) 414 #define RV1126_I2S0_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 9, 9) 415 416 #define RV1126_I2S0_CLK_TXONLY \ 417 RV1126_I2S0_MCLK_OUT_SRC_FROM_TX 418 419 #define RV1126_I2S0_CLK_RXONLY \ 420 RV1126_I2S0_MCLK_OUT_SRC_FROM_RX 421 422 #endif /* _ROCKCHIP_I2S_TDM_H */ 423