1 /* 2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 3 * Author: 4 * algea cao <algea.cao@rock-chips.com> 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 #ifndef __ROCKCHIP_DRM_TVE_H__ 16 #define __ROCKCHIP_DRM_TVE_H__ 17 18 #define RK3036_GRF_SOC_CON3 0x0154 19 #define RK312X_GRF_TVE_CON 0x0170 20 #define m_EXTREF_EN BIT(0) 21 #define m_VBG_EN BIT(1) 22 #define m_DAC_EN BIT(2) 23 #define m_SENSE_EN BIT(3) 24 #define m_BIAS_EN (7 << 4) 25 #define m_DAC_GAIN (0x3f << 7) 26 #define v_DAC_GAIN(x) (((x) & 0x3f) << 7) 27 28 #define TV_CTRL (0x00) 29 #define m_CVBS_MODE BIT(24) 30 #define m_CLK_UPSTREAM_EN (3 << 18) 31 #define m_TIMING_EN (3 << 16) 32 #define m_LUMA_FILTER_GAIN (3 << 9) 33 #define m_LUMA_FILTER_BW BIT(8) 34 #define m_CSC_PATH (3 << 1) 35 36 #define v_CVBS_MODE(x) (((x) & 1) << 24) 37 #define v_CLK_UPSTREAM_EN(x) (((x) & 3) << 18) 38 #define v_TIMING_EN(x) (((x) & 3) << 16) 39 #define v_LUMA_FILTER_GAIN(x) (((x) & 3) << 9) 40 #define v_LUMA_FILTER_UPSAMPLE(x) (((x) & 1) << 8) 41 #define v_CSC_PATH(x) (((x) & 3) << 1) 42 43 #define TV_SYNC_TIMING (0x04) 44 #define TV_ACT_TIMING (0x08) 45 #define TV_ADJ_TIMING (0x0c) 46 #define TV_FREQ_SC (0x10) 47 #define TV_LUMA_FILTER0 (0x14) 48 #define TV_LUMA_FILTER1 (0x18) 49 #define TV_LUMA_FILTER2 (0x1C) 50 #define TV_ACT_ST (0x34) 51 #define TV_ROUTING (0x38) 52 #define m_DAC_SENSE_EN BIT(27) 53 #define m_Y_IRE_7_5 BIT(19) 54 #define m_Y_AGC_PULSE_ON BIT(15) 55 #define m_Y_VIDEO_ON BIT(11) 56 #define m_Y_SYNC_ON BIT(7) 57 #define m_YPP_MODE BIT(3) 58 #define m_MONO_EN BIT(2) 59 #define m_PIC_MODE BIT(1) 60 61 #define v_DAC_SENSE_EN(x) (((x) & 1) << 27) 62 #define v_Y_IRE_7_5(x) (((x) & 1) << 19) 63 #define v_Y_AGC_PULSE_ON(x) (((x) & 1) << 15) 64 #define v_Y_VIDEO_ON(x) (((x) & 1) << 11) 65 #define v_Y_SYNC_ON(x) (((x) & 1) << 7) 66 #define v_YPP_MODE(x) (((x) & 1) << 3) 67 #define v_MONO_EN(x) (((x) & 1) << 2) 68 #define v_PIC_MODE(x) (((x) & 1) << 1) 69 70 #define TV_SYNC_ADJUST (0x50) 71 #define TV_STATUS (0x54) 72 #define TV_RESET (0x68) 73 #define m_RESET BIT(1) 74 #define v_RESET(x) (((x) & 1) << 1) 75 #define TV_SATURATION (0x78) 76 #define TV_BW_CTRL (0x8C) 77 #define m_CHROMA_BW (3 << 4) 78 #define m_COLOR_DIFF_BW (0xf) 79 80 enum { 81 BP_FILTER_PASS = 0, 82 BP_FILTER_NTSC, 83 BP_FILTER_PAL, 84 }; 85 enum { 86 COLOR_DIFF_FILTER_OFF = 0, 87 COLOR_DIFF_FILTER_BW_0_6, 88 COLOR_DIFF_FILTER_BW_1_3, 89 COLOR_DIFF_FILTER_BW_2_0 90 }; 91 92 #define v_CHROMA_BW(x) ((3 & (x)) << 4) 93 #define v_COLOR_DIFF_BW(x) (0xF & (x)) 94 95 #define TV_BRIGHTNESS_CONTRAST (0x90) 96 97 #define VDAC_VDAC0 (0x00) 98 #define m_RST_ANA BIT(7) 99 #define m_RST_DIG BIT(6) 100 101 #define v_RST_ANA(x) (((x) & 1) << 7) 102 #define v_RST_DIG(x) (((x) & 1) << 6) 103 #define VDAC_VDAC1 (0x280) 104 #define m_CUR_REG (0xf << 4) 105 #define m_DR_PWR_DOWN BIT(1) 106 #define m_BG_PWR_DOWN BIT(0) 107 108 #define v_CUR_REG(x) (((x) & 0xf) << 4) 109 #define v_DR_PWR_DOWN(x) (((x) & 1) << 1) 110 #define v_BG_PWR_DOWN(x) (((x) & 1) << 0) 111 #define VDAC_VDAC2 (0x284) 112 #define m_CUR_CTR (0X3f) 113 114 #define v_CUR_CTR(x) (((x) & 0x3f)) 115 #define VDAC_VDAC3 (0x288) 116 #define m_CAB_EN BIT(5) 117 #define m_CAB_REF BIT(4) 118 #define m_CAB_FLAG BIT(0) 119 120 #define v_CAB_EN(x) (((x) & 1) << 5) 121 #define v_CAB_REF(x) (((x) & 1) << 4) 122 #define v_CAB_FLAG(x) (((x) & 1) << 0) 123 124 // RK3528 CVBS GRF 125 #define RK3528_VO_GRF_CVBS_CON 0x60010 126 #define m_TVE_DCLK_POL BIT(5) 127 #define m_TVE_DCLK_EN BIT(4) 128 #define m_DCLK_UPSAMPLE_2X4X BIT(3) 129 #define m_DCLK_UPSAMPLE_EN BIT(2) 130 #define m_TVE_MODE BIT(1) 131 #define m_TVE_EN BIT(0) 132 133 #define v_TVE_DCLK_POL(x) (((x) & 1) << 5) 134 #define v_TVE_DCLK_EN(x) (((x) & 1) << 4) 135 #define v_DCLK_UPSAMPLE_2X4X(x) (((x) & 1) << 3) 136 #define v_DCLK_UPSAMPLE_EN(x) (((x) & 1) << 2) 137 #define v_TVE_MODE(x) (((x) & 1) << 1) 138 #define v_TVE_EN(x) (((x) & 1) << 0) 139 140 // RK3528 CVBS BT656 141 #define BT656_DECODER_CTRL (0x3D00) 142 #define BT656_DECODER_CROP (0x3D04) 143 #define BT656_DECODER_SIZE (0x3D08) 144 #define BT656_DECODER_HTOTAL_HS_END (0x3D0C) 145 #define BT656_DECODER_VACT_ST_HACT_ST (0x3D10) 146 #define BT656_DECODER_VTOTAL_VS_END (0x3D14) 147 #define BT656_DECODER_VS_ST_END_F1 (0x3D18) 148 #define BT656_DECODER_DBG_REG (0x3D1C) 149 150 // RK3528 CVBS TVE 151 #define TVE_MODE_CTRL (0x3E00) 152 #define TVE_HOR_TIMING1 (0x3E04) 153 #define TVE_HOR_TIMING2 (0x3E08) 154 #define TVE_HOR_TIMING3 (0x3E0C) 155 #define TVE_SUB_CAR_FRQ (0x3E10) 156 #define TVE_LUMA_FILTER1 (0x3E14) 157 #define TVE_LUMA_FILTER2 (0x3E18) 158 #define TVE_LUMA_FILTER3 (0x3E1C) 159 #define TVE_LUMA_FILTER4 (0x3E20) 160 #define TVE_LUMA_FILTER5 (0x3E24) 161 #define TVE_LUMA_FILTER6 (0x3E28) 162 #define TVE_LUMA_FILTER7 (0x3E2C) 163 #define TVE_LUMA_FILTER8 (0x3E30) 164 #define TVE_IMAGE_POSITION (0x3E34) 165 #define TVE_ROUTING (0x3E38) 166 #define TVE_SYNC_ADJUST (0x3E50) 167 #define TVE_STATUS (0x3E54) 168 #define TVE_CTRL (0x3E68) 169 #define TVE_INTR_STATUS (0x3E6C) 170 #define TVE_INTR_EN (0x3E70) 171 #define TVE_INTR_CLR (0x3E74) 172 #define TVE_COLOR_BUSRT_SAT (0x3E78) 173 #define TVE_CHROMA_BANDWIDTH (0x3E8C) 174 #define TVE_BRIGHTNESS_CONTRAST (0x3E90) 175 #define TVE_ID (0x3E98) 176 #define TVE_REVISION (0x3E9C) 177 #define TVE_CLAMP (0x3EA0) 178 179 // RK3528 CVBS VDAC 180 #define VDAC_CLK_RST (0x0000) 181 #define m_ANALOG_RST BIT(7) 182 #define m_DIGITAL_RST BIT(6) 183 #define m_INPUT_CLK_INV BIT(0) 184 185 #define v_ANALOG_RST(x) (((x) & 1) << 7) 186 #define v_DIGITAL_RST(x) (((x) & 1) << 6) 187 #define v_INPUT_CLK_INV(x) (((x) & 1) << 0) 188 #define VDAC_SINE_CTRL (0x0004) 189 #define VDAC_SQUARE_CTRL (0x0008) 190 #define VDAC_LEVEL_CTRL0 (0x0018) 191 #define VDAC_LEVEL_CTRL1 (0x001C) 192 #define VDAC_PWM_REF_CTRL (0x0280) 193 #define m_REF_VOLTAGE (0xf << 4) 194 #define m_REF_RESISTOR BIT(3) 195 #define m_SMP_CLK_INV BIT(2) 196 #define m_DAC_PWN BIT(1) 197 #define m_BIAS_PWN BIT(0) 198 199 #define v_REF_VOLTAGE(x) (((x) & 0xf) << 4) 200 #define v_SMP_CLK_INV(x) (((x) & 1) << 2) 201 #define v_REF_RESISTOR(x) (((x) & 1) << 3) 202 #define v_DAC_PWN(x) (((x) & 1) << 1) 203 #define v_BIAS_PWN(x) (((x) & 1) << 0) 204 #define VDAC_CURRENT_CTRL (0x0284) 205 #define m_OUT_CURRENT (0xff << 0) 206 207 #define v_OUT_CURRENT(x) (((x) & 0xff) << 0) 208 #define VDAC_CABLE_CTRL (0x0288) 209 #define VDAC_VOLTAGE_CTRL (0x028C) 210 #define VDAC_BIAS_CLK_CTRL0 (0x0290) 211 #define VDAC_BIAS_CLK_CTRL1 (0x0294) 212 #define VDAC_AUTO_CLK_CTRL0 (0x0298) 213 #define VDAC_AUTO_CLK_CTRL1 (0x029C) 214 215 enum { 216 TVOUT_CVBS_NTSC = 0, 217 TVOUT_CVBS_PAL, 218 }; 219 220 enum { 221 INPUT_FORMAT_RGB = 0, 222 INPUT_FORMAT_YUV 223 }; 224 225 enum { 226 SOC_RK3036 = 0, 227 SOC_RK312X, 228 SOC_RK322X, 229 SOC_RK3328, 230 SOC_RK3528 231 }; 232 233 enum { 234 DCLK_UPSAMPLEx1 = 0, 235 DCLK_UPSAMPLEx2, 236 DCLK_UPSAMPLEx4 237 }; 238 239 #define grf_writel(offset, v) do { \ 240 writel_relaxed(v, RK_GRF_VIRT + (offset)); \ 241 dsb(sy); \ 242 } while (0) 243 244 struct rockchip_tve { 245 struct device *dev; 246 struct drm_device *drm_dev; 247 struct drm_connector connector; 248 struct drm_encoder encoder; 249 250 u32 tv_format; 251 void __iomem *regbase; 252 void __iomem *vdacbase; 253 struct clk *aclk; 254 struct clk *hclk; 255 struct clk *pclk_vdac; 256 struct clk *dclk; 257 struct clk *dclk_4x; 258 struct regmap *dac_grf; 259 u32 reg_phy_base; 260 u32 len; 261 int input_format; 262 int soc_type; 263 int upsample_mode; 264 bool enable; 265 u32 test_mode; 266 u32 saturation; 267 u32 brightcontrast; 268 u32 adjtiming; 269 u32 lumafilter0; 270 u32 lumafilter1; 271 u32 lumafilter2; 272 u32 lumafilter3; 273 u32 lumafilter4; 274 u32 lumafilter5; 275 u32 lumafilter6; 276 u32 lumafilter7; 277 u32 daclevel; 278 u32 dac1level; 279 u32 preferred_mode; 280 u8 vdac_out_current; 281 struct mutex suspend_lock; /* mutex for tve resume operation*/ 282 struct rockchip_drm_sub_dev sub_dev; 283 }; 284 285 #endif /* _ROCKCHIP_DRM_TVE_ */ 286