1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 4 * 5 * Author: Dingxian Wen <shawn.wen@rock-chips.com> 6 */ 7 8 #ifndef __RK_HDMIRX_H__ 9 #define __RK_HDMIRX_H__ 10 11 #include <linux/bitops.h> 12 13 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) 14 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16)) 15 16 // -------------------- SYS_GRF --------------------------------- 17 #define SYS_GRF_SOC_CON1 0x0304 18 #define HDMIRXPHY_SRAM_EXT_LD_DONE BIT(1) 19 #define HDMIRXPHY_SRAM_BYPASS BIT(0) 20 #define SYS_GRF_SOC_STATUS1 0x0384 21 #define HDMIRXPHY_SRAM_INIT_DONE BIT(10) 22 #define SYS_GRF_CHIP_ID 0x0600 23 24 // -------------------- VO1_GRF --------------------------------- 25 #define VO1_GRF_VO1_CON1 0x0004 26 #define HDCP1_P0_GPIO_IN_SEL BIT(8) 27 28 #define VO1_GRF_VO1_CON2 0x0008 29 #define HDCP1_GATING_EN BIT(10) 30 #define HDMIRX_SDAIN_MSK BIT(2) 31 #define HDMIRX_SCLIN_MSK BIT(1) 32 #define HDCP2_SWITCH_LCK BIT(0) 33 #define HDCP2_ESM_P0_GPIO_IN 0x0300 34 35 // -------------------- HDMIRX PHY ------------------------------- 36 #define SUP_DIG_ANA_CREGS_SUP_ANA_NC 0x004f 37 38 #define LANE0_DIG_ASIC_RX_OVRD_OUT_0 0x100f 39 #define LANE1_DIG_ASIC_RX_OVRD_OUT_0 0x110f 40 #define LANE2_DIG_ASIC_RX_OVRD_OUT_0 0x120f 41 #define LANE3_DIG_ASIC_RX_OVRD_OUT_0 0x130f 42 #define ASIC_ACK_OVRD_EN BIT(1) 43 #define ASIC_ACK BIT(0) 44 45 #define LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x104a 46 #define LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x114a 47 #define LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x124a 48 #define LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x134a 49 #define FREQ_TUNE_START_VAL_MASK GENMASK(9, 0) 50 #define FREQ_TUNE_START_VAL(x) UPDATE(x, 9, 0) 51 52 #define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_FSM_CONFIG 0x20c4 53 #define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_ADAPT_REF_FOM 0x20c7 54 #define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_3_REG 0x20e9 55 #define CDR_SETTING_BOUNDARY_3_DEFAULT 0x52da 56 #define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_4_REG 0x20ea 57 #define CDR_SETTING_BOUNDARY_4_DEFAULT 0x43cd 58 #define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_5_REG 0x20eb 59 #define CDR_SETTING_BOUNDARY_5_DEFAULT 0x35b3 60 #define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_6_REG 0x20fb 61 #define CDR_SETTING_BOUNDARY_6_DEFAULT 0x2799 62 #define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_7_REG 0x20fc 63 #define CDR_SETTING_BOUNDARY_7_DEFAULT 0x1b65 64 65 #define RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 0x300e 66 #define RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 0x310e 67 #define RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 0x320e 68 #define RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 0x330e 69 #define PCS_ACK_WRITE_SELECT BIT(14) 70 #define PCS_EN_CTL BIT(1) 71 #define PCS_ACK BIT(0) 72 73 #define RAWLANE0_DIG_AON_FAST_FLAGS 0x305c 74 #define RAWLANE1_DIG_AON_FAST_FLAGS 0x315c 75 #define RAWLANE2_DIG_AON_FAST_FLAGS 0x325c 76 #define RAWLANE3_DIG_AON_FAST_FLAGS 0x335c 77 78 // -------------------- HDMIRX Ctrler ------------------------------- 79 #define GLOBAL_SWRESET_REQUEST 0x0020 80 #define DATAPATH_SWRESETREQ BIT(12) 81 #define AUDIO_SWRESETREQ BIT(9) 82 #define GLOBAL_SWENABLE 0x0024 83 #define PHYCTRL_ENABLE BIT(21) 84 #define CEC_ENABLE BIT(16) 85 #define TMDS_ENABLE BIT(13) 86 #define DATAPATH_ENABLE BIT(12) 87 #define PKTFIFO_ENABLE BIT(11) 88 #define HDCP_ENABLE BIT(10) 89 #define AUDIO_ENABLE BIT(9) 90 #define AVPUNIT_ENABLE BIT(8) 91 #define MAIN_ENABLE BIT(0) 92 #define GLOBAL_TIMER_REF_BASE 0x0028 93 #define CORE_CONFIG 0x0050 94 #define CMU_CONFIG0 0x0060 95 #define TMDSQPCLK_STABLE_FREQ_MARGIN_MASK GENMASK(30, 16) 96 #define TMDSQPCLK_STABLE_FREQ_MARGIN(x) UPDATE(x, 30, 16) 97 #define AUDCLK_STABLE_FREQ_MARGIN_MASK GENMASK(11, 9) 98 #define AUDCLK_STABLE_FREQ_MARGIN(x) UPDATE(x, 11, 9) 99 #define CMU_STATUS 0x007c 100 #define TMDSQPCLK_LOCKED_ST BIT(4) 101 #define CMU_TMDSQPCLK_FREQ 0x0084 102 #define PHY_CONFIG 0x00c0 103 #define LDO_AFE_PROG_MASK GENMASK(24, 23) 104 #define LDO_AFE_PROG(x) UPDATE(x, 24, 23) 105 #define LDO_PWRDN BIT(21) 106 #define TMDS_CLOCK_RATIO BIT(16) 107 #define RXDATA_WIDTH BIT(15) 108 #define REFFREQ_SEL_MASK GENMASK(11, 9) 109 #define REFFREQ_SEL(x) UPDATE(x, 11, 9) 110 #define HDMI_DISABLE BIT(8) 111 #define PHY_PDDQ BIT(1) 112 #define PHY_RESET BIT(0) 113 #define PHY_STATUS 0x00c8 114 #define HDMI_DISABLE_ACK BIT(1) 115 #define PDDQ_ACK BIT(0) 116 #define PHYCREG_CONFIG0 0x00e0 117 #define PHYCREG_CR_PARA_SELECTION_MODE_MASK GENMASK(1, 0) 118 #define PHYCREG_CR_PARA_SELECTION_MODE(x) UPDATE(x, 1, 0) 119 #define PHYCREG_CONFIG1 0x00e4 120 #define PHYCREG_CONFIG2 0x00e8 121 #define PHYCREG_CONFIG3 0x00ec 122 #define PHYCREG_CONTROL 0x00f0 123 #define PHYCREG_CR_PARA_WRITE_P BIT(1) 124 #define PHYCREG_CR_PARA_READ_P BIT(0) 125 #define PHYCREG_STATUS 0x00f4 126 127 #define MAINUNIT_STATUS 0x0150 128 #define TMDSVALID_STABLE_ST BIT(1) 129 #define DESCRAND_EN_CONTROL 0x0210 130 #define SCRAMB_EN_SEL_QST_MASK GENMASK(1, 0) 131 #define SCRAMB_EN_SEL_QST(x) UPDATE(x, 1, 0) 132 #define DESCRAND_SYNC_CONTROL 0x0214 133 #define RECOVER_UNSYNC_STREAM_QST BIT(0) 134 #define DESCRAND_SYNC_SEQ_CONFIG 0x022c 135 #define DESCRAND_SYNC_SEQ_ERR_CNT_EN BIT(0) 136 #define DESCRAND_SYNC_SEQ_STATUS 0x0234 137 #define DEFRAMER_CONFIG0 0x0270 138 #define VS_CNT_THR_QST_MASK GENMASK(27, 20) 139 #define VS_CNT_THR_QST(x) UPDATE(x, 27, 20) 140 #define HS_POL_QST_MASK GENMASK(19, 18) 141 #define HS_POL_QST(x) UPDATE(x, 19, 18) 142 #define VS_POL_QST_MASK GENMASK(17, 16) 143 #define VS_POL_QST(x) UPDATE(x, 17, 16) 144 #define VS_REMAPFILTER_EN_QST BIT(8) 145 #define HS_FILTER_ORDER_QST_MASK GENMASK(3, 2) 146 #define HS_FILTER_ORDER_QST(x) UPDATE(x, 3, 2) 147 #define VS_FILTER_ORDER_QST_MASK GENMASK(1, 0) 148 #define VS_FILTER_ORDER_QST(x) UPDATE(x, 1, 0) 149 #define DEFRAMER_VSYNC_CNT_CLEAR 0x0278 150 #define VSYNC_CNT_CLR_P BIT(0) 151 #define DEFRAMER_STATUS 0x027c 152 #define OPMODE_STS_MASK GENMASK(6, 4) 153 #define I2C_SLAVE_CONFIG1 0x0164 154 #define I2C_SDA_OUT_HOLD_VALUE_QST_MASK GENMASK(15, 8) 155 #define I2C_SDA_OUT_HOLD_VALUE_QST(x) UPDATE(x, 15, 8) 156 #define I2C_SDA_IN_HOLD_VALUE_QST_MASK GENMASK(7, 0) 157 #define I2C_SDA_IN_HOLD_VALUE_QST(x) UPDATE(x, 7, 0) 158 #define OPMODE_STS_MASK GENMASK(6, 4) 159 #define HDCP14_CONFIG 0x0290 160 #define REPEATER_QST BIT(28) 161 #define FASTREAUTH_QST BIT(27) 162 #define FEATURES_1DOT1_QST BIT(26) 163 #define FASTI2C_QST BIT(25) 164 #define EESS_CTL_THR_QST_MASK GENMASK(19, 16) 165 #define EESS_CTL_THR_QST(x) UPDATE(x, 19, 16) 166 #define OESS_CTL3_THR_QST_MASK GENMASK(11, 8) 167 #define OESS_CTL3_THR_QST(x) UPDATE(x, 11, 8) 168 #define EESS_OESS_SEL_QST_MASK GENMASK(5, 4) 169 #define EESS_OESS_SEL_QST(x) UPDATE(x, 5, 4) 170 #define KEY_DECRYPT_EN_QST BIT(0) 171 #define HDCP14_KEY_SEED 0x02a0 172 #define KEY_DECRYPT_SEED_QST_MASK GENMASK(15, 0) 173 #define KEY_DECRYPT_SEED_QST(x) UPDATE(x, 15, 0) 174 #define HDCP14_STATUS 0x2b8 175 #define HDCP2_CONFIG 0x02f0 176 #define HDCP2_CONNECTED BIT(12) 177 #define HDCP2_SWITCH_OVR_VALUE BIT(2) 178 #define HDCP2_SWITCH_OVR_EN BIT(1) 179 #define HDCP2_STATUS 0x02f4 180 #define HDCP2_ESM_P0_GPIO_OUT 0x0304 181 182 #define VIDEO_CONFIG2 0x042c 183 #define VPROC_VSYNC_POL_OVR_VALUE BIT(19) 184 #define VPROC_VSYNC_POL_OVR_EN BIT(18) 185 #define VPROC_HSYNC_POL_OVR_VALUE BIT(17) 186 #define VPROC_HSYNC_POL_OVR_EN BIT(16) 187 #define VPROC_FMT_OVR_VALUE_MASK GENMASK(6, 4) 188 #define VPROC_FMT_OVR_VALUE(x) UPDATE(x, 6, 4) 189 #define VPROC_FMT_OVR_EN BIT(0) 190 191 #define VIDEO_MUTE_VALUE_H 0x0430 192 #define VIDEO_MUTE_VALUE_L 0x0434 193 #define AUDIO_FIFO_CONFIG 0x0460 194 #define AFIFO_FILL_RESTART BIT(0) 195 #define AUDIO_FIFO_CONTROL 0x0464 196 #define AFIFO_INIT_P BIT(0) 197 #define AUDIO_FIFO_THR_PASS 0x0468 198 #define AUDIO_FIFO_THR 0x046c 199 #define AFIFO_THR_LOW_QST_MASK GENMASK(25, 16) 200 #define AFIFO_THR_LOW_QST(x) UPDATE(x, 25, 16) 201 #define AFIFO_THR_HIGH_QST_MASK GENMASK(9, 0) 202 #define AFIFO_THR_HIGH_QST(x) UPDATE(x, 9, 0) 203 #define AUDIO_FIFO_MUTE_THR 0x0470 204 #define AFIFO_THR_MUTE_LOW_QST_MASK GENMASK(25, 16) 205 #define AFIFO_THR_MUTE_LOW_QST(x) UPDATE(x, 25, 16) 206 #define AFIFO_THR_MUTE_HIGH_QST_MASK GENMASK(9, 0) 207 #define AFIFO_THR_MUTE_HIGH_QST(x) UPDATE(x, 9, 0) 208 209 #define AUDIO_FIFO_STATUS2 0x0478 210 #define AFIFO_UNDERFLOW_ST BIT(25) 211 #define AFIFO_OVERFLOW_ST BIT(24) 212 213 #define AUDIO_PROC_CONFIG0 0x0480 214 #define SPEAKER_ALLOC_OVR_EN BIT(16) 215 #define AUD_MUTE_OVR_VALUE BIT(13) 216 #define AUD_MUTE_OVR_EN BIT(12) 217 #define I2S_BPCUV_EN BIT(4) 218 #define SPDIF_EN BIT(2) 219 #define I2S_EN BIT(1) 220 #define AUDIO_PROC_CONFIG1 0x0484 221 #define AUDIO_PROC_CONFIG2 0x0488 222 #define AFIFO_THR_PASS_DEMUTEMASK_N BIT(24) 223 #define AVMUTE_DEMUTEMASK_N BIT(16) 224 #define AFIFO_THR_MUTE_LOW_MUTEMASK_N BIT(9) 225 #define AFIFO_THR_MUTE_HIGH_MUTEMASK_N BIT(8) 226 #define AUD_FMT_CHG_MUTEMASK_N BIT(1) 227 #define AVMUTE_MUTEMASK_N BIT(0) 228 #define AUDIO_PROC_CONFIG3 0x048c 229 #define AUDIO_PROC_STATUS1 0x0490 230 #define AUD_SAMPLE_PRESENT GENMASK(20, 17) 231 #define SCDC_CONFIG 0x0580 232 #define HPDLOW BIT(1) 233 #define POWERPROVIDED BIT(0) 234 #define SCDC_REGBANK_STATUS1 0x058c 235 #define SCDC_TMDSBITCLKRATIO BIT(1) 236 #define SCDC_REGBANK_STATUS3 0x0594 237 #define SCDC_REGBANK_CONFIG0 0x05c0 238 #define SCDC_SINKVERSION_QST_MASK GENMASK(7, 0) 239 #define SCDC_SINKVERSION_QST(x) UPDATE(x, 7, 0) 240 #define AUDIO_GEN_CONFIG0 0x0740 241 #define AGEN_LAYOUT BIT(4) 242 #define AGEN_SPEAKER_ALLOC GENMASK(15, 8) 243 244 #define CED_CONFIG 0x0760 245 #define CED_VIDDATACHECKEN_QST BIT(27) 246 #define CED_DATAISCHECKEN_QST BIT(26) 247 #define CED_GBCHECKEN_QST BIT(25) 248 #define CED_CTRLCHECKEN_QST BIT(24) 249 #define CED_CHLOCKMAXER_QST_MASK GENMASK(14, 0) 250 #define CED_CHLOCKMAXER_QST(x) UPDATE(x, 14, 0) 251 #define CED_DYN_CONFIG 0x0768 252 #define CED_DYN_CONTROL 0x076c 253 #define PKTEX_BCH_ERRFILT_CONFIG 0x07c4 254 #define PKTEX_CHKSUM_ERRFILT_CONFIG 0x07c8 255 256 #define PKTDEC_ACR_PH2_1 0x1100 257 #define PKTDEC_ACR_PB3_0 0x1104 258 #define PKTDEC_ACR_PB7_4 0x1108 259 #define PKTDEC_AVIIF_PH2_1 0x1200 260 #define PKTDEC_AVIIF_PB3_0 0x1204 261 #define RGB_QUANTIZATION_RANGE GENMASK(27, 26) 262 #define EXTEND_COLORIMETRY GENMASK(30, 28) 263 #define PKTDEC_AVIIF_PB7_4 0x1208 264 #define VIC_VAL_MASK GENMASK(6, 0) 265 #define PKTDEC_AVIIF_PB11_8 0x120c 266 #define PKTDEC_AVIIF_PB15_12 0x1210 267 #define PKTDEC_AVIIF_PB19_16 0x1214 268 #define PKTDEC_AVIIF_PB23_20 0x1218 269 #define PKTDEC_AVIIF_PB27_24 0x121c 270 #define PKTDEC_AUDIF_PH2_1 0x1240 271 #define PKTDEC_AUDIF_PB3_0 0x1244 272 #define PKTDEC_AUDIF_PB7_4 0x1248 273 #define PKTDEC_AUDIF_PB11_8 0x124c 274 #define PKTDEC_AUDIF_PB15_12 0x1250 275 #define PKTDEC_AUDIF_PB19_16 0x1254 276 #define PKTDEC_AUDIF_PB23_20 0x1258 277 #define PKTDEC_AUDIF_PB27_24 0x125c 278 279 #define PKTFIFO_CONFIG 0x1500 280 #define PKTFIFO_STORE_FILT_CONFIG 0x1504 281 #define PKTFIFO_THR_CONFIG0 0x1508 282 #define PKTFIFO_THR_CONFIG1 0x150c 283 #define PKTFIFO_CONTROL 0x1510 284 285 #define VMON_CONTROL 0x1560 286 #define VMON_SOURCE_SEL_MASK GENMASK(30, 28) 287 #define VMON_SOURCE_SEL_DEFRAMER(x) UPDATE(x, 30, 28) 288 #define VMON_IRQ_THR_MASK BIT(24) 289 #define VMON_CONTROL2 0x1564 290 #define VMON_IRQ_VERTICAL_MASK GENMASK(12, 8) 291 #define VMON_IRQ_VERTICAL_SEL(x) UPDATE(x, 12, 8) 292 #define VMON_IRQ_HORIZONAL_MASK GENMASK(4, 0) 293 #define VMON_IRQ_HORIZONAL_SEL(x) UPDATE(x, 4, 0) 294 #define VMON_STATUS1 0x1580 295 #define VMON_STATUS2 0x1584 296 #define VMON_STATUS3 0x1588 297 #define VMON_STATUS4 0x158c 298 #define VMON_STATUS5 0x1590 299 #define VMON_STATUS6 0x1594 300 #define VMON_STATUS7 0x1598 301 #define VMON_ILACE_DETECT BIT(4) 302 303 #define CEC_TX_CONTROL 0x2000 304 #define CEC_STATUS 0x2004 305 #define CEC_CONFIG 0x2008 306 #define RX_AUTO_DRIVE_ACKNOWLEDGE BIT(9) 307 #define CEC_ADDR 0x200c 308 #define CEC_TX_COUNT 0x2020 309 #define CEC_TX_DATA3_0 0x2024 310 #define CEC_RX_COUNT_STATUS 0x2040 311 #define CEC_RX_DATA3_0 0x2044 312 #define CEC_LOCK_CONTROL 0x2054 313 #define CEC_RXQUAL_BITTIME_CONFIG 0x2060 314 #define CEC_RX_BITTIME_CONFIG 0x2064 315 #define CEC_TX_BITTIME_CONFIG 0x2068 316 317 #define DMA_CONFIG1 0x4400 318 #define UV_WID_MASK GENMASK(31, 28) 319 #define UV_WID(x) UPDATE(x, 31, 28) 320 #define Y_WID_MASK GENMASK(27, 24) 321 #define Y_WID(x) UPDATE(x, 27, 24) 322 #define DDR_STORE_FORMAT_MASK GENMASK(15, 12) 323 #define DDR_STORE_FORMAT(x) UPDATE(x, 15, 12) 324 #define ABANDON_EN BIT(0) 325 #define DMA_CONFIG2 0x4404 326 #define DMA_CONFIG3 0x4408 327 #define DMA_CONFIG4 0x440c // dma irq en 328 #define DMA_CONFIG5 0x4410 // dma irq clear status 329 #define LINE_FLAG_INT_EN BIT(8) 330 #define HDMIRX_DMA_IDLE_INT BIT(7) 331 #define HDMIRX_LOCK_DISABLE_INT BIT(6) 332 #define LAST_FRAME_AXI_UNFINISH_INT_EN BIT(5) 333 #define FIFO_OVERFLOW_INT_EN BIT(2) 334 #define FIFO_UNDERFLOW_INT_EN BIT(1) 335 #define HDMIRX_AXI_ERROR_INT_EN BIT(0) 336 #define DMA_CONFIG6 0x4414 337 #define RB_SWAP_EN BIT(9) 338 #define HSYNC_TOGGLE_EN BIT(5) 339 #define VSYNC_TOGGLE_EN BIT(4) 340 #define HDMIRX_DMA_EN BIT(1) 341 #define DMA_CONFIG7 0x4418 342 #define LINE_FLAG_NUM_MASK GENMASK(31, 16) 343 #define LINE_FLAG_NUM(x) UPDATE(x, 31, 16) 344 #define LOCK_FRAME_NUM_MASK GENMASK(11, 0) 345 #define LOCK_FRAME_NUM(x) UPDATE(x, 11, 0) 346 #define DMA_CONFIG8 0x441c 347 #define REG_MIRROR_EN BIT(0) 348 #define DMA_CONFIG9 0x4420 349 #define DMA_CONFIG10 0x4424 350 #define DMA_CONFIG11 0x4428 351 #define EDID_READ_EN_MASK BIT(8) 352 #define EDID_READ_EN(x) UPDATE(x, 8, 8) 353 #define EDID_WRITE_EN_MASK BIT(7) 354 #define EDID_WRITE_EN(x) UPDATE(x, 7, 7) 355 #define EDID_SLAVE_ADDR_MASK GENMASK(6, 0) 356 #define EDID_SLAVE_ADDR(x) UPDATE(x, 6, 0) 357 #define DMA_STATUS1 0x4430 // dma irq status 358 #define DMA_STATUS2 0x4434 359 #define DMA_STATUS3 0x4438 360 #define DMA_STATUS4 0x443c 361 #define DMA_STATUS5 0x4440 362 #define DMA_STATUS6 0x4444 363 #define DMA_STATUS7 0x4448 364 #define DMA_STATUS8 0x444c 365 #define DMA_STATUS9 0x4450 366 #define DMA_STATUS10 0x4454 367 #define HDMIRX_LOCK BIT(3) 368 #define DMA_STATUS11 0x4458 369 #define HDMIRX_TYPE_MASK GENMASK(8, 7) 370 #define HDMIRX_COLOR_DEPTH_MASK GENMASK(6, 3) 371 #define HDMIRX_FORMAT_MASK GENMASK(2, 0) 372 #define DMA_STATUS12 0x445c 373 #define DMA_STATUS13 0x4460 374 #define DMA_STATUS14 0x4464 375 376 #define MAINUNIT_INTVEC_INDEX 0x5000 377 #define MAINUNIT_0_INT_STATUS 0x5010 378 #define CECRX_NOTIFY_ERR BIT(12) 379 #define CECRX_EOM BIT(11) 380 #define CECTX_DRIVE_ERR BIT(10) 381 #define CECRX_BUSY BIT(9) 382 #define CECTX_BUSY BIT(8) 383 #define CECTX_FRAME_DISCARDED BIT(5) 384 #define CECTX_NRETRANSMIT_FAIL BIT(4) 385 #define CECTX_LINE_ERR BIT(3) 386 #define CECTX_ARBLOST BIT(2) 387 #define CECTX_NACK BIT(1) 388 #define CECTX_DONE BIT(0) 389 #define MAINUNIT_0_INT_MASK_N 0x5014 390 #define MAINUNIT_0_INT_CLEAR 0x5018 391 #define MAINUNIT_0_INT_FORCE 0x501c 392 #define TIMER_BASE_LOCKED_IRQ BIT(26) 393 #define TMDSQPCLK_OFF_CHG BIT(5) 394 #define TMDSQPCLK_LOCKED_CHG BIT(4) 395 #define MAINUNIT_1_INT_STATUS 0x5020 396 #define MAINUNIT_1_INT_MASK_N 0x5024 397 #define MAINUNIT_1_INT_CLEAR 0x5028 398 #define MAINUNIT_1_INT_FORCE 0x502c 399 #define MAINUNIT_2_INT_STATUS 0x5030 400 #define MAINUNIT_2_INT_MASK_N 0x5034 401 #define MAINUNIT_2_INT_CLEAR 0x5038 402 #define MAINUNIT_2_INT_FORCE 0x503c 403 #define PHYCREG_CR_READ_DONE BIT(11) 404 #define PHYCREG_CR_WRITE_DONE BIT(10) 405 #define TMDSVALID_STABLE_CHG BIT(1) 406 407 #define AVPUNIT_0_INT_STATUS 0x5040 408 #define AVPUNIT_0_INT_MASK_N 0x5044 409 #define AVPUNIT_0_INT_CLEAR 0x5048 410 #define AVPUNIT_0_INT_FORCE 0x504c 411 #define CED_DYN_CNT_CH2_IRQ BIT(22) 412 #define CED_DYN_CNT_CH1_IRQ BIT(21) 413 #define CED_DYN_CNT_CH0_IRQ BIT(20) 414 #define AVPUNIT_1_INT_STATUS 0x5050 415 #define VMON_VMEAS_IRQ BIT(31) 416 #define VMON_HMEAS_IRQ BIT(30) 417 #define DEFRAMER_VSYNC_THR_REACHED_IRQ BIT(1) 418 #define AVPUNIT_1_INT_MASK_N 0x5054 419 #define DEFRAMER_VSYNC_THR_REACHED_MASK_N BIT(1) 420 #define DEFRAMER_VSYNC_MASK_N BIT(0) 421 #define AVPUNIT_1_INT_CLEAR 0x5058 422 #define DEFRAMER_VSYNC_THR_REACHED_CLEAR BIT(1) 423 #define AVPUNIT_1_INT_FORCE 0x505C 424 #define PKT_0_INT_STATUS 0x5080 425 #define PKTDEC_AUDIF_CHG_IRQ BIT(13) 426 #define PKTDEC_AVIIF_CHG_IRQ BIT(11) 427 #define PKTDEV_VSIF_CHG_IRQ BIT(10) 428 #define PKTDEC_ACR_CHG_IRQ BIT(3) 429 #define PKT_0_INT_MASK_N 0x5084 430 #define PKTDEC_AVIIF_CHG_MASK_N BIT(11) 431 #define PKTDEV_VSIF_CHG_MASK_N BIT(10) 432 #define PKTDEC_ACR_CHG_MASK_N BIT(3) 433 #define PKT_0_INT_CLEAR 0x5088 434 #define PKT_0_INT_FORCE 0x508c 435 #define PKT_1_INT_STATUS 0x5090 436 #define PKT_1_INT_MASK_N 0x5094 437 #define PKT_1_INT_CLEAR 0x5098 438 #define PKT_2_INT_STATUS 0x50a0 439 #define PKTDEC_AUDIF_RCV_IRQ BIT(13) 440 #define PKTDEC_ACR_RCV_IRQ BIT(3) 441 #define PKT_2_INT_MASK_N 0x50a4 442 #define PKTDEC_AUDIF_RCV_MASK_N BIT(13) 443 #define PKTDEC_AVIIF_RCV_IRQ BIT(11) 444 #define PKTDEC_ACR_RCV_MASK_N BIT(3) 445 #define PKT_2_INT_CLEAR 0x50a8 446 #define PKTDEC_AUDIF_RCV_CLEAR BIT(13) 447 #define PKTDEC_AVIIF_RCV_CLEAR BIT(11) 448 #define PKTDEC_ACR_RCV_CLEAR BIT(3) 449 #define SCDC_INT_STATUS 0x50c0 450 #define SCDC_INT_MASK_N 0x50c4 451 #define SCDC_INT_CLEAR 0x50c8 452 #define SCDCTMDSCCFG_CHG BIT(2) 453 454 #define HDCP_INT_STATUS 0x50d0 455 #define HDCP_INT_MASK_N 0x50d4 456 #define HDCP_INT_CLEAR 0x50d8 457 #define HDCP_1_INT_STATUS 0x50e0 458 #define HDCP_1_INT_MASK_N 0x50e4 459 #define HDCP_1_INT_CLEAR 0x50e8 460 #define CEC_INT_STATUS 0x5100 461 #define CEC_INT_MASK_N 0x5104 462 #define CEC_INT_CLEAR 0x5108 463 464 #endif 465