1 /* GPL-2.0 WITH Linux-syscall-note OR Apache 2.0 */ 2 /* Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd */ 3 4 #ifndef INCLUDE_RT_MPI_RK_COMMON_VO_H_ 5 #define INCLUDE_RT_MPI_RK_COMMON_VO_H_ 6 7 #include "rk_type.h" 8 #include "rk_common.h" 9 #include "rk_comm_video.h" 10 11 #define VO_DEF_WBC_DEPTH_LEN 8 12 13 #ifdef __cplusplus 14 #if __cplusplus 15 extern "C" { 16 #endif 17 #endif /* End of #ifdef __cplusplus */ 18 19 typedef enum rkEN_VOU_ERR_CODE_E { 20 EN_ERR_VO_DEV_NOT_CONFIG = 0x40, 21 EN_ERR_VO_DEV_NOT_ENABLE = 0x41, 22 EN_ERR_VO_DEV_HAS_ENABLED = 0x42, 23 EN_ERR_VO_DEV_HAS_BINDED = 0x43, 24 EN_ERR_VO_DEV_NOT_BINDED = 0x44, 25 26 ERR_VO_NOT_ENABLE = 0x45, 27 ERR_VO_NOT_DISABLE = 0x46, 28 ERR_VO_NOT_CONFIG = 0x47, 29 30 ERR_VO_CHN_NOT_DISABLE = 0x48, 31 ERR_VO_CHN_NOT_ENABLE = 0x49, 32 ERR_VO_CHN_NOT_CONFIG = 0x4a, 33 ERR_VO_CHN_NOT_ALLOC = 0x4b, 34 35 ERR_VO_CCD_INVALID_PAT = 0x4c, 36 ERR_VO_CCD_INVALID_POS = 0x4d, 37 38 ERR_VO_WAIT_TIMEOUT = 0x4e, 39 ERR_VO_INVALID_VFRAME = 0x4f, 40 ERR_VO_INVALID_RECT_PARA = 0x50, 41 ERR_VO_SETBEGIN_ALREADY = 0x51, 42 ERR_VO_SETBEGIN_NOTYET = 0x52, 43 ERR_VO_SETEND_ALREADY = 0x53, 44 ERR_VO_SETEND_NOTYET = 0x54, 45 46 ERR_VO_WBC_NOT_DISABLE = 0x55, 47 ERR_VO_WBC_NOT_CONFIG = 0x56, 48 49 ERR_VO_CHN_AREA_OVERLAP = 0x57, 50 51 EN_ERR_INVALID_WBCID = 0x58, 52 EN_ERR_INVALID_LAYERID = 0x59, 53 EN_ERR_VO_LAYER_HAS_BINDED = 0x5a, 54 EN_ERR_VO_LAYER_NOT_BINDED = 0x5b, 55 ERR_VO_WBC_HAS_BIND = 0x5c, 56 ERR_VO_WBC_HAS_CONFIG = 0x5d, 57 ERR_VO_WBC_NOT_BIND = 0x5e, 58 59 /* new added */ 60 ERR_VO_BUTT 61 } EN_VOU_ERR_CODE_E; 62 63 /* System define error code */ 64 #define RK_ERR_VO_BUSY RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, RK_ERR_BUSY) 65 #define RK_ERR_VO_NO_MEM RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, RK_ERR_NOMEM) 66 #define RK_ERR_VO_NULL_PTR RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, RK_ERR_NULL_PTR) 67 #define RK_ERR_VO_SYS_NOTREADY RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, RK_ERR_NOTREADY) 68 #define RK_ERR_VO_INVALID_DEVID RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, RK_ERR_INVALID_DEVID) 69 #define RK_ERR_VO_INVALID_CHNID RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, RK_ERR_INVALID_CHNID) 70 #define RK_ERR_VO_ILLEGAL_PARAM RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, RK_ERR_ILLEGAL_PARAM) 71 #define RK_ERR_VO_NOT_SUPPORT RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, RK_ERR_NOT_SUPPORT) 72 #define RK_ERR_VO_NOT_PERMIT RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, RK_ERR_NOT_PERM) 73 #define RK_ERR_VO_INVALID_WBCID RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, EN_ERR_INVALID_WBCID) 74 #define RK_ERR_VO_INVALID_LAYERID RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, EN_ERR_INVALID_LAYERID) 75 76 /* Device relative error code */ 77 #define RK_ERR_VO_DEV_NOT_CONFIG RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_NOT_CONFIG) 78 #define RK_ERR_VO_DEV_NOT_ENABLE RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_NOT_ENABLE) 79 #define RK_ERR_VO_DEV_HAS_ENABLED RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_HAS_ENABLED) 80 #define RK_ERR_VO_DEV_HAS_BINDED RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_HAS_BINDED) 81 #define RK_ERR_VO_DEV_NOT_BINDED RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_NOT_BINDED) 82 83 /* layer relative error code */ 84 #define RK_ERR_VO_LAYER_NOT_ENABLE RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_NOT_ENABLE) 85 #define RK_ERR_VO_LAYER_NOT_DISABLE RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_NOT_DISABLE) 86 #define RK_ERR_VO_LAYER_NOT_CONFIG RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_NOT_CONFIG) 87 #define RK_ERR_VO_LAYER_HAS_BINDED RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, EN_ERR_VO_LAYER_HAS_BINDED) 88 #define RK_ERR_VO_LAYER_NOT_BINDED RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, EN_ERR_VO_LAYER_NOT_BINDED) 89 90 /* WBC Relative error code */ 91 92 #define RK_ERR_VO_WBC_NOT_DISABLE RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_WBC_NOT_DISABLE) 93 #define RK_ERR_VO_WBC_NOT_CONFIG RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_WBC_NOT_CONFIG) 94 #define RK_ERR_VO_WBC_HAS_CONFIG RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_WBC_HAS_CONFIG) 95 #define RK_ERR_VO_WBC_NOT_BIND RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_WBC_NOT_BIND) 96 #define RK_ERR_VO_WBC_HAS_BIND RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_WBC_HAS_BIND) 97 98 /* Channel Relative error code */ 99 #define RK_ERR_VO_CHN_NOT_DISABLE RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_CHN_NOT_DISABLE) 100 #define RK_ERR_VO_CHN_NOT_ENABLE RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_CHN_NOT_ENABLE) 101 #define RK_ERR_VO_CHN_NOT_CONFIG RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_CHN_NOT_CONFIG) 102 #define RK_ERR_VO_CHN_NOT_ALLOC RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_CHN_NOT_ALLOC) 103 #define RK_ERR_VO_CHN_AREA_OVERLAP RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_CHN_AREA_OVERLAP) 104 105 /* Cascade Relatvie error code */ 106 #define RK_ERR_VO_INVALID_PATTERN RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_CCD_INVALID_PAT) 107 #define RK_ERR_VO_INVALID_POSITION RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_CCD_INVALID_POS) 108 109 /* MISCellaneous error code */ 110 #define RK_ERR_VO_WAIT_TIMEOUT RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_WAIT_TIMEOUT) 111 #define RK_ERR_VO_INVALID_VFRAME RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_INVALID_VFRAME) 112 #define RK_ERR_VO_INVALID_RECT_PARA RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_INVALID_RECT_PARA) 113 #define RK_ERR_VO_SETBEGIN_ALREADY RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_SETBEGIN_ALREADY) 114 #define RK_ERR_VO_SETBEGIN_NOTYET RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_SETBEGIN_NOTYET) 115 #define RK_ERR_VO_SETEND_ALREADY RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_SETEND_ALREADY) 116 #define RK_ERR_VO_SETEND_NOTYET RK_DEF_ERR(RK_ID_VO, RK_ERR_LEVEL_ERROR, ERR_VO_SETEND_NOTYET) 117 118 /* VO video output interface type */ 119 #define VO_INTF_CVBS (0x01L << 0) 120 #define VO_INTF_YPBPR (0x01L << 1) 121 #define VO_INTF_VGA (0x01L << 2) 122 #define VO_INTF_BT656 (0x01L << 3) 123 #define VO_INTF_BT1120 (0x01L << 4) 124 #define VO_INTF_LCD (0x01L << 6) 125 #define VO_INTF_LVDS (0x01L << 7) 126 #define VO_INTF_MIPI (0x01L << 9) 127 #define VO_INTF_MIPI1 (0x01L << 10) 128 #define VO_INTF_EDP (0x01L << 11) 129 #define VO_INTF_EDP1 (0x01L << 12) 130 #define VO_INTF_HDMI (0x01L << 13) 131 #define VO_INTF_HDMI1 (0x01L << 14) 132 #define VO_INTF_DP (0x01L << 15) 133 #define VO_INTF_DP1 (0x01L << 16) 134 #define VO_INTF_DEFAULT (0x01L << 17) 135 136 #define VO_INTF_NUM 17 137 138 typedef RK_U32 VO_INTF_TYPE_E; 139 140 typedef enum rkVO_INTF_SYNC_E { 141 VO_OUTPUT_PAL = 0, /* PAL standard */ 142 VO_OUTPUT_NTSC, /* NTSC standard */ 143 144 VO_OUTPUT_1080P24, /* 1920 x 1080 at 24 Hz. */ 145 VO_OUTPUT_1080P25, /* 1920 x 1080 at 25 Hz. */ 146 VO_OUTPUT_1080P30, /* 1920 x 1080 at 30 Hz. */ 147 148 VO_OUTPUT_720P50, /* 1280 x 720 at 50 Hz. */ 149 VO_OUTPUT_720P60, /* 1280 x 720 at 60 Hz. */ 150 151 VO_OUTPUT_1080I50, /* 1920 x 1080 at 50 Hz, interlace. */ 152 VO_OUTPUT_1080I60, /* 1920 x 1080 at 60 Hz, interlace. */ 153 VO_OUTPUT_1080P50, /* 1920 x 1080 at 50 Hz. */ 154 VO_OUTPUT_1080P60, /* 1920 x 1080 at 60 Hz. */ 155 156 VO_OUTPUT_576P50, /* 720 x 576 at 50 Hz. */ 157 VO_OUTPUT_480P60, /* 720 x 480 at 60 Hz. */ 158 VO_OUTPUT_1280P60, /* 720 x 1280 at 60 Hz. */ 159 160 VO_OUTPUT_800x600_60, /* VESA 800 x 600 at 60 Hz (non-interlaced) */ 161 VO_OUTPUT_1024x768_60, /* VESA 1024 x 768 at 60 Hz (non-interlaced) */ 162 VO_OUTPUT_1280x1024_60, /* VESA 1280 x 1024 at 60 Hz (non-interlaced) */ 163 VO_OUTPUT_1366x768_60, /* VESA 1366 x 768 at 60 Hz (non-interlaced) */ 164 VO_OUTPUT_1440x900_60, /* VESA 1440 x 900 at 60 Hz (non-interlaced) CVT Compliant */ 165 VO_OUTPUT_1280x800_60, /* 1280*800@60Hz VGA@60Hz */ 166 VO_OUTPUT_1600x1200_60, /* VESA 1600 x 1200 at 60 Hz (non-interlaced) */ 167 VO_OUTPUT_1680x1050_60, /* VESA 1680 x 1050 at 60 Hz (non-interlaced) */ 168 VO_OUTPUT_1920x1200_60, /* VESA 1920 x 1600 at 60 Hz (non-interlaced) CVT (Reduced Blanking) */ 169 VO_OUTPUT_640x480_60, /* VESA 640 x 480 at 60 Hz (non-interlaced) CVT */ 170 VO_OUTPUT_960H_PAL, /* ITU-R BT.1302 960 x 576 at 50 Hz (interlaced) */ 171 VO_OUTPUT_960H_NTSC, /* ITU-R BT.1302 960 x 480 at 60 Hz (interlaced) */ 172 VO_OUTPUT_1920x2160_30, /* 1920x2160_30 */ 173 VO_OUTPUT_2560x1440_30, /* 2560x1440_30 */ 174 VO_OUTPUT_2560x1440_60, /* 2560x1440_60 */ 175 VO_OUTPUT_2560x1600_60, /* 2560x1600_60 */ 176 VO_OUTPUT_3840x2160_24, /* 3840x2160_24 */ 177 VO_OUTPUT_3840x2160_25, /* 3840x2160_25 */ 178 VO_OUTPUT_3840x2160_30, /* 3840x2160_30 */ 179 VO_OUTPUT_3840x2160_50, /* 3840x2160_50 */ 180 VO_OUTPUT_3840x2160_60, /* 3840x2160_60 */ 181 VO_OUTPUT_4096x2160_24, /* 4096x2160_24 */ 182 VO_OUTPUT_4096x2160_25, /* 4096x2160_25 */ 183 VO_OUTPUT_4096x2160_30, /* 4096x2160_30 */ 184 VO_OUTPUT_4096x2160_50, /* 4096x2160_50 */ 185 VO_OUTPUT_4096x2160_60, /* 4096x2160_60 */ 186 /* For HDMI2.1 */ 187 VO_OUTPUT_7680x4320_24, /* 7680x4320_24 */ 188 VO_OUTPUT_7680x4320_25, /* 7680x4320_25 */ 189 VO_OUTPUT_7680x4320_30, /* 7680x4320_30 */ 190 VO_OUTPUT_7680x4320_50, /* 7680x4320_50 */ 191 VO_OUTPUT_7680x4320_60, /* 7680x4320_60 */ 192 193 VO_OUTPUT_3840x1080_60, /* For split mode */ 194 VO_OUTPUT_1080P120, /* 1920x1080_120 */ 195 196 VO_OUTPUT_USER, /* User timing. */ 197 VO_OUTPUT_DEFAULT, 198 199 VO_OUTPUT_BUTT 200 } VO_INTF_SYNC_E; 201 202 typedef enum rkVO_ZOOM_IN_E { 203 VO_ZOOM_IN_RECT = 0, /* Zoom in by rect */ 204 VO_ZOOM_IN_RATIO, /* Zoom in by ratio */ 205 VO_ZOOM_IN_BUTT 206 } VO_ZOOM_IN_E; 207 208 typedef enum rkVO_CSC_MATRIX_E { 209 VO_CSC_MATRIX_IDENTITY = 0, /* Identity CSC matrix. */ 210 211 VO_CSC_MATRIX_BT601_TO_BT709, /* BT601 to BT709 */ 212 VO_CSC_MATRIX_BT709_TO_BT601, /* BT709 to BT601 */ 213 214 VO_CSC_MATRIX_BT601_TO_RGB_PC, /* BT601 to RGB */ 215 VO_CSC_MATRIX_BT709_TO_RGB_PC, /* BT709 to RGB */ 216 217 VO_CSC_MATRIX_RGB_TO_BT601_PC, /* RGB to BT601 FULL */ 218 VO_CSC_MATRIX_RGB_TO_BT709_PC, /* RGB to BT709 FULL */ 219 220 VO_CSC_MATRIX_RGB_TO_BT2020_PC, /* RGB to BT.2020 */ 221 VO_CSC_MATRIX_BT2020_TO_RGB_PC, /* BT.2020 to RGB */ 222 223 VO_CSC_MATRIX_RGB_TO_BT601_TV, /* RGB to BT601 LIMIT */ 224 VO_CSC_MATRIX_RGB_TO_BT709_TV, /* RGB to BT709 LIMIT */ 225 226 VO_CSC_MATRIX_BUTT 227 } VO_CSC_MATRIX_E; 228 229 typedef struct rkVO_CHN_ATTR_S { 230 RK_U32 u32Priority; /* Video out overlay pri sd */ 231 RECT_S stRect; /* Rectangle of video output channel */ 232 RK_BOOL bDeflicker; /* Deflicker or not sd */ 233 RK_U32 u32FgAlpha; /* Alpha of A = 1 in pixel format BGRA5551/RGBA5551 */ 234 RK_U32 u32BgAlpha; /* Alpha of A = 0 in pixel format BGRA5551/RGBA5551 */ 235 RK_BOOL bEnKeyColor;/* Enable key color or not when pixel format BGRA5551/RGBA5551 */ 236 RK_U32 u32KeyColor; /* Key color value of pixel format BGRA5551/RGBA5551, B[0:4] G[5:9] R[10:14] */ 237 MIRROR_E enMirror; /* RW, Mirror */ 238 ROTATION_E enRotation; /* RW, rotation. */ 239 RK_U32 u32MaxChnQueue; /* vo channel max queue length */ 240 } VO_CHN_ATTR_S; 241 242 typedef struct rkVO_CHN_PARAM_S { 243 ASPECT_RATIO_S stAspectRatio; /* RW; aspect ratio */ 244 } VO_CHN_PARAM_S; 245 246 typedef struct rkVO_BORDER_S { 247 RK_BOOL bBorderEn; /* RW; Do frame or not */ 248 BORDER_S stBorder; /* RW; frame's top, bottom, left, right width and color */ 249 } VO_BORDER_S; 250 251 typedef struct rkVO_QUERY_STATUS_S { 252 RK_U32 u32ChnBufUsed; /* Channel buffer that been occupied */ 253 } VO_QUERY_STATUS_S; 254 255 typedef struct rkVO_SYNC_INFO_S { 256 RK_BOOL bSynm; /* RW; sync mode(0:timing,as BT.656; 1:signal,as LCD) */ 257 RK_BOOL bIop; /* RW; interlaced or progressive display(0:i; 1:p) */ 258 259 RK_U16 u16Vact; /* RW; vertical active area */ 260 RK_U16 u16Vbb; /* RW; vertical back blank porch */ 261 RK_U16 u16Vfb; /* RW; vertical front blank porch */ 262 263 RK_U16 u16Hact; /* RW; horizontal active area */ 264 RK_U16 u16Hbb; /* RW; horizontal back blank porch */ 265 RK_U16 u16Hfb; /* RW; horizontal front blank porch */ 266 RK_U16 u16Hmid; /* RW; bottom horizontal active area */ 267 268 RK_U16 u16Bvact; /* RW; bottom vertical active area */ 269 RK_U16 u16Bvbb; /* RW; bottom vertical back blank porch */ 270 RK_U16 u16Bvfb; /* RW; bottom vertical front blank porch */ 271 272 RK_U16 u16Hpw; /* RW; horizontal pulse width */ 273 RK_U16 u16Vpw; /* RW; vertical pulse width */ 274 275 RK_BOOL bIdv; /* RW; inverse data valid of output */ 276 RK_BOOL bIhs; /* RW; polarity of horizontal synch signal, 0: negative, 1: positive */ 277 RK_BOOL bIvs; /* RW; polarity of vertical synch signal, 0: negative, 1: positive */ 278 279 RK_U16 u16FrameRate; /* RW; frame rate of output */ 280 RK_U32 u32PixClock; /* RW; pixel clock, the unit is KHZ */ 281 } VO_SYNC_INFO_S; 282 283 typedef struct rkVO_PUB_ATTR_S { 284 RK_U32 u32BgColor; /* RW; Background color of a device, in RGB format. */ 285 VO_INTF_TYPE_E enIntfType; /* RW; Type of a VO interface */ 286 VO_INTF_SYNC_E enIntfSync; /* RW; Type of a VO interface timing */ 287 VO_SYNC_INFO_S stSyncInfo; /* RW; Information about VO interface timings */ 288 } VO_PUB_ATTR_S; 289 290 typedef struct rkVO_WBC_ATTR_S { 291 SIZE_S stTargetSize; /* RW; WBC Zoom target size */ 292 PIXEL_FORMAT_E enPixelFormat; /* RW; the pixel format of WBC output */ 293 RK_U32 u32FrameRate; /* RW; frame rate control */ 294 DYNAMIC_RANGE_E enDynamicRange; /* RW; Write back dynamic range type */ 295 COMPRESS_MODE_E enCompressMode; /* RW; Write back Compressing mode */ 296 } VO_WBC_ATTR_S; 297 298 typedef enum rkVO_WBC_MODE_E { 299 /* 300 * In this mode, wbc will capture frames according 301 * to dev frame rate and wbc frame rate 302 */ 303 VO_WBC_MODE_NORMAL = 0, 304 /* 305 * In this mode, wbc will drop dev repeat frame, 306 * and capture the real frame according to video layer's 307 * display rate and wbc frame rate 308 */ 309 VO_WBC_MODE_DROP_REPEAT, 310 /* 311 * In this mode, wbc will drop dev repeat frame 312 * which repeats more than 3 times, and change 313 * two progressive frames to one interlace frame 314 */ 315 VO_WBC_MODE_PROG_TO_INTL, 316 VO_WBC_MODE_BUTT, 317 } VO_WBC_MODE_E; 318 319 typedef enum rkVO_WBC_SOURCE_TYPE_E { 320 VO_WBC_SOURCE_DEV = 0x0, /* WBC source is device */ 321 VO_WBC_SOURCE_VIDEO = 0x1, /* WBC source is video layer */ 322 VO_WBC_SOURCE_GRAPHIC = 0x2, /* WBC source is graphic layer. Warning: not supported */ 323 VO_WBC_SOURCE_VIRTUAL = 0x3, /* WBC source is virtual layer */ 324 VO_WBC_SOURCE_BUTT 325 } VO_WBC_SOURCE_TYPE_E; 326 327 typedef struct rkVO_WBC_SOURCE_S { 328 VO_WBC_SOURCE_TYPE_E enSourceType; /* RW; WBC source's type */ 329 RK_U32 u32SourceId; /* RW; WBC source's ID */ 330 } VO_WBC_SOURCE_S; 331 332 typedef enum rkVO_PART_MODE_E { 333 VO_PART_MODE_SINGLE = 0, /* single partition, which use software to make multi-picture in one hardware cell */ 334 VO_PART_MODE_MULTI = 1, /* muliti partition, each partition is a hardware cell */ 335 VO_PART_MODE_BUTT 336 } VO_PART_MODE_E; 337 338 typedef enum rkVO_SPLICE_MODE_E { 339 VO_SPLICE_MODE_GPU = 0, 340 VO_SPLICE_MODE_RGA 341 } VO_SPLICE_MODE_E; 342 343 typedef enum rkVO_LAYER_MODE_E { 344 VO_LAYER_MODE_CURSOR = 0, 345 VO_LAYER_MODE_GRAPHIC, 346 VO_LAYER_MODE_VIDEO, 347 VO_LAYER_MODE_VIRTUAL, 348 VO_LAYER_MODE_BUTT 349 } VO_LAYER_MODE_E; 350 351 typedef struct rkVO_VIDEO_LAYER_ATTR_S { 352 RECT_S stDispRect; /* RW; Display resolution */ 353 SIZE_S stImageSize; /* RW; Canvas size of the video layer */ 354 RK_U32 u32DispFrmRt; /* RW; Display frame rate */ 355 PIXEL_FORMAT_E enPixFormat; /* RW; Pixel format of the video layer */ 356 RK_BOOL bBypassFrame; /* RW; Whether to bypass frame to video layer */ 357 RK_BOOL bLowDelay; /* RW; Whether start composer at once when channel 0 recive buffer */ 358 COMPRESS_MODE_E enCompressMode; /* RW; Video Layer output compress mode */ 359 DYNAMIC_RANGE_E enDstDynamicRange; /* RW; Video Layer output dynamic range type */ 360 } VO_VIDEO_LAYER_ATTR_S; 361 362 typedef struct rkVO_LAYER_PARAM_S { 363 ASPECT_RATIO_S stAspectRatio; /* RW; aspect ratio */ 364 } VO_LAYER_PARAM_S; 365 366 typedef struct rkVO_ZOOM_RATIO_S { 367 /* 368 * RW; Range: [0, 1000]; XRatio = x * 1000 / W, 369 * x means the start point to be zoomed, 370 * W means displaying channel's width. 371 */ 372 RK_U32 u32XRatio; 373 /* 374 * RW; Range: [0, 1000]; YRatio = y * 1000 / H, 375 * y means the start point to be zoomed, 376 * H means displaying channel's height. 377 */ 378 RK_U32 u32YRatio; 379 /* 380 * RW; Range: [0, 1000]; WRatio = w * 1000 / W, 381 * w means the width to be zoomed, 382 * W means displaying channel's width. 383 */ 384 RK_U32 u32WRatio; 385 /* 386 * RW; Range: [0, 1000]; HRatio = h * 1000 / H, 387 * h means the height to be zoomed, 388 * H means displaying channel's height. 389 */ 390 RK_U32 u32HRatio; 391 } VO_ZOOM_RATIO_S; 392 393 typedef struct rkVO_ZOOM_ATTR_S { 394 VO_ZOOM_IN_E enZoomType; /* choose the type of zoom in */ 395 union { 396 RECT_S stZoomRect; /* zoom in by rect */ 397 VO_ZOOM_RATIO_S stZoomRatio; /* zoom in by ratio */ 398 }; 399 } VO_ZOOM_ATTR_S; 400 401 typedef struct rkVO_CSC_S { 402 VO_CSC_MATRIX_E enCscMatrix; /* CSC matrix */ 403 RK_U32 u32Luma; /* RW; Range: [0, 100]; luminance, default: 50 */ 404 RK_U32 u32Contrast; /* RW; Range: [0, 100]; contrast, default: 50 */ 405 RK_U32 u32Hue; /* RW; Range: [0, 100]; hue, default: 50 */ 406 RK_U32 u32Satuature; /* RW; Range: [0, 100]; satuature, default: 50 */ 407 } VO_CSC_S; 408 409 typedef struct rkVO_REGION_INFO_S { 410 RK_U32 u32RegionNum; /* count of the region */ 411 RECT_S *ATTRIBUTE pstRegion; /* region attribute */ 412 } VO_REGION_INFO_S; 413 414 typedef struct rkVO_LAYER_BOUNDARY_S { 415 RK_U32 u32Width; 416 RK_U32 u32Color[2]; 417 } VO_LAYER_BOUNDARY_S; 418 419 typedef struct rkVO_CHN_BOUNDARY_S { 420 RK_BOOL bBoundaryEn; /* do Frame or not */ 421 RK_U32 u32ColorIndex; /* the index of Frame color,[0,1] */ 422 } VO_CHN_BOUNDARY_S; 423 424 typedef struct rkVO_MOD_PARAM_S { 425 /* 426 * RW, Range: [0, 1]; YC(Luminance and Chrominance) 427 * changes or not when passing through VO 428 */ 429 RK_BOOL bTransparentTransmit; 430 RK_BOOL bExitDev; 431 RK_BOOL bWbcBgBlackEn; 432 RK_BOOL bDevClkExtEn; 433 RK_BOOL bSaveBufMode[VO_MAX_PHY_DEV_NUM]; /* save buff mode */ 434 } VO_MOD_PARAM_S; 435 436 typedef enum rkVO_CLK_SOURCE_E { 437 VO_CLK_SOURCE_PLL, 438 VO_CLK_SOURCE_LCDMCLK, 439 440 VO_CLK_SOURCE_BUTT 441 } VO_CLK_SOURCE_E; 442 443 typedef struct rkVO_USER_INTFSYNC_PLL_S { 444 RK_U32 u32Fbdiv; 445 RK_U32 u32Frac; 446 RK_U32 u32Refdiv; 447 RK_U32 u32Postdiv1; 448 RK_U32 u32Postdiv2; 449 } VO_USER_INTFSYNC_PLL_S; 450 451 typedef struct rkVO_USER_INTFSYNC_ATTR_S { 452 VO_CLK_SOURCE_E enClkSource; 453 454 union { 455 VO_USER_INTFSYNC_PLL_S stUserSyncPll; 456 RK_U32 u32LcdMClkDiv; 457 }; 458 } VO_USER_INTFSYNC_ATTR_S; 459 460 typedef struct rkVO_USER_INTFSYNC_INFO_S { 461 VO_USER_INTFSYNC_ATTR_S stUserIntfSyncAttr; 462 RK_U32 u32PreDiv; 463 RK_U32 u32DevDiv; 464 RK_BOOL bClkReverse; 465 } VO_USER_INTFSYNC_INFO_S; 466 467 typedef struct rkVO_GFX_FRAME_INFO_S { 468 RK_U32 u32Width; 469 RK_U32 u32Height; 470 RK_U32 u32VirWidth; 471 RK_U32 u32VirHeight; 472 PIXEL_FORMAT_E enPixelFormat; 473 RK_U32 u32FgAlpha; 474 RK_U32 u32BgAlpha; 475 RK_VOID *pData; 476 RK_U32 u32Size; 477 } VO_FRAME_INFO_S; 478 479 typedef struct rk_VO_EDID_S { 480 RK_BOOL bEdidValid; 481 RK_U32 u32Edidlength; 482 RK_U8 u8Edid[512]; 483 } VO_EDID_S; 484 485 typedef struct rk_VO_SINK_CAPABILITY_S { 486 RK_BOOL bConnected; 487 RK_BOOL bSupportYCbCr; 488 RK_BOOL bSupportHDMI; 489 } VO_SINK_CAPABILITY_S; 490 491 typedef struct rk_VO_CB_INFO_S { 492 RK_U32 u32Id; 493 RK_U32 u32Sec; 494 RK_U32 u32Usec; 495 } VO_CB_INFO_S; 496 497 /** hpd event handling callback function */ 498 typedef void (*RK_VO_CallBack)(RK_VOID *pPrivateData); 499 500 typedef struct rk_VO_CALLBACK_FUNC_S { 501 RK_VO_CallBack pfnEventCallback; 502 RK_VOID *pPrivateData; 503 } RK_VO_CALLBACK_FUNC_S; 504 505 /** vsync event handling callback function */ 506 typedef void (*RK_VO_VsyncCallBack)(RK_VOID *pPrivateData, VO_CB_INFO_S* info); 507 508 typedef struct rk_VO_VSYNC_CALLBACK_FUNC_S { 509 RK_VO_VsyncCallBack pfnEventCallback; 510 RK_VOID *pPrivateData; 511 } RK_VO_VSYNC_CALLBACK_FUNC_S; 512 513 typedef enum rkVO_GFX_MODE_E { 514 VO_MODE_NORMAL, 515 VO_MODE_GFX_PRE_CREATED 516 } VO_GFX_MODE_E; 517 518 typedef enum rkVO_HDMI_MODE_E { 519 VO_HDMI_MODE_AUTO = 0, /* According EDID */ 520 VO_HDMI_MODE_HDMI, 521 VO_HDMI_MODE_DVI 522 } VO_HDMI_MODE_E; 523 524 typedef enum rkVO_HDMI_COLOR_FMT_E { 525 VO_HDMI_COLOR_FORMAT_RGB = 0, 526 VO_HDMI_COLOR_FORMAT_YCBCR444, 527 VO_HDMI_COLOR_FORMAT_YCBCR422, 528 VO_HDMI_COLOR_FORMAT_YCBCR420, 529 VO_HDMI_COLOR_FORMT_AUTO, 530 VO_HDMI_COLOR_FORMAT_BUTT 531 } VO_HDMI_COLOR_FMT_E; 532 533 typedef enum rkVO_HDMI_QUANT_RANGE_E { 534 VO_HDMI_QUANT_RANGE_AUTO = 0, /* Limited: CEA Mode; Full: Non-CEA Mode */ 535 VO_HDMI_QUANT_RANGE_LIMITED, 536 VO_HDMI_QUANT_RANGE_FULL, 537 VO_HDMI_QUANT_RANGE_BUTT 538 } VO_HDMI_QUANT_RANGE_E; 539 540 typedef struct rk_VO_HDMI_PARAM_S { 541 VO_HDMI_MODE_E enHdmiMode; 542 VO_HDMI_COLOR_FMT_E enColorFmt; 543 VO_HDMI_QUANT_RANGE_E enQuantRange; /* Effective in enColorFmt == RGB mode */ 544 } VO_HDMI_PARAM_S; 545 546 typedef enum rk356X_VO_LAYER_NAME_E { 547 RK356X_VOP_LAYER_CLUSTER0 = 0, 548 RK356X_VOP_LAYER_CLUSTER1 = 2, 549 RK356X_VOP_LAYER_ESMART0 = 4, 550 RK356X_VOP_LAYER_ESMART1, 551 RK356X_VOP_LAYER_SMART0, 552 RK356X_VOP_LAYER_SMART1, 553 } VO_LAYER_NAME_RK356X_E; 554 555 typedef enum rkVOP2_LAYER_NAME_E { 556 VO_LAYER_CLUSTER0 = 0, 557 VO_LAYER_CLUSTER1, 558 VO_LAYER_CLUSTER2, 559 VO_LAYER_CLUSTER3, 560 VO_LAYER_ESMART0, 561 VO_LAYER_ESMART1, 562 VO_LAYER_ESMART2, 563 VO_LAYER_ESMART3, 564 VO_LAYER_BUTT 565 } VO_LAYER_NAME_E; 566 567 typedef enum rkVO_VIR_LAYER_NAME_E { 568 VO_LAYER_VIRTUAL0 = VO_LAYER_BUTT, 569 VO_LAYER_VIRTUAL1, 570 VO_LAYER_VIRTUAL2, 571 VO_LAYER_VIRTUAL3, 572 } VO_VIR_LAYER_NAME_E; 573 574 #ifdef __cplusplus 575 #if __cplusplus 576 } 577 #endif 578 #endif /* End of #ifdef __cplusplus */ 579 580 #endif /* End of #ifndef INCLUDE_RT_MPI_RK_COMMON_VO_H_ */ 581 582 583