1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Register definitions for Rockchip's RK808/RK818 PMIC 4 * 5 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd 6 * 7 * Author: Chris Zhong <zyw@rock-chips.com> 8 * Author: Zhang Qing <zhangqing@rock-chips.com> 9 * 10 * Copyright (C) 2016 PHYTEC Messtechnik GmbH 11 * 12 * Author: Wadim Egorov <w.egorov@phytec.de> 13 */ 14 15 #ifndef __LINUX_REGULATOR_RK808_H 16 #define __LINUX_REGULATOR_RK808_H 17 18 #include <linux/regulator/machine.h> 19 #include <linux/regmap.h> 20 21 /* 22 * rk808 Global Register Map. 23 */ 24 25 #define RK808_DCDC1 0 /* (0+RK808_START) */ 26 #define RK808_LDO1 4 /* (4+RK808_START) */ 27 #define RK808_NUM_REGULATORS 14 28 29 enum rk808_reg { 30 RK808_ID_DCDC1, 31 RK808_ID_DCDC2, 32 RK808_ID_DCDC3, 33 RK808_ID_DCDC4, 34 RK808_ID_LDO1, 35 RK808_ID_LDO2, 36 RK808_ID_LDO3, 37 RK808_ID_LDO4, 38 RK808_ID_LDO5, 39 RK808_ID_LDO6, 40 RK808_ID_LDO7, 41 RK808_ID_LDO8, 42 RK808_ID_SWITCH1, 43 RK808_ID_SWITCH2, 44 }; 45 46 #define RK808_SECONDS_REG 0x00 47 #define RK808_MINUTES_REG 0x01 48 #define RK808_HOURS_REG 0x02 49 #define RK808_DAYS_REG 0x03 50 #define RK808_MONTHS_REG 0x04 51 #define RK808_YEARS_REG 0x05 52 #define RK808_WEEKS_REG 0x06 53 #define RK808_ALARM_SECONDS_REG 0x08 54 #define RK808_ALARM_MINUTES_REG 0x09 55 #define RK808_ALARM_HOURS_REG 0x0a 56 #define RK808_ALARM_DAYS_REG 0x0b 57 #define RK808_ALARM_MONTHS_REG 0x0c 58 #define RK808_ALARM_YEARS_REG 0x0d 59 #define RK808_RTC_CTRL_REG 0x10 60 #define RK808_RTC_STATUS_REG 0x11 61 #define RK808_RTC_INT_REG 0x12 62 #define RK808_RTC_COMP_LSB_REG 0x13 63 #define RK808_RTC_COMP_MSB_REG 0x14 64 #define RK808_ID_MSB 0x17 65 #define RK808_ID_LSB 0x18 66 #define RK808_CLK32OUT_REG 0x20 67 #define RK808_VB_MON_REG 0x21 68 #define RK808_THERMAL_REG 0x22 69 #define RK808_DCDC_EN_REG 0x23 70 #define RK808_LDO_EN_REG 0x24 71 #define RK808_SLEEP_SET_OFF_REG1 0x25 72 #define RK808_SLEEP_SET_OFF_REG2 0x26 73 #define RK808_DCDC_UV_STS_REG 0x27 74 #define RK808_DCDC_UV_ACT_REG 0x28 75 #define RK808_LDO_UV_STS_REG 0x29 76 #define RK808_LDO_UV_ACT_REG 0x2a 77 #define RK808_DCDC_PG_REG 0x2b 78 #define RK808_LDO_PG_REG 0x2c 79 #define RK808_VOUT_MON_TDB_REG 0x2d 80 #define RK808_BUCK1_CONFIG_REG 0x2e 81 #define RK808_BUCK1_ON_VSEL_REG 0x2f 82 #define RK808_BUCK1_SLP_VSEL_REG 0x30 83 #define RK808_BUCK1_DVS_VSEL_REG 0x31 84 #define RK808_BUCK2_CONFIG_REG 0x32 85 #define RK808_BUCK2_ON_VSEL_REG 0x33 86 #define RK808_BUCK2_SLP_VSEL_REG 0x34 87 #define RK808_BUCK2_DVS_VSEL_REG 0x35 88 #define RK808_BUCK3_CONFIG_REG 0x36 89 #define RK808_BUCK4_CONFIG_REG 0x37 90 #define RK808_BUCK4_ON_VSEL_REG 0x38 91 #define RK808_BUCK4_SLP_VSEL_REG 0x39 92 #define RK808_BOOST_CONFIG_REG 0x3a 93 #define RK808_LDO1_ON_VSEL_REG 0x3b 94 #define RK808_LDO1_SLP_VSEL_REG 0x3c 95 #define RK808_LDO2_ON_VSEL_REG 0x3d 96 #define RK808_LDO2_SLP_VSEL_REG 0x3e 97 #define RK808_LDO3_ON_VSEL_REG 0x3f 98 #define RK808_LDO3_SLP_VSEL_REG 0x40 99 #define RK808_LDO4_ON_VSEL_REG 0x41 100 #define RK808_LDO4_SLP_VSEL_REG 0x42 101 #define RK808_LDO5_ON_VSEL_REG 0x43 102 #define RK808_LDO5_SLP_VSEL_REG 0x44 103 #define RK808_LDO6_ON_VSEL_REG 0x45 104 #define RK808_LDO6_SLP_VSEL_REG 0x46 105 #define RK808_LDO7_ON_VSEL_REG 0x47 106 #define RK808_LDO7_SLP_VSEL_REG 0x48 107 #define RK808_LDO8_ON_VSEL_REG 0x49 108 #define RK808_LDO8_SLP_VSEL_REG 0x4a 109 #define RK808_DEVCTRL_REG 0x4b 110 #define RK808_INT_STS_REG1 0x4c 111 #define RK808_INT_STS_MSK_REG1 0x4d 112 #define RK808_INT_STS_REG2 0x4e 113 #define RK808_INT_STS_MSK_REG2 0x4f 114 #define RK808_IO_POL_REG 0x50 115 116 /* RK816 */ 117 enum rk816_reg { 118 RK816_ID_DCDC1, 119 RK816_ID_DCDC2, 120 RK816_ID_DCDC3, 121 RK816_ID_DCDC4, 122 RK816_ID_LDO1, 123 RK816_ID_LDO2, 124 RK816_ID_LDO3, 125 RK816_ID_LDO4, 126 RK816_ID_LDO5, 127 RK816_ID_LDO6, 128 }; 129 130 /*VERSION REGISTER*/ 131 #define RK816_CHIP_NAME_REG 0x17 132 #define RK816_CHIP_VER_REG 0x18 133 #define RK816_OTP_VER_REG 0x19 134 #define RK816_NUM_REGULATORS 10 135 136 /*POWER ON/OFF REGISTER*/ 137 #define RK816_VB_MON_REG 0x21 138 #define RK816_THERMAL_REG 0x22 139 #define RK816_PWRON_LP_INT_TIME_REG 0x47 140 #define RK816_PWRON_DB_REG 0x48 141 #define RK816_DEV_CTRL_REG 0x4B 142 #define RK816_ON_SOURCE_REG 0xAE 143 #define RK816_OFF_SOURCE_REG 0xAF 144 145 /*POWER CHANNELS ENABLE REGISTER*/ 146 #define RK816_DCDC_EN_REG1 0x23 147 #define RK816_DCDC_EN_REG2 0x24 148 #define RK816_SLP_DCDC_EN_REG 0x25 149 #define RK816_SLP_LDO_EN_REG 0x26 150 #define RK816_LDO_EN_REG1 0x27 151 #define RK816_LDO_EN_REG2 0x28 152 153 /*BUCK AND LDO CONFIG REGISTER*/ 154 #define RK816_BUCK1_CONFIG_REG 0x2E 155 #define RK816_BUCK1_ON_VSEL_REG 0x2F 156 #define RK816_BUCK1_SLP_VSEL_REG 0x30 157 #define RK816_BUCK2_CONFIG_REG 0x32 158 #define RK816_BUCK2_ON_VSEL_REG 0x33 159 #define RK816_BUCK2_SLP_VSEL_REG 0x34 160 #define RK816_BUCK3_CONFIG_REG 0x36 161 #define RK816_BUCK4_CONFIG_REG 0x37 162 #define RK816_BUCK4_ON_VSEL_REG 0x38 163 #define RK816_BUCK4_SLP_VSEL_REG 0x39 164 #define RK816_LDO1_ON_VSEL_REG 0x3B 165 #define RK816_LDO1_SLP_VSEL_REG 0x3C 166 #define RK816_LDO2_ON_VSEL_REG 0x3D 167 #define RK816_LDO2_SLP_VSEL_REG 0x3E 168 #define RK816_LDO3_ON_VSEL_REG 0x3F 169 #define RK816_LDO3_SLP_VSEL_REG 0x40 170 #define RK816_LDO4_ON_VSEL_REG 0x41 171 #define RK816_LDO4_SLP_VSEL_REG 0x42 172 #define RK816_LDO5_ON_VSEL_REG 0x43 173 #define RK816_LDO5_SLP_VSEL_REG 0x44 174 #define RK816_LDO6_ON_VSEL_REG 0x45 175 #define RK816_LDO6_SLP_VSEL_REG 0x46 176 #define RK816_GPIO_IO_POL_REG 0x50 177 178 /*CHARGER BOOST AND OTG REGISTER*/ 179 #define RK816_OTG_BUCK_LDO_CONFIG_REG 0x2A 180 #define RK816_CHRG_CONFIG_REG 0x2B 181 #define RK816_BOOST_ON_VESL_REG 0x54 182 #define RK816_BOOST_SLP_VSEL_REG 0x55 183 #define RK816_CHRG_BOOST_CONFIG_REG 0x9A 184 #define RK816_SUP_STS_REG 0xA0 185 #define RK816_USB_CTRL_REG 0xA1 186 #define RK816_CHRG_CTRL_REG1 0xA3 187 #define RK816_CHRG_CTRL_REG2 0xA4 188 #define RK816_CHRG_CTRL_REG3 0xA5 189 #define RK816_BAT_CTRL_REG 0xA6 190 #define RK816_BAT_HTS_TS_REG 0xA8 191 #define RK816_BAT_LTS_TS_REG 0xA9 192 193 #define RK816_TS_CTRL_REG 0xAC 194 #define RK816_ADC_CTRL_REG 0xAD 195 #define RK816_GGCON_REG 0xB0 196 #define RK816_GGSTS_REG 0xB1 197 #define RK816_ZERO_CUR_ADC_REGH 0xB2 198 #define RK816_ZERO_CUR_ADC_REGL 0xB3 199 #define RK816_GASCNT_CAL_REG3 0xB4 200 #define RK816_GASCNT_CAL_REG2 0xB5 201 #define RK816_GASCNT_CAL_REG1 0xB6 202 #define RK816_GASCNT_CAL_REG0 0xB7 203 #define RK816_GASCNT_REG3 0xB8 204 #define RK816_GASCNT_REG2 0xB9 205 #define RK816_GASCNT_REG1 0xBA 206 #define RK816_GASCNT_REG0 0xBB 207 #define RK816_BAT_CUR_AVG_REGH 0xBC 208 #define RK816_BAT_CUR_AVG_REGL 0xBD 209 #define RK816_TS_ADC_REGH 0xBE 210 #define RK816_TS_ADC_REGL 0xBF 211 #define RK816_USB_ADC_REGH 0xC0 212 #define RK816_USB_ADC_REGL 0xC1 213 #define RK816_BAT_OCV_REGH 0xC2 214 #define RK816_BAT_OCV_REGL 0xC3 215 #define RK816_BAT_VOL_REGH 0xC4 216 #define RK816_BAT_VOL_REGL 0xC5 217 #define RK816_RELAX_ENTRY_THRES_REGH 0xC6 218 #define RK816_RELAX_ENTRY_THRES_REGL 0xC7 219 #define RK816_RELAX_EXIT_THRES_REGH 0xC8 220 #define RK816_RELAX_EXIT_THRES_REGL 0xC9 221 #define RK816_RELAX_VOL1_REGH 0xCA 222 #define RK816_RELAX_VOL1_REGL 0xCB 223 #define RK816_RELAX_VOL2_REGH 0xCC 224 #define RK816_RELAX_VOL2_REGL 0xCD 225 #define RK816_RELAX_CUR1_REGH 0xCE 226 #define RK816_RELAX_CUR1_REGL 0xCF 227 #define RK816_RELAX_CUR2_REGH 0xD0 228 #define RK816_RELAX_CUR2_REGL 0xD1 229 #define RK816_CAL_OFFSET_REGH 0xD2 230 #define RK816_CAL_OFFSET_REGL 0xD3 231 #define RK816_NON_ACT_TIMER_CNT_REG 0xD4 232 #define RK816_VCALIB0_REGH 0xD5 233 #define RK816_VCALIB0_REGL 0xD6 234 #define RK816_VCALIB1_REGH 0xD7 235 #define RK816_VCALIB1_REGL 0xD8 236 #define RK816_FCC_GASCNT_REG3 0xD9 237 #define RK816_FCC_GASCNT_REG2 0xDA 238 #define RK816_FCC_GASCNT_REG1 0xDB 239 #define RK816_FCC_GASCNT_REG0 0xDC 240 #define RK816_IOFFSET_REGH 0xDD 241 #define RK816_IOFFSET_REGL 0xDE 242 #define RK816_SLEEP_CON_SAMP_CUR_REG 0xDF 243 244 /*DATA REGISTER*/ 245 #define RK816_SOC_REG 0xE0 246 #define RK816_REMAIN_CAP_REG3 0xE1 247 #define RK816_REMAIN_CAP_REG2 0xE2 248 #define RK816_REMAIN_CAP_REG1 0xE3 249 #define RK816_REMAIN_CAP_REG0 0xE4 250 #define RK816_UPDATE_LEVE_REG 0xE5 251 #define RK816_NEW_FCC_REG3 0xE6 252 #define RK816_NEW_FCC_REG2 0xE7 253 #define RK816_NEW_FCC_REG1 0xE8 254 #define RK816_NEW_FCC_REG0 0xE9 255 #define RK816_NON_ACT_TIMER_CNT_REG_SAVE 0xEA 256 #define RK816_OCV_VOL_VALID_REG 0xEB 257 #define RK816_REBOOT_CNT_REG 0xEC 258 #define RK816_PCB_IOFFSET_REG 0xED 259 #define RK816_MISC_MARK_REG 0xEE 260 #define RK816_HALT_CNT_REG 0xEF 261 #define RK816_CALC_REST_REGH 0xF0 262 #define RK816_CALC_REST_REGL 0xF1 263 #define DATA18_REG 0xF2 264 265 /*INTERRUPT REGISTER*/ 266 #define RK816_INT_STS_REG1 0x49 267 #define RK816_INT_STS_MSK_REG1 0x4A 268 #define RK816_INT_STS_REG2 0x4C 269 #define RK816_INT_STS_MSK_REG2 0x4D 270 #define RK816_INT_STS_REG3 0x4E 271 #define RK816_INT_STS_MSK_REG3 0x4F 272 #define RK816_GPIO_IO_POL_REG 0x50 273 274 #define RK816_DATA18_REG 0xF2 275 276 /* IRQ Definitions */ 277 #define RK816_IRQ_PWRON_FALL 0 278 #define RK816_IRQ_PWRON_RISE 1 279 #define RK816_IRQ_VB_LOW 2 280 #define RK816_IRQ_PWRON 3 281 #define RK816_IRQ_PWRON_LP 4 282 #define RK816_IRQ_HOTDIE 5 283 #define RK816_IRQ_RTC_ALARM 6 284 #define RK816_IRQ_RTC_PERIOD 7 285 #define RK816_IRQ_USB_OV 8 286 #define RK816_IRQ_PLUG_IN 9 287 #define RK816_IRQ_PLUG_OUT 10 288 #define RK816_IRQ_CHG_OK 11 289 #define RK816_IRQ_CHG_TE 12 290 #define RK816_IRQ_CHG_TS 13 291 #define RK816_IRQ_CHG_CVTLIM 14 292 #define RK816_IRQ_DISCHG_ILIM 15 293 294 #define RK816_IRQ_PWRON_FALL_MSK BIT(5) 295 #define RK816_IRQ_PWRON_RISE_MSK BIT(6) 296 #define RK816_IRQ_VB_LOW_MSK BIT(1) 297 #define RK816_IRQ_PWRON_MSK BIT(2) 298 #define RK816_IRQ_PWRON_LP_MSK BIT(3) 299 #define RK816_IRQ_HOTDIE_MSK BIT(4) 300 #define RK816_IRQ_RTC_ALARM_MSK BIT(5) 301 #define RK816_IRQ_RTC_PERIOD_MSK BIT(6) 302 #define RK816_IRQ_USB_OV_MSK BIT(7) 303 #define RK816_IRQ_PLUG_IN_MSK BIT(0) 304 #define RK816_IRQ_PLUG_OUT_MSK BIT(1) 305 #define RK816_IRQ_CHG_OK_MSK BIT(2) 306 #define RK816_IRQ_CHG_TE_MSK BIT(3) 307 #define RK816_IRQ_CHG_TS_MSK BIT(4) 308 #define RK816_IRQ_CHG_CVTLIM_MSK BIT(6) 309 #define RK816_IRQ_DISCHG_ILIM_MSK BIT(7) 310 311 #define RK816_VBAT_LOW_2V8 0x00 312 #define RK816_VBAT_LOW_2V9 0x01 313 #define RK816_VBAT_LOW_3V0 0x02 314 #define RK816_VBAT_LOW_3V1 0x03 315 #define RK816_VBAT_LOW_3V2 0x04 316 #define RK816_VBAT_LOW_3V3 0x05 317 #define RK816_VBAT_LOW_3V4 0x06 318 #define RK816_VBAT_LOW_3V5 0x07 319 #define RK816_PWR_FALL_INT_STATUS (0x1 << 5) 320 #define RK816_PWR_RISE_INT_STATUS (0x1 << 6) 321 #define RK816_ALARM_INT_STATUS (0x1 << 5) 322 #define EN_VBAT_LOW_IRQ (0x1 << 4) 323 #define VBAT_LOW_ACT_MASK (0x1 << 4) 324 #define RTC_TIMER_ALARM_INT_MSK (0x3 << 2) 325 #define RTC_TIMER_ALARM_INT_DIS (0x0 << 2) 326 #define RTC_PERIOD_ALARM_INT_MSK (0x3 << 5) 327 #define RTC_PERIOD_ALARM_INT_ST (0x3 << 5) 328 #define RTC_PERIOD_ALARM_INT_DIS (0x3 << 5) 329 #define RTC_PERIOD_ALARM_INT_EN (0x9f) 330 #define REG_WRITE_MSK 0xff 331 #define BUCK4_MAX_ILIMIT 0x2c 332 #define BUCK_RATE_MSK (0x3 << 3) 333 #define BUCK_RATE_12_5MV_US (0x2 << 3) 334 #define ALL_INT_FLAGS_ST 0xff 335 #define PLUGIN_OUT_INT_EN 0xfc 336 #define RK816_PWRON_FALL_RISE_INT_EN 0x9f 337 #define BUCK1_2_IMAX_MAX (0x3 << 6) 338 #define BUCK3_4_IMAX_MAX (0x3 << 3) 339 #define BOOST_DISABLE ((0x1 << 5) | (0x0 << 1)) 340 #define BUCK4_VRP_3PERCENT 0xc0 341 #define RK816_BUCK_DVS_CONFIRM (0x1 << 7) 342 #define RK816_TYPE_ES2 0x05 343 #define RK816_CHIP_VERSION_MASK 0x0f 344 345 /* RK818 */ 346 #define RK818_DCDC1 0 347 #define RK818_LDO1 4 348 #define RK818_NUM_REGULATORS 17 349 350 enum rk818_reg { 351 RK818_ID_DCDC1, 352 RK818_ID_DCDC2, 353 RK818_ID_DCDC3, 354 RK818_ID_DCDC4, 355 RK818_ID_BOOST, 356 RK818_ID_LDO1, 357 RK818_ID_LDO2, 358 RK818_ID_LDO3, 359 RK818_ID_LDO4, 360 RK818_ID_LDO5, 361 RK818_ID_LDO6, 362 RK818_ID_LDO7, 363 RK818_ID_LDO8, 364 RK818_ID_LDO9, 365 RK818_ID_SWITCH, 366 RK818_ID_HDMI_SWITCH, 367 RK818_ID_OTG_SWITCH, 368 }; 369 370 #define RK818_VB_MON_REG 0x21 371 #define RK818_THERMAL_REG 0x22 372 #define RK818_DCDC_EN_REG 0x23 373 #define RK818_LDO_EN_REG 0x24 374 #define RK818_SLEEP_SET_OFF_REG1 0x25 375 #define RK818_SLEEP_SET_OFF_REG2 0x26 376 #define RK818_DCDC_UV_STS_REG 0x27 377 #define RK818_DCDC_UV_ACT_REG 0x28 378 #define RK818_LDO_UV_STS_REG 0x29 379 #define RK818_LDO_UV_ACT_REG 0x2a 380 #define RK818_DCDC_PG_REG 0x2b 381 #define RK818_LDO_PG_REG 0x2c 382 #define RK818_VOUT_MON_TDB_REG 0x2d 383 #define RK818_BUCK1_CONFIG_REG 0x2e 384 #define RK818_BUCK1_ON_VSEL_REG 0x2f 385 #define RK818_BUCK1_SLP_VSEL_REG 0x30 386 #define RK818_BUCK2_CONFIG_REG 0x32 387 #define RK818_BUCK2_ON_VSEL_REG 0x33 388 #define RK818_BUCK2_SLP_VSEL_REG 0x34 389 #define RK818_BUCK3_CONFIG_REG 0x36 390 #define RK818_BUCK4_CONFIG_REG 0x37 391 #define RK818_BUCK4_ON_VSEL_REG 0x38 392 #define RK818_BUCK4_SLP_VSEL_REG 0x39 393 #define RK818_BOOST_CONFIG_REG 0x3a 394 #define RK818_LDO1_ON_VSEL_REG 0x3b 395 #define RK818_LDO1_SLP_VSEL_REG 0x3c 396 #define RK818_LDO2_ON_VSEL_REG 0x3d 397 #define RK818_LDO2_SLP_VSEL_REG 0x3e 398 #define RK818_LDO3_ON_VSEL_REG 0x3f 399 #define RK818_LDO3_SLP_VSEL_REG 0x40 400 #define RK818_LDO4_ON_VSEL_REG 0x41 401 #define RK818_LDO4_SLP_VSEL_REG 0x42 402 #define RK818_LDO5_ON_VSEL_REG 0x43 403 #define RK818_LDO5_SLP_VSEL_REG 0x44 404 #define RK818_LDO6_ON_VSEL_REG 0x45 405 #define RK818_LDO6_SLP_VSEL_REG 0x46 406 #define RK818_LDO7_ON_VSEL_REG 0x47 407 #define RK818_LDO7_SLP_VSEL_REG 0x48 408 #define RK818_LDO8_ON_VSEL_REG 0x49 409 #define RK818_LDO8_SLP_VSEL_REG 0x4a 410 #define RK818_BOOST_LDO9_ON_VSEL_REG 0x54 411 #define RK818_BOOST_LDO9_SLP_VSEL_REG 0x55 412 #define RK818_DEVCTRL_REG 0x4b 413 #define RK818_INT_STS_REG1 0X4c 414 #define RK818_INT_STS_MSK_REG1 0x4d 415 #define RK818_INT_STS_REG2 0x4e 416 #define RK818_INT_STS_MSK_REG2 0x4f 417 #define RK818_IO_POL_REG 0x50 418 #define RK818_H5V_EN_REG 0x52 419 #define RK818_SLEEP_SET_OFF_REG3 0x53 420 #define RK818_BOOST_LDO9_ON_VSEL_REG 0x54 421 #define RK818_BOOST_LDO9_SLP_VSEL_REG 0x55 422 #define RK818_BOOST_CTRL_REG 0x56 423 #define RK818_DCDC_ILMAX 0x90 424 #define RK818_CHRG_COMP_REG 0x9a 425 #define RK818_SUP_STS_REG 0xa0 426 #define RK818_USB_CTRL_REG 0xa1 427 #define RK818_CHRG_CTRL_REG1 0xa3 428 #define RK818_CHRG_CTRL_REG2 0xa4 429 #define RK818_CHRG_CTRL_REG3 0xa5 430 #define RK818_BAT_CTRL_REG 0xa6 431 #define RK818_BAT_HTS_TS1_REG 0xa8 432 #define RK818_BAT_LTS_TS1_REG 0xa9 433 #define RK818_BAT_HTS_TS2_REG 0xaa 434 #define RK818_BAT_LTS_TS2_REG 0xab 435 #define RK818_TS_CTRL_REG 0xac 436 #define RK818_ADC_CTRL_REG 0xad 437 #define RK818_ON_SOURCE_REG 0xae 438 #define RK818_OFF_SOURCE_REG 0xaf 439 #define RK818_GGCON_REG 0xb0 440 #define RK818_GGSTS_REG 0xb1 441 #define RK818_FRAME_SMP_INTERV_REG 0xb2 442 #define RK818_AUTO_SLP_CUR_THR_REG 0xb3 443 #define RK818_GASCNT_CAL_REG3 0xb4 444 #define RK818_GASCNT_CAL_REG2 0xb5 445 #define RK818_GASCNT_CAL_REG1 0xb6 446 #define RK818_GASCNT_CAL_REG0 0xb7 447 #define RK818_GASCNT3_REG 0xb8 448 #define RK818_GASCNT2_REG 0xb9 449 #define RK818_GASCNT1_REG 0xba 450 #define RK818_GASCNT0_REG 0xbb 451 #define RK818_BAT_CUR_AVG_REGH 0xbc 452 #define RK818_BAT_CUR_AVG_REGL 0xbd 453 #define RK818_TS1_ADC_REGH 0xbe 454 #define RK818_TS1_ADC_REGL 0xbf 455 #define RK818_TS2_ADC_REGH 0xc0 456 #define RK818_TS2_ADC_REGL 0xc1 457 #define RK818_BAT_OCV_REGH 0xc2 458 #define RK818_BAT_OCV_REGL 0xc3 459 #define RK818_BAT_VOL_REGH 0xc4 460 #define RK818_BAT_VOL_REGL 0xc5 461 #define RK818_RELAX_ENTRY_THRES_REGH 0xc6 462 #define RK818_RELAX_ENTRY_THRES_REGL 0xc7 463 #define RK818_RELAX_EXIT_THRES_REGH 0xc8 464 #define RK818_RELAX_EXIT_THRES_REGL 0xc9 465 #define RK818_RELAX_VOL1_REGH 0xca 466 #define RK818_RELAX_VOL1_REGL 0xcb 467 #define RK818_RELAX_VOL2_REGH 0xcc 468 #define RK818_RELAX_VOL2_REGL 0xcd 469 #define RK818_BAT_CUR_R_CALC_REGH 0xce 470 #define RK818_BAT_CUR_R_CALC_REGL 0xcf 471 #define RK818_BAT_VOL_R_CALC_REGH 0xd0 472 #define RK818_BAT_VOL_R_CALC_REGL 0xd1 473 #define RK818_CAL_OFFSET_REGH 0xd2 474 #define RK818_CAL_OFFSET_REGL 0xd3 475 #define RK818_NON_ACT_TIMER_CNT_REG 0xd4 476 #define RK818_VCALIB0_REGH 0xd5 477 #define RK818_VCALIB0_REGL 0xd6 478 #define RK818_VCALIB1_REGH 0xd7 479 #define RK818_VCALIB1_REGL 0xd8 480 #define RK818_IOFFSET_REGH 0xdd 481 #define RK818_IOFFSET_REGL 0xde 482 #define RK818_SOC_REG 0xe0 483 #define RK818_REMAIN_CAP_REG3 0xe1 484 #define RK818_REMAIN_CAP_REG2 0xe2 485 #define RK818_REMAIN_CAP_REG1 0xe3 486 #define RK818_REMAIN_CAP_REG0 0xe4 487 #define RK818_UPDAT_LEVE_REG 0xe5 488 #define RK818_NEW_FCC_REG3 0xe6 489 #define RK818_NEW_FCC_REG2 0xe7 490 #define RK818_NEW_FCC_REG1 0xe8 491 #define RK818_NEW_FCC_REG0 0xe9 492 #define RK818_NON_ACT_TIMER_CNT_SAVE_REG 0xea 493 #define RK818_OCV_VOL_VALID_REG 0xeb 494 #define RK818_REBOOT_CNT_REG 0xec 495 #define RK818_POFFSET_REG 0xed 496 #define RK818_MISC_MARK_REG 0xee 497 #define RK818_HALT_CNT_REG 0xef 498 #define RK818_CALC_REST_REGH 0xf0 499 #define RK818_CALC_REST_REGL 0xf1 500 #define RK818_SAVE_DATA19 0xf2 501 #define RK818_NUM_REGULATOR 17 502 503 #define RK818_H5V_EN BIT(0) 504 #define RK818_REF_RDY_CTRL BIT(1) 505 #define RK818_USB_ILIM_SEL_MASK 0xf 506 #define RK818_USB_ILMIN_2000MA 0x7 507 #define RK818_USB_CHG_SD_VSEL_MASK 0x70 508 509 /* RK805 */ 510 enum rk805_reg { 511 RK805_ID_DCDC1, 512 RK805_ID_DCDC2, 513 RK805_ID_DCDC3, 514 RK805_ID_DCDC4, 515 RK805_ID_LDO1, 516 RK805_ID_LDO2, 517 RK805_ID_LDO3, 518 }; 519 520 /* CONFIG REGISTER */ 521 #define RK805_VB_MON_REG 0x21 522 #define RK805_THERMAL_REG 0x22 523 524 /* POWER CHANNELS ENABLE REGISTER */ 525 #define RK805_DCDC_EN_REG 0x23 526 #define RK805_SLP_DCDC_EN_REG 0x25 527 #define RK805_SLP_LDO_EN_REG 0x26 528 #define RK805_LDO_EN_REG 0x27 529 530 /* BUCK AND LDO CONFIG REGISTER */ 531 #define RK805_BUCK_LDO_SLP_LP_EN_REG 0x2A 532 #define RK805_BUCK1_CONFIG_REG 0x2E 533 #define RK805_BUCK1_ON_VSEL_REG 0x2F 534 #define RK805_BUCK1_SLP_VSEL_REG 0x30 535 #define RK805_BUCK2_CONFIG_REG 0x32 536 #define RK805_BUCK2_ON_VSEL_REG 0x33 537 #define RK805_BUCK2_SLP_VSEL_REG 0x34 538 #define RK805_BUCK3_CONFIG_REG 0x36 539 #define RK805_BUCK4_CONFIG_REG 0x37 540 #define RK805_BUCK4_ON_VSEL_REG 0x38 541 #define RK805_BUCK4_SLP_VSEL_REG 0x39 542 #define RK805_LDO1_ON_VSEL_REG 0x3B 543 #define RK805_LDO1_SLP_VSEL_REG 0x3C 544 #define RK805_LDO2_ON_VSEL_REG 0x3D 545 #define RK805_LDO2_SLP_VSEL_REG 0x3E 546 #define RK805_LDO3_ON_VSEL_REG 0x3F 547 #define RK805_LDO3_SLP_VSEL_REG 0x40 548 549 /* INTERRUPT REGISTER */ 550 #define RK805_PWRON_LP_INT_TIME_REG 0x47 551 #define RK805_PWRON_DB_REG 0x48 552 #define RK805_DEV_CTRL_REG 0x4B 553 #define RK805_INT_STS_REG 0x4C 554 #define RK805_INT_STS_MSK_REG 0x4D 555 #define RK805_GPIO_IO_POL_REG 0x50 556 #define RK805_OUT_REG 0x52 557 #define RK805_ON_SOURCE_REG 0xAE 558 #define RK805_OFF_SOURCE_REG 0xAF 559 560 #define RK805_NUM_REGULATORS 7 561 562 #define RK805_PWRON_FALL_RISE_INT_EN 0x0 563 #define RK805_PWRON_FALL_RISE_INT_MSK 0x81 564 565 /* RK805 IRQ Definitions */ 566 #define RK805_IRQ_VB_LOW 1 567 #define RK805_IRQ_PWRON 2 568 #define RK805_IRQ_PWRON_LP 3 569 #define RK805_IRQ_HOTDIE 4 570 #define RK805_IRQ_RTC_ALARM 5 571 #define RK805_IRQ_RTC_PERIOD 6 572 573 /* 574 * When PMIC irq occurs, regmap-irq.c will traverse all PMIC child 575 * interrupts from low index 0 to high index, we give fall interrupt 576 * high priority to be called earlier than rise, so that it can be 577 * override by late rise event. This can helps to solve key release 578 * glitch which make a wrongly fall event immediately after rise. 579 */ 580 #define RK805_IRQ_PWRON_FALL 0 581 #define RK805_IRQ_PWRON_RISE 7 582 583 #define RK805_IRQ_PWRON_RISE_MSK BIT(0) 584 #define RK805_IRQ_VB_LOW_MSK BIT(1) 585 #define RK805_IRQ_PWRON_MSK BIT(2) 586 #define RK805_IRQ_PWRON_LP_MSK BIT(3) 587 #define RK805_IRQ_HOTDIE_MSK BIT(4) 588 #define RK805_IRQ_RTC_ALARM_MSK BIT(5) 589 #define RK805_IRQ_RTC_PERIOD_MSK BIT(6) 590 #define RK805_IRQ_PWRON_FALL_MSK BIT(7) 591 592 #define RK805_PWR_RISE_INT_STATUS BIT(0) 593 #define RK805_VB_LOW_INT_STATUS BIT(1) 594 #define RK805_PWRON_INT_STATUS BIT(2) 595 #define RK805_PWRON_LP_INT_STATUS BIT(3) 596 #define RK805_HOTDIE_INT_STATUS BIT(4) 597 #define RK805_ALARM_INT_STATUS BIT(5) 598 #define RK805_PERIOD_INT_STATUS BIT(6) 599 #define RK805_PWR_FALL_INT_STATUS BIT(7) 600 601 #define RK805_BUCK1_2_ILMAX_MASK (3 << 6) 602 #define RK805_BUCK3_4_ILMAX_MASK (3 << 3) 603 #define RK805_RTC_PERIOD_INT_MASK (1 << 6) 604 #define RK805_RTC_ALARM_INT_MASK (1 << 5) 605 #define RK805_INT_ALARM_EN (1 << 3) 606 #define RK805_INT_TIMER_EN (1 << 2) 607 608 #define RK805_SLP_LDO_EN_OFFSET -1 609 #define RK805_SLP_DCDC_EN_OFFSET 2 610 611 #define RK805_RAMP_RATE_OFFSET 3 612 #define RK805_RAMP_RATE_MASK (3 << RK805_RAMP_RATE_OFFSET) 613 #define RK805_RAMP_RATE_3MV_PER_US (0 << RK805_RAMP_RATE_OFFSET) 614 #define RK805_RAMP_RATE_6MV_PER_US (1 << RK805_RAMP_RATE_OFFSET) 615 #define RK805_RAMP_RATE_12_5MV_PER_US (2 << RK805_RAMP_RATE_OFFSET) 616 #define RK805_RAMP_RATE_25MV_PER_US (3 << RK805_RAMP_RATE_OFFSET) 617 618 /* RK808 IRQ Definitions */ 619 #define RK808_IRQ_VOUT_LO 0 620 #define RK808_IRQ_VB_LO 1 621 #define RK808_IRQ_PWRON 2 622 #define RK808_IRQ_PWRON_LP 3 623 #define RK808_IRQ_HOTDIE 4 624 #define RK808_IRQ_RTC_ALARM 5 625 #define RK808_IRQ_RTC_PERIOD 6 626 #define RK808_IRQ_PLUG_IN_INT 7 627 #define RK808_IRQ_PLUG_OUT_INT 8 628 #define RK808_NUM_IRQ 9 629 630 #define RK808_IRQ_VOUT_LO_MSK BIT(0) 631 #define RK808_IRQ_VB_LO_MSK BIT(1) 632 #define RK808_IRQ_PWRON_MSK BIT(2) 633 #define RK808_IRQ_PWRON_LP_MSK BIT(3) 634 #define RK808_IRQ_HOTDIE_MSK BIT(4) 635 #define RK808_IRQ_RTC_ALARM_MSK BIT(5) 636 #define RK808_IRQ_RTC_PERIOD_MSK BIT(6) 637 #define RK808_IRQ_PLUG_IN_INT_MSK BIT(0) 638 #define RK808_IRQ_PLUG_OUT_INT_MSK BIT(1) 639 640 /* RK818 IRQ Definitions */ 641 #define RK818_IRQ_VOUT_LO 0 642 #define RK818_IRQ_VB_LO 1 643 #define RK818_IRQ_PWRON 2 644 #define RK818_IRQ_PWRON_LP 3 645 #define RK818_IRQ_HOTDIE 4 646 #define RK818_IRQ_RTC_ALARM 5 647 #define RK818_IRQ_RTC_PERIOD 6 648 #define RK818_IRQ_USB_OV 7 649 #define RK818_IRQ_PLUG_IN 8 650 #define RK818_IRQ_PLUG_OUT 9 651 #define RK818_IRQ_CHG_OK 10 652 #define RK818_IRQ_CHG_TE 11 653 #define RK818_IRQ_CHG_TS1 12 654 #define RK818_IRQ_TS2 13 655 #define RK818_IRQ_CHG_CVTLIM 14 656 #define RK818_IRQ_DISCHG_ILIM 15 657 658 #define RK818_IRQ_VOUT_LO_MSK BIT(0) 659 #define RK818_IRQ_VB_LO_MSK BIT(1) 660 #define RK818_IRQ_PWRON_MSK BIT(2) 661 #define RK818_IRQ_PWRON_LP_MSK BIT(3) 662 #define RK818_IRQ_HOTDIE_MSK BIT(4) 663 #define RK818_IRQ_RTC_ALARM_MSK BIT(5) 664 #define RK818_IRQ_RTC_PERIOD_MSK BIT(6) 665 #define RK818_IRQ_USB_OV_MSK BIT(7) 666 #define RK818_IRQ_PLUG_IN_MSK BIT(0) 667 #define RK818_IRQ_PLUG_OUT_MSK BIT(1) 668 #define RK818_IRQ_CHG_OK_MSK BIT(2) 669 #define RK818_IRQ_CHG_TE_MSK BIT(3) 670 #define RK818_IRQ_CHG_TS1_MSK BIT(4) 671 #define RK818_IRQ_TS2_MSK BIT(5) 672 #define RK818_IRQ_CHG_CVTLIM_MSK BIT(6) 673 #define RK818_IRQ_DISCHG_ILIM_MSK BIT(7) 674 675 #define RK818_NUM_IRQ 16 676 677 /*RK818_DCDC_EN_REG*/ 678 #define BUCK1_EN_MASK BIT(0) 679 #define BUCK2_EN_MASK BIT(1) 680 #define BUCK3_EN_MASK BIT(2) 681 #define BUCK4_EN_MASK BIT(3) 682 #define BOOST_EN_MASK BIT(4) 683 #define LDO9_EN_MASK BIT(5) 684 #define SWITCH_EN_MASK BIT(6) 685 #define OTG_EN_MASK BIT(7) 686 687 #define BUCK1_EN_ENABLE BIT(0) 688 #define BUCK2_EN_ENABLE BIT(1) 689 #define BUCK3_EN_ENABLE BIT(2) 690 #define BUCK4_EN_ENABLE BIT(3) 691 #define BOOST_EN_ENABLE BIT(4) 692 #define LDO9_EN_ENABLE BIT(5) 693 #define SWITCH_EN_ENABLE BIT(6) 694 #define OTG_EN_ENABLE BIT(7) 695 696 #define BUCK1_SLP_SET_MASK BIT(0) 697 #define BUCK2_SLP_SET_MASK BIT(1) 698 #define BUCK3_SLP_SET_MASK BIT(2) 699 #define BUCK4_SLP_SET_MASK BIT(3) 700 #define BOOST_SLP_SET_MASK BIT(4) 701 #define LDO9_SLP_SET_MASK BIT(5) 702 #define SWITCH_SLP_SET_MASK BIT(6) 703 #define OTG_SLP_SET_MASK BIT(7) 704 705 #define BUCK1_SLP_SET_OFF BIT(0) 706 #define BUCK2_SLP_SET_OFF BIT(1) 707 #define BUCK3_SLP_SET_OFF BIT(2) 708 #define BUCK4_SLP_SET_OFF BIT(3) 709 #define BOOST_SLP_SET_OFF BIT(4) 710 #define LDO9_SLP_SET_OFF BIT(5) 711 #define SWITCH_SLP_SET_OFF BIT(6) 712 #define OTG_SLP_SET_OFF BIT(7) 713 #define OTG_BOOST_SLP_OFF (BOOST_SLP_SET_OFF | OTG_SLP_SET_OFF) 714 715 #define BUCK1_SLP_SET_ON BIT(0) 716 #define BUCK2_SLP_SET_ON BIT(1) 717 #define BUCK3_SLP_SET_ON BIT(2) 718 #define BUCK4_SLP_SET_ON BIT(3) 719 #define BOOST_SLP_SET_ON BIT(4) 720 #define LDO9_SLP_SET_ON BIT(5) 721 #define SWITCH_SLP_SET_ON BIT(6) 722 #define OTG_SLP_SET_ON BIT(7) 723 724 #define VOUT_LO_MASK BIT(0) 725 #define VB_LO_MASK BIT(1) 726 #define PWRON_MASK BIT(2) 727 #define PWRON_LP_MASK BIT(3) 728 #define HOTDIE_MASK BIT(4) 729 #define RTC_ALARM_MASK BIT(5) 730 #define RTC_PERIOD_MASK BIT(6) 731 #define USB_OV_MASK BIT(7) 732 733 #define VOUT_LO_DISABLE BIT(0) 734 #define VB_LO_DISABLE BIT(1) 735 #define PWRON_DISABLE BIT(2) 736 #define PWRON_LP_DISABLE BIT(3) 737 #define HOTDIE_DISABLE BIT(4) 738 #define RTC_ALARM_DISABLE BIT(5) 739 #define RTC_PERIOD_DISABLE BIT(6) 740 #define USB_OV_INT_DISABLE BIT(7) 741 742 #define VOUT_LO_ENABLE (0 << 0) 743 #define VB_LO_ENABLE (0 << 1) 744 #define PWRON_ENABLE (0 << 2) 745 #define PWRON_LP_ENABLE (0 << 3) 746 #define HOTDIE_ENABLE (0 << 4) 747 #define RTC_ALARM_ENABLE (0 << 5) 748 #define RTC_PERIOD_ENABLE (0 << 6) 749 #define USB_OV_INT_ENABLE (0 << 7) 750 751 #define PLUG_IN_MASK BIT(0) 752 #define PLUG_OUT_MASK BIT(1) 753 #define CHGOK_MASK BIT(2) 754 #define CHGTE_MASK BIT(3) 755 #define CHGTS1_MASK BIT(4) 756 #define TS2_MASK BIT(5) 757 #define CHG_CVTLIM_MASK BIT(6) 758 #define DISCHG_ILIM_MASK BIT(7) 759 760 #define PLUG_IN_DISABLE BIT(0) 761 #define PLUG_OUT_DISABLE BIT(1) 762 #define CHGOK_DISABLE BIT(2) 763 #define CHGTE_DISABLE BIT(3) 764 #define CHGTS1_DISABLE BIT(4) 765 #define TS2_DISABLE BIT(5) 766 #define CHG_CVTLIM_DISABLE BIT(6) 767 #define DISCHG_ILIM_DISABLE BIT(7) 768 769 #define PLUG_IN_ENABLE BIT(0) 770 #define PLUG_OUT_ENABLE BIT(1) 771 #define CHGOK_ENABLE BIT(2) 772 #define CHGTE_ENABLE BIT(3) 773 #define CHGTS1_ENABLE BIT(4) 774 #define TS2_ENABLE BIT(5) 775 #define CHG_CVTLIM_ENABLE BIT(6) 776 #define DISCHG_ILIM_ENABLE BIT(7) 777 778 #define RK808_VBAT_LOW_2V8 0x00 779 #define RK808_VBAT_LOW_2V9 0x01 780 #define RK808_VBAT_LOW_3V0 0x02 781 #define RK808_VBAT_LOW_3V1 0x03 782 #define RK808_VBAT_LOW_3V2 0x04 783 #define RK808_VBAT_LOW_3V3 0x05 784 #define RK808_VBAT_LOW_3V4 0x06 785 #define RK808_VBAT_LOW_3V5 0x07 786 #define VBAT_LOW_VOL_MASK (0x07 << 0) 787 #define EN_VABT_LOW_SHUT_DOWN (0x00 << 4) 788 #define EN_VBAT_LOW_IRQ (0x1 << 4) 789 #define VBAT_LOW_ACT_MASK (0x1 << 4) 790 791 #define BUCK_ILMIN_MASK (7 << 0) 792 #define BOOST_ILMIN_MASK (7 << 0) 793 #define BUCK1_RATE_MASK (3 << 3) 794 #define BUCK2_RATE_MASK (3 << 3) 795 #define MASK_ALL 0xff 796 797 #define BUCK_UV_ACT_MASK 0x0f 798 #define BUCK_UV_ACT_DISABLE 0 799 800 #define SWITCH2_EN BIT(6) 801 #define SWITCH1_EN BIT(5) 802 #define DEV_OFF_RST BIT(3) 803 #define DEV_OFF BIT(0) 804 #define RTC_STOP BIT(0) 805 806 #define VB_LO_ACT BIT(4) 807 #define VB_LO_SEL_3500MV (7 << 0) 808 809 #define VOUT_LO_INT BIT(0) 810 #define CLK32KOUT2_EN BIT(0) 811 #define CLK32KOUT2_FUNC (0 << 1) 812 #define CLK32KOUT2_FUNC_MASK BIT(1) 813 814 #define TEMP105C 0x08 815 #define TEMP115C 0x0c 816 #define TEMP_HOTDIE_MSK 0x0c 817 #define SLP_SD_MSK (0x3 << 2) 818 #define SHUTDOWN_FUN (0x2 << 2) 819 #define SLEEP_FUN (0x1 << 2) 820 #define RK8XX_ID_MSK 0xfff0 821 #define PWM_MODE_MSK BIT(7) 822 #define FPWM_MODE BIT(7) 823 #define AUTO_PWM_MODE 0 824 #define REGS_WMSK 0xf0 825 826 enum rk817_reg_id { 827 RK817_ID_DCDC1 = 0, 828 RK817_ID_DCDC2, 829 RK817_ID_DCDC3, 830 RK817_ID_DCDC4, 831 RK817_ID_LDO1, 832 RK817_ID_LDO2, 833 RK817_ID_LDO3, 834 RK817_ID_LDO4, 835 RK817_ID_LDO5, 836 RK817_ID_LDO6, 837 RK817_ID_LDO7, 838 RK817_ID_LDO8, 839 RK817_ID_LDO9, 840 RK817_ID_BOOST, 841 RK817_ID_BOOST_OTG_SW, 842 RK817_NUM_REGULATORS 843 }; 844 845 enum rk809_reg_id { 846 RK809_ID_DCDC5 = RK817_ID_BOOST, 847 RK809_ID_SW1, 848 RK809_ID_SW2, 849 RK809_NUM_REGULATORS 850 }; 851 852 #define RK817_SECONDS_REG 0x00 853 #define RK817_MINUTES_REG 0x01 854 #define RK817_HOURS_REG 0x02 855 #define RK817_DAYS_REG 0x03 856 #define RK817_MONTHS_REG 0x04 857 #define RK817_YEARS_REG 0x05 858 #define RK817_WEEKS_REG 0x06 859 #define RK817_ALARM_SECONDS_REG 0x07 860 #define RK817_ALARM_MINUTES_REG 0x08 861 #define RK817_ALARM_HOURS_REG 0x09 862 #define RK817_ALARM_DAYS_REG 0x0a 863 #define RK817_ALARM_MONTHS_REG 0x0b 864 #define RK817_ALARM_YEARS_REG 0x0c 865 #define RK817_RTC_CTRL_REG 0xd 866 #define RK817_RTC_STATUS_REG 0xe 867 #define RK817_RTC_INT_REG 0xf 868 #define RK817_RTC_COMP_LSB_REG 0x10 869 #define RK817_RTC_COMP_MSB_REG 0x11 870 #define RK817_ADC_CONFIG0 0x50 871 #define RK817_CURE_ADC_K0 0xb0 872 #define RK817_POWER_EN_SAVE0 0x99 873 #define RK817_POWER_EN_SAVE1 0xa4 874 875 #define RK817_POWER_EN_REG(i) (0xb1 + (i)) 876 #define RK817_POWER_SLP_EN_REG(i) (0xb5 + (i)) 877 878 #define RK817_POWER_CONFIG (0xb9) 879 880 #define RK817_BUCK_CONFIG_REG(i) (0xba + (i) * 3) 881 882 #define RK817_BUCK1_ON_VSEL_REG 0xBB 883 #define RK817_BUCK1_SLP_VSEL_REG 0xBC 884 885 #define RK817_BUCK2_CONFIG_REG 0xBD 886 #define RK817_BUCK2_ON_VSEL_REG 0xBE 887 #define RK817_BUCK2_SLP_VSEL_REG 0xBF 888 889 #define RK817_BUCK3_CONFIG_REG 0xC0 890 #define RK817_BUCK3_ON_VSEL_REG 0xC1 891 #define RK817_BUCK3_SLP_VSEL_REG 0xC2 892 893 #define RK817_BUCK4_CONFIG_REG 0xC3 894 #define RK817_BUCK4_ON_VSEL_REG 0xC4 895 #define RK817_BUCK4_SLP_VSEL_REG 0xC5 896 897 #define RK817_LDO_ON_VSEL_REG(idx) (0xcc + (idx) * 2) 898 #define RK817_BOOST_OTG_CFG (0xde) 899 900 #define RK817_CHRG_OUT 0xe4 901 #define RK817_CHRG_IN 0xe5 902 #define RK817_CHRG_STS 0xeb 903 #define RK817_ID_MSB 0xed 904 #define RK817_ID_LSB 0xee 905 906 #define RK817_SYS_STS 0xf0 907 #define RK817_SYS_CFG(i) (0xf1 + (i)) 908 909 #define RK817_ON_SOURCE_REG 0xf5 910 #define RK817_OFF_SOURCE_REG 0xf6 911 912 /* INTERRUPT REGISTER */ 913 #define RK817_INT_STS_REG0 0xf8 914 #define RK817_INT_STS_MSK_REG0 0xf9 915 #define RK817_INT_STS_REG1 0xfa 916 #define RK817_INT_STS_MSK_REG1 0xfb 917 #define RK817_INT_STS_REG2 0xfc 918 #define RK817_INT_STS_MSK_REG2 0xfd 919 #define RK817_GPIO_INT_CFG 0xfe 920 921 /* IRQ Definitions */ 922 #define RK817_IRQ_PWRON_FALL 0 923 #define RK817_IRQ_PWRON_RISE 1 924 #define RK817_IRQ_PWRON 2 925 #define RK817_IRQ_PWMON_LP 3 926 #define RK817_IRQ_HOTDIE 4 927 #define RK817_IRQ_RTC_ALARM 5 928 #define RK817_IRQ_RTC_PERIOD 6 929 #define RK817_IRQ_VB_LO 7 930 #define RK817_IRQ_PLUG_IN 8 931 #define RK817_IRQ_PLUG_OUT 9 932 #define RK817_IRQ_CHRG_TERM 10 933 #define RK817_IRQ_CHRG_TIME 11 934 #define RK817_IRQ_CHRG_TS 12 935 #define RK817_IRQ_USB_OV 13 936 #define RK817_IRQ_CHRG_IN_CLMP 14 937 #define RK817_IRQ_BAT_DIS_ILIM 15 938 #define RK817_IRQ_GATE_GPIO 16 939 #define RK817_IRQ_TS_GPIO 17 940 #define RK817_IRQ_CODEC_PD 18 941 #define RK817_IRQ_CODEC_PO 19 942 #define RK817_IRQ_CLASSD_MUTE_DONE 20 943 #define RK817_IRQ_CLASSD_OCP 21 944 #define RK817_IRQ_BAT_OVP 22 945 #define RK817_IRQ_CHRG_BAT_HI 23 946 #define RK817_IRQ_END (RK817_IRQ_CHRG_BAT_HI + 1) 947 948 /* 949 * rtc_ctrl 0xd 950 * same as 808, except bit4 951 */ 952 #define RK817_RTC_CTRL_RSV4 BIT(4) 953 954 /* power config 0xb9 */ 955 #define RK817_BUCK3_FB_RES_MSK BIT(6) 956 #define RK817_BUCK3_FB_RES_INTER BIT(6) 957 #define RK817_BUCK3_FB_RES_EXT 0 958 959 /* buck config 0xba */ 960 #define RK817_RAMP_RATE_OFFSET 6 961 #define RK817_RAMP_RATE_MASK (0x3 << RK817_RAMP_RATE_OFFSET) 962 #define RK817_RAMP_RATE_3MV_PER_US (0x0 << RK817_RAMP_RATE_OFFSET) 963 #define RK817_RAMP_RATE_6_3MV_PER_US (0x1 << RK817_RAMP_RATE_OFFSET) 964 #define RK817_RAMP_RATE_12_5MV_PER_US (0x2 << RK817_RAMP_RATE_OFFSET) 965 #define RK817_RAMP_RATE_25MV_PER_US (0x3 << RK817_RAMP_RATE_OFFSET) 966 967 /* sys_cfg1 0xf2 */ 968 #define RK817_HOTDIE_TEMP_MSK (0x3 << 4) 969 #define RK817_HOTDIE_85 (0x0 << 4) 970 #define RK817_HOTDIE_95 (0x1 << 4) 971 #define RK817_HOTDIE_105 (0x2 << 4) 972 #define RK817_HOTDIE_115 (0x3 << 4) 973 974 #define RK817_TSD_TEMP_MSK BIT(6) 975 #define RK817_TSD_140 0 976 #define RK817_TSD_160 BIT(6) 977 978 #define RK817_CLK32KOUT2_EN BIT(7) 979 980 /* sys_cfg3 0xf4 */ 981 #define RK817_SLPPIN_FUNC_MSK (0x3 << 3) 982 #define SLPPIN_NULL_FUN (0x0 << 3) 983 #define SLPPIN_SLP_FUN (0x1 << 3) 984 #define SLPPIN_DN_FUN (0x2 << 3) 985 #define SLPPIN_RST_FUN (0x3 << 3) 986 987 #define RK817_RST_FUNC_MSK (0x3 << 6) 988 #define RK817_RST_FUNC_SFT (6) 989 #define RK817_RST_FUNC_CNT (3) 990 #define RK817_RST_FUNC_DEV (0) /* reset the dev */ 991 #define RK817_RST_FUNC_REG (0x1 << 6) /* reset the reg only */ 992 993 #define RK817_SLPPOL_MSK BIT(5) 994 #define RK817_SLPPOL_H BIT(5) 995 #define RK817_SLPPOL_L (0) 996 997 /* gpio&int 0xfe */ 998 #define RK817_INT_POL_MSK BIT(1) 999 #define RK817_INT_POL_H BIT(1) 1000 #define RK817_INT_POL_L 0 1001 #define RK809_BUCK5_CONFIG(i) (RK817_BOOST_OTG_CFG + (i) * 1) 1002 1003 enum { 1004 BUCK_ILMIN_50MA, 1005 BUCK_ILMIN_100MA, 1006 BUCK_ILMIN_150MA, 1007 BUCK_ILMIN_200MA, 1008 BUCK_ILMIN_250MA, 1009 BUCK_ILMIN_300MA, 1010 BUCK_ILMIN_350MA, 1011 BUCK_ILMIN_400MA, 1012 }; 1013 1014 enum { 1015 BOOST_ILMIN_75MA, 1016 BOOST_ILMIN_100MA, 1017 BOOST_ILMIN_125MA, 1018 BOOST_ILMIN_150MA, 1019 BOOST_ILMIN_175MA, 1020 BOOST_ILMIN_200MA, 1021 BOOST_ILMIN_225MA, 1022 BOOST_ILMIN_250MA, 1023 }; 1024 1025 enum { 1026 RK805_BUCK1_2_ILMAX_2500MA, 1027 RK805_BUCK1_2_ILMAX_3000MA, 1028 RK805_BUCK1_2_ILMAX_3500MA, 1029 RK805_BUCK1_2_ILMAX_4000MA, 1030 }; 1031 1032 enum { 1033 RK805_BUCK3_ILMAX_1500MA, 1034 RK805_BUCK3_ILMAX_2000MA, 1035 RK805_BUCK3_ILMAX_2500MA, 1036 RK805_BUCK3_ILMAX_3000MA, 1037 }; 1038 1039 enum { 1040 RK805_BUCK4_ILMAX_2000MA, 1041 RK805_BUCK4_ILMAX_2500MA, 1042 RK805_BUCK4_ILMAX_3000MA, 1043 RK805_BUCK4_ILMAX_3500MA, 1044 }; 1045 1046 enum { 1047 RK805_ID = 0x8050, 1048 RK808_ID = 0x0000, 1049 RK809_ID = 0x8090, 1050 RK816_ID = 0x8160, 1051 RK817_ID = 0x8170, 1052 RK818_ID = 0x8180, 1053 }; 1054 1055 struct rk808_pin_info { 1056 struct pinctrl *p; 1057 struct pinctrl_state *reset; 1058 struct pinctrl_state *power_off; 1059 struct pinctrl_state *sleep; 1060 }; 1061 1062 struct rk808 { 1063 struct i2c_client *i2c; 1064 struct regmap_irq_chip_data *irq_data; 1065 struct regmap_irq_chip_data *battery_irq_data; 1066 struct regmap *regmap; 1067 long variant; 1068 const struct regmap_config *regmap_cfg; 1069 const struct regmap_irq_chip *regmap_irq_chip; 1070 void (*pm_pwroff_prep_fn)(void); 1071 struct rk808_pin_info *pins; 1072 }; 1073 #endif /* __LINUX_REGULATOR_RK808_H */ 1074