xref: /OK3568_Linux_fs/kernel/drivers/misc/rk628/rk628_gvi.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
4  *
5  * Author: Guochun Huang <hero.huang@rock-chips.com>
6  */
7 
8 #ifndef RK628_GVI_H
9 #define RK628_GVI_H
10 
11 #include "rk628.h"
12 
13 #define GVI_BASE					0x80000
14 #define HOSTREG(x)					((x) + GVI_BASE)
15 #define GVI_SYS_CTRL0					HOSTREG(0x0000)
16 #define GVI_SYS_CTRL1					HOSTREG(0x0004)
17 #define GVI_SYS_CTRL2					HOSTREG(0x0008)
18 #define GVI_SYS_CTRL3					HOSTREG(0x000c)
19 #define GVI_VERSION					HOSTREG(0x0010)
20 #define GVI_SYS_RST					HOSTREG(0x0014)
21 #define GVI_LINE_FLAG					HOSTREG(0x0018)
22 #define GVI_STATUS					HOSTREG(0x001c)
23 #define GVI_PLL_LOCK_TIMEOUT				HOSTREG(0x0030)
24 #define GVI_HTPDN_TIMEOUT				HOSTREG(0x0034)
25 #define GVI_LOCKN_TIMEOUT				HOSTREG(0x0038)
26 #define GVI_WAIT_LOCKN					HOSTREG(0x003C)
27 #define GVI_WAIT_HTPDN					HOSTREG(0x0040)
28 #define GVI_INTR_EN					HOSTREG(0x0050)
29 #define GVI_INTR_CLR					HOSTREG(0x0054)
30 #define GVI_INTR_RAW_STATUS				HOSTREG(0x0058)
31 #define GVI_INTR_STATUS					HOSTREG(0x005c)
32 #define GVI_COLOR_BAR_CTRL				HOSTREG(0x0060)
33 #define GVI_COLOR_BAR_HTIMING0				HOSTREG(0x0070)
34 #define GVI_COLOR_BAR_HTIMING1				HOSTREG(0x0074)
35 #define GVI_COLOR_BAR_VTIMING0				HOSTREG(0x0078)
36 #define GVI_COLOR_BAR_VTIMING1				HOSTREG(0x007c)
37 
38 /* SYS_CTRL0 */
39 #define SYS_CTRL0_GVI_EN				BIT(0)
40 #define SYS_CTRL0_AUTO_GATING				BIT(1)
41 #define SYS_CTRL0_FRM_RST_EN				BIT(2)
42 #define SYS_CTRL0_FRM_RST_MODE				BIT(3)
43 #define SYS_CTRL0_LANE_NUM_MASK				GENMASK(7, 4)
44 #define SYS_CTRL0_LANE_NUM(x)				UPDATE(x, 7, 4)
45 #define SYS_CTRL0_BYTE_MODE_MASK			GENMASK(9, 8)
46 #define SYS_CTRL0_BYTE_MODE(x)				UPDATE(x, 9, 8)
47 #define SYS_CTRL0_SECTION_NUM_MASK			GENMASK(11, 10)
48 #define SYS_CTRL0_SECTION_NUM(x)			UPDATE(x, 11, 10)
49 #define SYS_CTRL0_CDR_ENDIAN_SWAP			BIT(12)
50 #define SYS_CTRL0_PACK_BYTE_SWAP			BIT(13)
51 #define SYS_CTRL0_PACK_ENDIAN_SWAP			BIT(14)
52 #define SYS_CTRL0_ENC8B10B_ENDIAN_SWAP			BIT(15)
53 #define SYS_CTRL0_CDR_EN				BIT(16)
54 #define SYS_CTRL0_ALN_EN				BIT(17)
55 #define SYS_CTRL0_NOR_EN				BIT(18)
56 #define SYS_CTRL0_ALN_NOR_MODE				BIT(19)
57 #define SYS_CTRL0_GVI_MASK				GENMASK(19, 16)
58 #define SYS_CTRL0_GVI_GN_EN(x)				UPDATE(x, 19, 16)
59 
60 #define SYS_CTRL0_SCRAMBLER_EN				BIT(20)
61 #define SYS_CTRL0_ENCODE8B10B_EN			BIT(21)
62 #define SYS_CTRL0_INIT_RD_EN				BIT(22)
63 #define SYS_CTRL0_INIT_RD_VALUE				BIT(23)
64 #define SYS_CTRL0_FORCE_HTPDN_EN			BIT(24)
65 #define SYS_CTRL0_FORCE_HTPDN_VALUE			BIT(25)
66 #define SYS_CTRL0_FORCE_PLL_EN				BIT(26)
67 #define SYS_CTRL0_FORCE_PLL_VALUE			BIT(27)
68 #define SYS_CTRL0_FORCE_LOCKN_EN			BIT(28)
69 #define SYS_CTRL0_FORCE_LOCKN_VALUE			BIT(29)
70 
71 /* SYS_CTRL1 */
72 #define SYS_CTRL1_COLOR_DEPTH_MASK			GENMASK(3, 0)
73 #define SYS_CTRL1_COLOR_DEPTH(x)			UPDATE(x, 3, 0)
74 #define SYS_CTRL1_DUAL_PIXEL_EN				BIT(4)
75 #define SYS_CTRL1_TIMING_ALIGN_EN			BIT(8)
76 #define SYS_CTRL1_LANE_ALIGN_EN				BIT(9)
77 
78 #define SYS_CTRL1_DUAL_PIXEL_SWAP			BIT(12)
79 #define SYS_CTRL1_RB_SWAP				BIT(13)
80 #define SYS_CTRL1_YC_SWAP				BIT(14)
81 #define SYS_CTRL1_WHOLE_FRM_EN				BIT(16)
82 #define SYS_CTRL1_NOR_PROTECT				BIT(17)
83 #define SYS_CTRL1_RD_WCNT_UPDATE			BIT(31)
84 
85 /* SYS_CTRL2 */
86 #define SYS_CTRL2_AFIFO_READ_THOLD_MASK			GENMASK(7, 0)
87 #define SYS_CTRL2_AFIFO_READ_THOLD(x)			UPDATE(x, 7, 0)
88 #define SYS_CTRL2_AFIFO_ALMOST_FULL_THOLD_MASK		GENMASK(23, 16)
89 #define SYS_CTRL2_AFIFO_ALMOST_FULL_THOLD(x)		UPDATE(x, 23, 16)
90 #define SYS_CTRL2_AFIFO_ALMOST_EMPTY_THOLD_MASK		GENMASK(31, 24)
91 #define SYS_CTRL2_AFIFO_ALMOST_EMPTY_THOLD(x)		UPDATE(x, 31, 24)
92 
93 /* SYS_CTRL3 */
94 #define SYS_CTRL3_LANE0_SEL_MASK			GENMASK(2, 0)
95 #define SYS_CTRL3_LANE0_SEL(x)				UPDATE(x, 2, 0)
96 #define SYS_CTRL3_LANE1_SEL_MASK			GENMASK(6, 4)
97 #define SYS_CTRL3_LANE1_SEL(x)				UPDATE(x, 6, 4)
98 #define SYS_CTRL3_LANE2_SEL_MASK			GENMASK(10, 8)
99 #define SYS_CTRL3_LANE2_SEL(x)				UPDATE(x, 10, 8)
100 #define SYS_CTRL3_LANE3_SEL_MASK			GENMASK(14, 12)
101 #define SYS_CTRL3_LANE3_SEL(x)				UPDATE(x, 14, 12)
102 #define SYS_CTRL3_LANE4_SEL_MASK			GENMASK(18, 16)
103 #define SYS_CTRL3_LANE4_SEL(x)				UPDATE(x, 18, 16)
104 #define SYS_CTRL3_LANE5_SEL_MASK			GENMASK(22, 20)
105 #define SYS_CTRL3_LANE5_SEL(x)				UPDATE(x, 22, 20)
106 #define SYS_CTRL3_LANE6_SEL_MASK			GENMASK(26, 24)
107 #define SYS_CTRL3_LANE6_SEL(x)				UPDATE(x, 26, 24)
108 #define SYS_CTRL3_LANE7_SEL_MASK			GENMASK(30, 28)
109 #define SYS_CTRL3_LANE7_SEL(x)				UPDATE(x, 30, 28)
110 /* VERSIION */
111 #define VERSION_VERSION(x)				UPDATE(x, 31, 0)
112 /* SYS_RESET*/
113 #define SYS_RST_SOFT_RST				BIT(0)
114 /* LINE_FLAG */
115 #define LINE_FLAG_LANE_FLAG0_MASK			GENMASK(15, 0)
116 #define LINE_FLAG_LANE_FLAG0(x)				UPDATE(x, 15, 0)
117 #define LINE_FLAG_LANE_FLAG1_MASK			GENMASK(31, 16)
118 #define LINE_FLAG_LANE_FLAG1(x)				UPDATE(x, 31, 16)
119 /* STATUS */
120 #define STATUS_HTDPN					BIT(4)
121 #define STATUS_LOCKN					BIT(5)
122 #define STATUS_PLL_LOCKN				BIT(6)
123 #define STATUS_AFIFO0_WCNT_MASK				GENMASK(23, 16)
124 #define STATUS_AFIFO0_WCNT(x)				UPDATE(x, 23, 16)
125 #define STATUS_AFIFO1_WCNT_MASK				GENMASK(31, 24)
126 #define STATUS_AFIFO1_WCNT(x)				UPDATE(x, 31, 24)
127 /* PLL_LTIMEOUT */
128 #define PLL_LOCK_TIMEOUT_PLL_LOCK_TIME_OUT_MASK		GENMASK(31, 0)
129 #define PLL_LOCK_TIMEOUT_PLL_LOCK_TIME_OUT(x)		UPDATE(x, 31, 0)
130 /* HTPDNEOUT */
131 #define HTPDN_TIMEOUT_HTPDN_TIME_OUT_MASK		GENMASK(31, 0)
132 #define HTPDN_TIMEOUT_HTPDN_TIME_OUT(x)			UPDATE(x, 31, 0)
133 /* LOCKNEOUT */
134 #define LOCKN_TIMEOUT_LOCKN_TIME_OUT_MASK		GENMASK(31, 0)
135 #define LOCKN_TIMEOUT_LOCKN_TIME_OUT(x)			UPDATE(x, 31, 0)
136 /* WAIT_LOCKN */
137 #define WAIT_LOCKN_WAIT_LOCKN_TIME_MASK			GENMASK(30, 0)
138 #define WAIT_LOCKN_WAIT_LOCKN_TIME(x)			UPDATE(x, 30, 0)
139 #define WAIT_LOCKN_WAIT_LOCKN_TIME_EN			BIT(31)
140 /* WAIT_HTPDN */
141 #define WAIT_HTPDN_WAIT_HTPDN_TIME_MASK			GENMASK(30, 0)
142 #define WAIT_HTPDN_WAIT_HTPDN_TIME(x)			UPDATE(x, 30, 0)
143 #define WAIT_HTPDN_WAIT_HTPDN_EN			BIT(31)
144 /* INTR_EN */
145 #define INTR_EN_INTR_FRM_ST_EN				BIT(0)
146 #define INTR_EN_INTR_PLL_LOCK_EN			BIT(1)
147 #define INTR_EN_INTR_HTPDN_EN				BIT(2)
148 #define INTR_EN_INTR_LOCKN_EN				BIT(3)
149 #define INTR_EN_INTR_PLL_TIMEOUT_EN			BIT(4)
150 #define INTR_EN_INTR_HTPDN_TIMEOUT_EN			BIT(5)
151 #define INTR_EN_INTR_LOCKN_TIMEOUT_EN			BIT(6)
152 #define INTR_EN_INTR_LINE_FLAG0_EN			BIT(8)
153 #define INTR_EN_INTR_LINE_FLAG1_EN			BIT(9)
154 #define INTR_EN_INTR_AFIFO_OVERFLOW_EN			BIT(10)
155 #define INTR_EN_INTR_AFIFO_UNDERFLOW_EN			BIT(11)
156 #define INTR_EN_INTR_PLL_ERR_EN				BIT(12)
157 #define INTR_EN_INTR_HTPDN_ERR_EN			BIT(13)
158 #define INTR_EN_INTR_LOCKN_ERR_EN			BIT(14)
159 /* INTR_CLR*/
160 #define INTR_CLR_INTR_FRM_ST_CLR			BIT(0)
161 #define INTR_CLR_INTR_PLL_LOCK_CLR			BIT(1)
162 #define INTR_CLR_INTR_HTPDN_CLR				BIT(2)
163 #define INTR_CLR_INTR_LOCKN_CLR				BIT(3)
164 #define INTR_CLR_INTR_PLL_TIMEOUT_CLR			BIT(4)
165 #define INTR_CLR_INTR_HTPDN_TIMEOUT_CLR			BIT(5)
166 #define INTR_CLR_INTR_LOCKN_TIMEOUT_CLR			BIT(6)
167 #define INTR_CLR_INTR_LINE_FLAG0_CLR			BIT(8)
168 #define INTR_CLR_INTR_LINE_FLAG1_CLR			BIT(9)
169 #define INTR_CLR_INTR_AFIFO_OVERFLOW_CLR		BIT(10)
170 #define INTR_CLR_INTR_AFIFO_UNDERFLOW_CLR		BIT(11)
171 #define INTR_CLR_INTR_PLL_ERR_CLR			BIT(12)
172 #define INTR_CLR_INTR_HTPDN_ERR_CLR			BIT(13)
173 #define INTR_CLR_INTR_LOCKN_ERR_CLR			BIT(14)
174 /* INTR_RAW_STATUS */
175 #define INTR_RAW_STATUS_RAW_INTR_FRM_ST			BIT(0)
176 #define INTR_RAW_STATUS_RAW_INTR_PLL_LOCK		BIT(1)
177 #define INTR_RAW_STATUS_RAW_INTR_HTPDN			BIT(2)
178 #define INTR_RAW_STATUS_RAW_INTR_LOCKN			BIT(3)
179 #define INTR_RAW_STATUS_RAW_INTR_PLL_TIMEOUT		BIT(4)
180 #define INTR_RAW_STATUS_RAW_INTR_HTPDN_TIMEOUT		BIT(5)
181 #define INTR_RAW_STATUS_RAW_INTR_LOCKN_TIMEOUT		BIT(6)
182 #define INTR_RAW_STATUS_RAW_INTR_LINE_FLAG0		BIT(8)
183 #define INTR_RAW_STATUS_RAW_INTR_LINE_FLAG1		BIT(9)
184 #define INTR_RAW_STATUS_RAW_INTR_AFIFO_OVERFLOW		BIT(10)
185 #define INTR_RAW_STATUS_RAW_INTR_AFIFO_UNDERFLOW	BIT(11)
186 #define INTR_RAW_STATUS_RAW_INTR_PLL_ERR		BIT(12)
187 #define INTR_RAW_STATUS_RAW_INTR_HTPDN_ERR		BIT(13)
188 #define INTR_RAW_STATUS_RAW_INTR_LOCKN_ERR		BIT(14)
189 /* INTR_STATUS */
190 #define INTR_STATUS_INTR_FRM_ST				BIT(0)
191 #define INTR_STATUS_INTR_PLL_LOCK			BIT(1)
192 #define INTR_STATUS_INTR_HTPDN				BIT(2)
193 #define INTR_STATUS_INTR_LOCKN				BIT(3)
194 #define INTR_STATUS_INTR_PLL_TIMEOUT			BIT(4)
195 #define INTR_STATUS_INTR_HTPDN_TIMEOUT			BIT(5)
196 #define INTR_STATUS_INTR_LOCKN_TIMEOUT			BIT(6)
197 #define INTR_STATUS_INTR_LINE_FLAG0			BIT(8)
198 #define INTR_STATUS_INTR_LINE_FLAG1			BIT(9)
199 #define INTR_STATUS_INTR_AFIFO_OVERFLOW			BIT(10)
200 #define INTR_STATUS_INTR_AFIFO_UNDERFLOW		BIT(11)
201 #define INTR_STATUS_INTR_PLL_ERR			BIT(12)
202 #define INTR_STATUS_INTR_HTPDN_ERR			BIT(13)
203 #define INTR_STATUS_INTR_LOCKN_ERR			BIT(14)
204 
205 /* COLOR_BAR_CTRL */
206 #define COLOR_BAR_EN					BIT(0)
207 
208 #define COLOR_DEPTH_RGB_YUV444_18BIT			0
209 #define COLOR_DEPTH_RGB_YUV444_24BIT			1
210 #define COLOR_DEPTH_RGB_YUV444_30BIT			2
211 #define COLOR_DEPTH_YUV422_16BIT			8
212 #define COLOR_DEPTH_YUV422_20BIT			9
213 
214 int rk628_gvi_parse(struct rk628 *rk628, struct device_node *gvi_np);
215 void rk628_gvi_enable(struct rk628 *rk628);
216 void rk628_gvi_disable(struct rk628 *rk628);
217 
218 #endif
219