1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4 * 5 * Author: Wyon Bi <bivvy.bi@rock-chips.com> 6 */ 7 8 #ifndef RK628_GPIO_H 9 #define RK628_GPIO_H 10 11 #define RK628_GPIO0_BASE 0x000D0000 12 #define RK628_GPIO1_BASE 0x000E0000 13 #define RK628_GPIO2_BASE 0x000F0000 14 #define RK628_GPIO3_BASE 0x00100000 15 #define RK628_GPIO_MAX_REGISTER (RK628_GPIO3_BASE + GPIO_VER_ID) 16 17 /* GPIO control registers */ 18 #define GPIO_SWPORT_DR_L 0x00 19 #define GPIO_SWPORT_DR_H 0x04 20 #define GPIO_SWPORT_DDR_L 0x08 21 #define GPIO_SWPORT_DDR_H 0x0c 22 #define GPIO_INTEN_L 0x10 23 #define GPIO_INTEN_H 0x14 24 #define GPIO_INTMASK_L 0x18 25 #define GPIO_INTMASK_H 0x1c 26 #define GPIO_INTTYPE_L 0x20 27 #define GPIO_INTTYPE_H 0x24 28 #define GPIO_INT_POLARITY_L 0x28 29 #define GPIO_INT_POLARITY_H 0x2c 30 #define GPIO_INT_BOTHEDGE_L 0x30 31 #define GPIO_INT_BOTHEDGE_H 0x34 32 #define GPIO_DEBOUNCE_L 0x38 33 #define GPIO_DEBOUNCE_H 0x3c 34 #define GPIO_DBCLK_DIV_EN_L 0x40 35 #define GPIO_DBCLK_DIV_EN_H 0x44 36 #define GPIO_INT_STATUS 0x50 37 #define GPIO_INT_RAWSTATUS 0x58 38 #define GPIO_PORTS_EOI_L 0x60 39 #define GPIO_PORTS_EOI_H 0x64 40 #define GPIO_EXT_PORT 0x70 41 #define GPIO_VER_ID 0x78 42 43 #define GPIO_REG_LOW 0x0 44 #define GPIO_REG_HIGH 0x1 45 46 /* GPIO control registers */ 47 #define GPIO_INTMASK 0x34 48 #define GPIO_PORTS_EOI 0x4c 49 50 #define BANK_OFFSET 32 51 52 #define GPIO_DIRECTION_OUT 1 53 #define GPIO_DIRECTION_IN 0 54 55 enum { 56 GPIO_HIGH_Z, 57 GPIO_PULL_UP, 58 GPIO_PULL_DOWN, 59 }; 60 61 enum { 62 GPIO_BANK0 = 0, 63 GPIO_BANK1, 64 GPIO_BANK2, 65 GPIO_BANK3, 66 GPIO_BANKX = 9, 67 }; 68 69 70 enum { 71 GPIO0_A0 = BANK_OFFSET * 0, 72 GPIO0_A1, 73 GPIO0_A2, 74 GPIO0_A3, 75 GPIO0_A4, 76 GPIO0_A5, 77 GPIO0_A6, 78 GPIO0_A7, 79 GPIO0_B0, 80 GPIO0_B1, 81 GPIO0_B2, 82 GPIO0_B3, 83 GPIO1_A0 = BANK_OFFSET * 1, 84 GPIO1_A1, 85 GPIO1_A2, 86 GPIO1_A3, 87 GPIO1_A4, 88 GPIO1_A5, 89 GPIO1_A6, 90 GPIO1_A7, 91 GPIO1_B0, 92 GPIO1_B1, 93 GPIO1_B2, 94 GPIO1_B3, 95 GPIO1_B4, 96 GPIO1_B5, 97 GPIO2_A0 = BANK_OFFSET * 2, 98 GPIO2_A1, 99 GPIO2_A2, 100 GPIO2_A3, 101 GPIO2_A4, 102 GPIO2_A5, 103 GPIO2_A6, 104 GPIO2_A7, 105 GPIO2_B0, 106 GPIO2_B1, 107 GPIO2_B2, 108 GPIO2_B3, 109 GPIO2_B4, 110 GPIO2_B5, 111 GPIO2_B6, 112 GPIO2_B7, 113 GPIO2_C0, 114 GPIO2_C1, 115 GPIO2_C2, 116 GPIO2_C3, 117 GPIO2_C4, 118 GPIO2_C5, 119 GPIO2_C6, 120 GPIO2_C7, 121 GPIO3_A0 = BANK_OFFSET * 3, 122 GPIO3_A1, 123 GPIO3_A2, 124 GPIO3_A3, 125 GPIO3_A4, 126 GPIO3_A5, 127 GPIO3_A6, 128 GPIO3_A7, 129 GPIO3_B0, 130 GPIO3_B1, 131 GPIO3_B2, 132 GPIO3_B3, 133 GPIO3_B4, 134 PIN_I2SM_SCK = BANK_OFFSET * 4 + 2, 135 PIN_I2SM_D, 136 PIN_I2SM_LR, 137 PIN_RXDDC_SCL, 138 PIN_RXDDC_SDA, 139 PIN_HDMIRX_CE, 140 PIN_JTAG_EN, 141 PIN_UART_SEL, 142 PIN_UART_RTS_EN, 143 PIN_UART_CTS_EN, 144 PIN_MUX, 145 }; 146 147 struct rk628_pin_iomux_group { 148 unsigned int pins; 149 int bank; 150 int mux; 151 int iomux_base; 152 int gpio_base; 153 int pull_reg; 154 }; 155 156 157 #define PINCTRL_GROUP(a, b, c, d, e, f) \ 158 {.pins = a, .bank = b, .mux = c, .iomux_base = d, .gpio_base = e, .pull_reg = f} 159 160 161 static const struct rk628_pin_iomux_group rk628_pin_iomux_groups[] = { 162 PINCTRL_GROUP(GPIO0_A0, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON, 163 RK628_GPIO0_BASE, GRF_GPIO0A_P_CON), 164 PINCTRL_GROUP(GPIO0_A1, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON, 165 RK628_GPIO0_BASE, GRF_GPIO0A_P_CON), 166 PINCTRL_GROUP(GPIO0_A2, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON, RK628_GPIO0_BASE, 0), 167 PINCTRL_GROUP(GPIO0_A3, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON, 168 RK628_GPIO0_BASE, GRF_GPIO0A_P_CON), 169 PINCTRL_GROUP(GPIO0_A4, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON, 170 RK628_GPIO0_BASE, GRF_GPIO0A_P_CON), 171 PINCTRL_GROUP(GPIO0_A5, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON, 172 RK628_GPIO0_BASE, GRF_GPIO0A_P_CON), 173 PINCTRL_GROUP(GPIO0_A6, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON, 174 RK628_GPIO0_BASE, GRF_GPIO0A_P_CON), 175 PINCTRL_GROUP(GPIO0_A7, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON, 176 RK628_GPIO0_BASE, GRF_GPIO0A_P_CON), 177 PINCTRL_GROUP(GPIO0_B0, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON, RK628_GPIO0_BASE, 0), 178 PINCTRL_GROUP(GPIO0_B1, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON, RK628_GPIO0_BASE, 0), 179 PINCTRL_GROUP(GPIO0_B2, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON, RK628_GPIO0_BASE, 0), 180 PINCTRL_GROUP(GPIO0_B3, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON, RK628_GPIO0_BASE, 0), 181 182 PINCTRL_GROUP(GPIO1_A0, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON, 183 RK628_GPIO1_BASE, GRF_GPIO1A_P_CON), 184 PINCTRL_GROUP(GPIO1_A1, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON, 185 RK628_GPIO1_BASE, GRF_GPIO1A_P_CON), 186 PINCTRL_GROUP(GPIO1_A2, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON, 187 RK628_GPIO1_BASE, GRF_GPIO1A_P_CON), 188 PINCTRL_GROUP(GPIO1_A3, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON, 189 RK628_GPIO1_BASE, GRF_GPIO1A_P_CON), 190 PINCTRL_GROUP(GPIO1_A4, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON, 191 RK628_GPIO1_BASE, GRF_GPIO1A_P_CON), 192 PINCTRL_GROUP(GPIO1_A5, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON, 193 RK628_GPIO1_BASE, GRF_GPIO1A_P_CON), 194 PINCTRL_GROUP(GPIO1_A6, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON, 195 RK628_GPIO1_BASE, GRF_GPIO1A_P_CON), 196 PINCTRL_GROUP(GPIO1_A7, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON, 197 RK628_GPIO1_BASE, GRF_GPIO1A_P_CON), 198 PINCTRL_GROUP(GPIO1_B0, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON, RK628_GPIO1_BASE, 0), 199 PINCTRL_GROUP(GPIO1_B1, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON, RK628_GPIO1_BASE, 0), 200 PINCTRL_GROUP(GPIO1_B2, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON, RK628_GPIO1_BASE, 0), 201 PINCTRL_GROUP(GPIO1_B3, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON, RK628_GPIO1_BASE, 0), 202 PINCTRL_GROUP(GPIO1_B4, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON, RK628_GPIO1_BASE, 0), 203 PINCTRL_GROUP(GPIO1_B5, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON, RK628_GPIO1_BASE, 0), 204 205 PINCTRL_GROUP(GPIO2_A0, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON, 206 RK628_GPIO2_BASE, GRF_GPIO2A_P_CON), 207 PINCTRL_GROUP(GPIO2_A1, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON, 208 RK628_GPIO2_BASE, GRF_GPIO2A_P_CON), 209 PINCTRL_GROUP(GPIO2_A2, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON, 210 RK628_GPIO2_BASE, GRF_GPIO2A_P_CON), 211 PINCTRL_GROUP(GPIO2_A3, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON, 212 RK628_GPIO2_BASE, GRF_GPIO2A_P_CON), 213 PINCTRL_GROUP(GPIO2_A4, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON, 214 RK628_GPIO2_BASE, GRF_GPIO2A_P_CON), 215 PINCTRL_GROUP(GPIO2_A5, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON, 216 RK628_GPIO2_BASE, GRF_GPIO2A_P_CON), 217 PINCTRL_GROUP(GPIO2_A6, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON, 218 RK628_GPIO2_BASE, GRF_GPIO2A_P_CON), 219 PINCTRL_GROUP(GPIO2_A7, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON, 220 RK628_GPIO2_BASE, GRF_GPIO2A_P_CON), 221 PINCTRL_GROUP(GPIO2_B0, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON, 222 RK628_GPIO2_BASE, GRF_GPIO2B_P_CON), 223 PINCTRL_GROUP(GPIO2_B1, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON, 224 RK628_GPIO2_BASE, GRF_GPIO2B_P_CON), 225 PINCTRL_GROUP(GPIO2_B2, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON, 226 RK628_GPIO2_BASE, GRF_GPIO2B_P_CON), 227 PINCTRL_GROUP(GPIO2_B3, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON, 228 RK628_GPIO2_BASE, GRF_GPIO2B_P_CON), 229 PINCTRL_GROUP(GPIO2_B4, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON, 230 RK628_GPIO2_BASE, GRF_GPIO2B_P_CON), 231 PINCTRL_GROUP(GPIO2_B5, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON, 232 RK628_GPIO2_BASE, GRF_GPIO2B_P_CON), 233 PINCTRL_GROUP(GPIO2_B6, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON, 234 RK628_GPIO2_BASE, GRF_GPIO2B_P_CON), 235 PINCTRL_GROUP(GPIO2_B7, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON, 236 RK628_GPIO2_BASE, GRF_GPIO2B_P_CON), 237 PINCTRL_GROUP(GPIO2_C0, GPIO_BANK2, 1, GRF_GPIO2C_SEL_CON, 238 RK628_GPIO2_BASE, GRF_GPIO2C_P_CON), 239 PINCTRL_GROUP(GPIO2_C1, GPIO_BANK2, 1, GRF_GPIO2C_SEL_CON, 240 RK628_GPIO2_BASE, GRF_GPIO2C_P_CON), 241 PINCTRL_GROUP(GPIO2_C2, GPIO_BANK2, 1, GRF_GPIO2C_SEL_CON, 242 RK628_GPIO2_BASE, GRF_GPIO2C_P_CON), 243 PINCTRL_GROUP(GPIO2_C3, GPIO_BANK2, 1, GRF_GPIO2C_SEL_CON, 244 RK628_GPIO2_BASE, GRF_GPIO2C_P_CON), 245 PINCTRL_GROUP(GPIO2_C4, GPIO_BANK2, 1, GRF_GPIO2C_SEL_CON, 246 RK628_GPIO2_BASE, GRF_GPIO2C_P_CON), 247 PINCTRL_GROUP(GPIO2_C5, GPIO_BANK2, 1, GRF_GPIO2C_SEL_CON, 248 RK628_GPIO2_BASE, GRF_GPIO2C_P_CON), 249 PINCTRL_GROUP(GPIO2_C6, GPIO_BANK2, 1, GRF_GPIO2C_SEL_CON, 250 RK628_GPIO2_BASE, GRF_GPIO2C_P_CON), 251 PINCTRL_GROUP(GPIO2_C7, GPIO_BANK2, 1, GRF_GPIO2C_SEL_CON, 252 RK628_GPIO2_BASE, GRF_GPIO2C_P_CON), 253 254 PINCTRL_GROUP(GPIO3_A0, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON, 255 RK628_GPIO3_BASE, GRF_GPIO3A_P_CON), 256 PINCTRL_GROUP(GPIO3_A1, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON, 257 RK628_GPIO3_BASE, GRF_GPIO3A_P_CON), 258 PINCTRL_GROUP(GPIO3_A2, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON, 259 RK628_GPIO3_BASE, GRF_GPIO3A_P_CON), 260 PINCTRL_GROUP(GPIO3_A3, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON, 261 RK628_GPIO3_BASE, GRF_GPIO3A_P_CON), 262 PINCTRL_GROUP(GPIO3_A4, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON, 263 RK628_GPIO3_BASE, 0), 264 PINCTRL_GROUP(GPIO3_A5, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON, 265 RK628_GPIO3_BASE, 0), 266 PINCTRL_GROUP(GPIO3_A6, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON, 267 RK628_GPIO3_BASE, 0), 268 PINCTRL_GROUP(GPIO3_A7, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON, 269 RK628_GPIO3_BASE, 0), 270 PINCTRL_GROUP(GPIO3_B0, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON, 271 RK628_GPIO3_BASE, GRF_GPIO3B_P_CON), 272 PINCTRL_GROUP(GPIO3_B1, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON, 273 RK628_GPIO3_BASE, GRF_GPIO3B_P_CON), 274 PINCTRL_GROUP(GPIO3_B2, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON, 275 RK628_GPIO3_BASE, GRF_GPIO3B_P_CON), 276 PINCTRL_GROUP(GPIO3_B3, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON, 277 RK628_GPIO3_BASE, GRF_GPIO3B_P_CON), 278 PINCTRL_GROUP(GPIO3_B4, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON, 279 RK628_GPIO3_BASE, GRF_GPIO3B_P_CON), 280 281 PINCTRL_GROUP(PIN_I2SM_SCK, GPIO_BANKX, 1, GRF_SYSTEM_CON3, 0, 0), 282 PINCTRL_GROUP(PIN_I2SM_D, GPIO_BANKX, 1, GRF_SYSTEM_CON3, 0, 0), 283 PINCTRL_GROUP(PIN_I2SM_LR, GPIO_BANKX, 1, GRF_SYSTEM_CON3, 0, 0), 284 PINCTRL_GROUP(PIN_RXDDC_SCL, GPIO_BANKX, 1, GRF_SYSTEM_CON3, 0, 0), 285 PINCTRL_GROUP(PIN_RXDDC_SDA, GPIO_BANKX, 1, GRF_SYSTEM_CON3, 0, 0), 286 PINCTRL_GROUP(PIN_HDMIRX_CE, GPIO_BANKX, 1, GRF_SYSTEM_CON3, 0, 0), 287 PINCTRL_GROUP(PIN_JTAG_EN, GPIO_BANKX, 1, GRF_SYSTEM_CON3, 0, 0), 288 PINCTRL_GROUP(PIN_UART_SEL, GPIO_BANKX, 1, GRF_SYSTEM_CON3, 0, 0), 289 PINCTRL_GROUP(PIN_UART_RTS_EN, GPIO_BANKX, 1, GRF_SYSTEM_CON3, 0, 0), 290 PINCTRL_GROUP(PIN_UART_CTS_EN, GPIO_BANKX, 1, GRF_SYSTEM_CON3, 0, 0), 291 292 }; 293 294 #endif // RK628_GPIO_H 295 296 297