1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7/ { 8 dsi2lvds_backlight1: dsi2lvds_backlight1 { 9 compatible = "pwm-backlight"; 10 brightness-levels = < 11 0 20 20 21 21 22 22 23 12 23 24 24 25 25 26 26 27 13 27 28 28 29 29 30 30 31 14 31 32 32 33 33 34 34 35 15 35 36 36 37 37 38 38 39 16 40 41 42 43 44 45 46 47 17 48 49 50 51 52 53 54 55 18 56 57 58 59 60 61 62 63 19 64 65 66 67 68 69 70 71 20 72 73 74 75 76 77 78 79 21 80 81 82 83 84 85 86 87 22 88 89 90 91 92 93 94 95 23 96 97 98 99 100 101 102 103 24 104 105 106 107 108 109 110 111 25 112 113 114 115 116 117 118 119 26 120 121 122 123 124 125 126 127 27 128 129 130 131 132 133 134 135 28 136 137 138 139 140 141 142 143 29 144 145 146 147 148 149 150 151 30 152 153 154 155 156 157 158 159 31 160 161 162 163 164 165 166 167 32 168 169 170 171 172 173 174 175 33 176 177 178 179 180 181 182 183 34 184 185 186 187 188 189 190 191 35 192 193 194 195 196 197 198 199 36 200 201 202 203 204 205 206 207 37 208 209 210 211 212 213 214 215 38 216 217 218 219 220 221 222 223 39 224 225 226 227 228 229 230 231 40 232 233 234 235 236 237 238 239 41 240 241 242 243 244 245 246 247 42 248 249 250 251 252 253 254 255 43 >; 44 default-brightness-level = <200>; 45 }; 46 47 dp2lvds_backlight0: dp2lvds_backlight0 { 48 compatible = "pwm-backlight"; 49 brightness-levels = < 50 0 20 20 21 21 22 22 23 51 23 24 24 25 25 26 26 27 52 27 28 28 29 29 30 30 31 53 31 32 32 33 33 34 34 35 54 35 36 36 37 37 38 38 39 55 40 41 42 43 44 45 46 47 56 48 49 50 51 52 53 54 55 57 56 57 58 59 60 61 62 63 58 64 65 66 67 68 69 70 71 59 72 73 74 75 76 77 78 79 60 80 81 82 83 84 85 86 87 61 88 89 90 91 92 93 94 95 62 96 97 98 99 100 101 102 103 63 104 105 106 107 108 109 110 111 64 112 113 114 115 116 117 118 119 65 120 121 122 123 124 125 126 127 66 128 129 130 131 132 133 134 135 67 136 137 138 139 140 141 142 143 68 144 145 146 147 148 149 150 151 69 152 153 154 155 156 157 158 159 70 160 161 162 163 164 165 166 167 71 168 169 170 171 172 173 174 175 72 176 177 178 179 180 181 182 183 73 184 185 186 187 188 189 190 191 74 192 193 194 195 196 197 198 199 75 200 201 202 203 204 205 206 207 76 208 209 210 211 212 213 214 215 77 216 217 218 219 220 221 222 223 78 224 225 226 227 228 229 230 231 79 232 233 234 235 236 237 238 239 80 240 241 242 243 244 245 246 247 81 248 249 250 251 252 253 254 255 82 >; 83 default-brightness-level = <200>; 84 }; 85 86 dp2lvds_backlight1: dp2lvds_backlight1 { 87 compatible = "pwm-backlight"; 88 brightness-levels = < 89 0 20 20 21 21 22 22 23 90 23 24 24 25 25 26 26 27 91 27 28 28 29 29 30 30 31 92 31 32 32 33 33 34 34 35 93 35 36 36 37 37 38 38 39 94 40 41 42 43 44 45 46 47 95 48 49 50 51 52 53 54 55 96 56 57 58 59 60 61 62 63 97 64 65 66 67 68 69 70 71 98 72 73 74 75 76 77 78 79 99 80 81 82 83 84 85 86 87 100 88 89 90 91 92 93 94 95 101 96 97 98 99 100 101 102 103 102 104 105 106 107 108 109 110 111 103 112 113 114 115 116 117 118 119 104 120 121 122 123 124 125 126 127 105 128 129 130 131 132 133 134 135 106 136 137 138 139 140 141 142 143 107 144 145 146 147 148 149 150 151 108 152 153 154 155 156 157 158 159 109 160 161 162 163 164 165 166 167 110 168 169 170 171 172 173 174 175 111 176 177 178 179 180 181 182 183 112 184 185 186 187 188 189 190 191 113 192 193 194 195 196 197 198 199 114 200 201 202 203 204 205 206 207 115 208 209 210 211 212 213 214 215 116 216 217 218 219 220 221 222 223 117 224 225 226 227 228 229 230 231 118 232 233 234 235 236 237 238 239 119 240 241 242 243 244 245 246 247 120 248 249 250 251 252 253 254 255 121 >; 122 default-brightness-level = <200>; 123 }; 124 125 edp2lvds_backlight0: edp2lvds_backlight0 { 126 compatible = "pwm-backlight"; 127 brightness-levels = < 128 0 20 20 21 21 22 22 23 129 23 24 24 25 25 26 26 27 130 27 28 28 29 29 30 30 31 131 31 32 32 33 33 34 34 35 132 35 36 36 37 37 38 38 39 133 40 41 42 43 44 45 46 47 134 48 49 50 51 52 53 54 55 135 56 57 58 59 60 61 62 63 136 64 65 66 67 68 69 70 71 137 72 73 74 75 76 77 78 79 138 80 81 82 83 84 85 86 87 139 88 89 90 91 92 93 94 95 140 96 97 98 99 100 101 102 103 141 104 105 106 107 108 109 110 111 142 112 113 114 115 116 117 118 119 143 120 121 122 123 124 125 126 127 144 128 129 130 131 132 133 134 135 145 136 137 138 139 140 141 142 143 146 144 145 146 147 148 149 150 151 147 152 153 154 155 156 157 158 159 148 160 161 162 163 164 165 166 167 149 168 169 170 171 172 173 174 175 150 176 177 178 179 180 181 182 183 151 184 185 186 187 188 189 190 191 152 192 193 194 195 196 197 198 199 153 200 201 202 203 204 205 206 207 154 208 209 210 211 212 213 214 215 155 216 217 218 219 220 221 222 223 156 224 225 226 227 228 229 230 231 157 232 233 234 235 236 237 238 239 158 240 241 242 243 244 245 246 247 159 248 249 250 251 252 253 254 255 160 >; 161 default-brightness-level = <200>; 162 }; 163 164 edp2lvds_backlight1: edp2lvds_backlight1 { 165 compatible = "pwm-backlight"; 166 brightness-levels = < 167 0 20 20 21 21 22 22 23 168 23 24 24 25 25 26 26 27 169 27 28 28 29 29 30 30 31 170 31 32 32 33 33 34 34 35 171 35 36 36 37 37 38 38 39 172 40 41 42 43 44 45 46 47 173 48 49 50 51 52 53 54 55 174 56 57 58 59 60 61 62 63 175 64 65 66 67 68 69 70 71 176 72 73 74 75 76 77 78 79 177 80 81 82 83 84 85 86 87 178 88 89 90 91 92 93 94 95 179 96 97 98 99 100 101 102 103 180 104 105 106 107 108 109 110 111 181 112 113 114 115 116 117 118 119 182 120 121 122 123 124 125 126 127 183 128 129 130 131 132 133 134 135 184 136 137 138 139 140 141 142 143 185 144 145 146 147 148 149 150 151 186 152 153 154 155 156 157 158 159 187 160 161 162 163 164 165 166 167 188 168 169 170 171 172 173 174 175 189 176 177 178 179 180 181 182 183 190 184 185 186 187 188 189 190 191 191 192 193 194 195 196 197 198 199 192 200 201 202 203 204 205 206 207 193 208 209 210 211 212 213 214 215 194 216 217 218 219 220 221 222 223 195 224 225 226 227 228 229 230 231 196 232 233 234 235 236 237 238 239 197 240 241 242 243 244 245 246 247 198 248 249 250 251 252 253 254 255 199 >; 200 default-brightness-level = <200>; 201 }; 202 203 dsi2lvds_panel0 { 204 compatible = "simple-panel"; 205 backlight = <&backlight>; 206 207 display-timings { 208 native-mode = <&dsi2lvds0>; 209 dsi2lvds0: timing0 { 210 clock-frequency = <115200000>;//115200000/105573600 211 hactive = <1920>; 212 vactive = <720>; 213 hfront-porch = <56>; 214 hsync-len = <32>; 215 hback-porch = <56>; 216 vfront-porch = <200>; 217 vsync-len = <2>; 218 vback-porch = <8>; 219 hsync-active = <0>; 220 vsync-active = <0>; 221 de-active = <0>; 222 pixelclk-active = <0>; 223 }; 224 }; 225 226 ports { 227 #address-cells = <1>; 228 #size-cells = <0>; 229 230 port@0 { 231 reg = <0>; 232 panel0_in_i2c2_bu18rl82: endpoint { 233 remote-endpoint = <&i2c2_bu18rl82_out_panel0>; 234 }; 235 }; 236 }; 237 }; 238 239 dsi2lvds_panel1 { 240 compatible = "simple-panel"; 241 backlight = <&dsi2lvds_backlight1>; 242 243 display-timings { 244 native-mode = <&dsi2lvds1>; 245 dsi2lvds1: timing0 { 246 clock-frequency = <115200000>; 247 hactive = <1920>; 248 vactive = <720>; 249 hfront-porch = <56>; 250 hsync-len = <32>; 251 hback-porch = <56>; 252 vfront-porch = <200>; 253 vsync-len = <2>; 254 vback-porch = <8>; 255 hsync-active = <0>; 256 vsync-active = <0>; 257 de-active = <0>; 258 pixelclk-active = <0>; 259 }; 260 }; 261 262 ports { 263 #address-cells = <1>; 264 #size-cells = <0>; 265 266 port@0 { 267 reg = <0>; 268 panel1_in_i2c6_bu18rl82: endpoint { 269 remote-endpoint = <&i2c6_bu18rl82_out_panel1>; 270 }; 271 }; 272 }; 273 }; 274 275 dp2lvds_panel0 { 276 compatible = "simple-panel"; 277 backlight = <&dp2lvds_backlight0>; 278 status = "okay"; 279 280 panel-timing { 281 clock-frequency = <115200000>; 282 hactive = <1920>; 283 vactive = <720>; 284 hfront-porch = <56>; 285 hsync-len = <32>; 286 hback-porch = <56>; 287 vfront-porch = <200>; 288 vsync-len = <2>; 289 vback-porch = <8>; 290 hsync-active = <0>; 291 vsync-active = <0>; 292 de-active = <0>; 293 pixelclk-active = <0>; 294 }; 295 296 port { 297 panel0_in_i2c4_bu18rl82: endpoint { 298 remote-endpoint = <&i2c4_bu18rl82_out_panel0>; 299 }; 300 }; 301 }; 302 303 dp2lvds_panel1 { 304 compatible = "simple-panel"; 305 backlight = <&dp2lvds_backlight1>; 306 status = "disabled"; 307 308 panel-timing { 309 clock-frequency = <148500000>; 310 hactive = <1920>; 311 vactive = <1080>; 312 hfront-porch = <140>; 313 hsync-len = <40>; 314 hback-porch = <100>; 315 vfront-porch = <15>; 316 vsync-len = <20>; 317 vback-porch = <10>; 318 hsync-active = <0>; 319 vsync-active = <0>; 320 de-active = <0>; 321 pixelclk-active = <0>; 322 }; 323 324 port { 325 panel1_in_i2c8_bu18rl82: endpoint { 326 remote-endpoint = <&i2c8_bu18rl82_out_panel1>; 327 }; 328 }; 329 }; 330 331 edp2lvds_panel0 { 332 compatible = "simple-panel"; 333 backlight = <&edp2lvds_backlight0>; 334 status = "okay"; 335 336 panel-timing { 337 clock-frequency = <148500000>; 338 hactive = <1920>; 339 vactive = <1080>; 340 hfront-porch = <140>; 341 hsync-len = <40>; 342 hback-porch = <100>; 343 vfront-porch = <15>; 344 vsync-len = <20>; 345 vback-porch = <10>; 346 hsync-active = <0>; 347 vsync-active = <0>; 348 de-active = <0>; 349 pixelclk-active = <0>; 350 }; 351 352 port { 353 panel0_in_i2c5_bu18rl82: endpoint { 354 remote-endpoint = <&i2c5_bu18rl82_out_panel0>; 355 }; 356 }; 357 }; 358 359 edp2lvds_panel1 { 360 compatible = "simple-panel"; 361 backlight = <&edp2lvds_backlight1>; 362 status = "disabled"; 363 364 panel-timing { 365 clock-frequency = <148500000>; 366 hactive = <1920>; 367 vactive = <1080>; 368 hfront-porch = <140>; 369 hsync-len = <40>; 370 hback-porch = <100>; 371 vfront-porch = <15>; 372 vsync-len = <20>; 373 vback-porch = <10>; 374 hsync-active = <0>; 375 vsync-active = <0>; 376 de-active = <0>; 377 pixelclk-active = <0>; 378 }; 379 380 port { 381 panel1_in_i2c7_bu18rl82: endpoint { 382 remote-endpoint = <&i2c7_bu18rl82_out_panel1>; 383 }; 384 }; 385 }; 386}; 387 388&backlight { 389 pwms = <&pwm0 0 25000 0>; 390 pinctrl-names = "default"; 391 pinctrl-0 = <&bl0_enable_pin>; 392 enable-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; 393 status = "okay"; 394}; 395 396&dsi2lvds_backlight1 { 397 pwms = <&pwm13 0 25000 0>; 398 pinctrl-names = "default"; 399 pinctrl-0 = <&bl1_enable_pin>; 400 enable-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; 401 status = "okay"; 402}; 403 404&dp0 { 405 //split-mode; 406 force-hpd; 407 status = "okay"; 408 409 ports { 410 port@1 { 411 reg = <1>; 412 413 dp0_out_i2c4_bu18tl82: endpoint { 414 remote-endpoint = <&i2c4_bu18tl82_in_dp0>; 415 }; 416 }; 417 }; 418}; 419 420&dp0_in_vp0 { 421 status = "okay"; 422}; 423 424&dp0_in_vp1 { 425 status = "disabled"; 426}; 427 428&dp0_in_vp2 { 429 status = "disabled"; 430}; 431 432&dp1 { 433 force-hpd; 434 status = "disabled"; 435 436 ports { 437 port@1 { 438 reg = <1>; 439 440 dp1_out_i2c8_bu18tl82: endpoint { 441 remote-endpoint = <&i2c8_bu18tl82_in_dp1>; 442 }; 443 }; 444 }; 445}; 446 447&dp1_in_vp0 { 448 status = "okay"; 449}; 450 451&dp1_in_vp1 { 452 status = "disabled"; 453}; 454 455&dp1_in_vp2 { 456 status = "disabled"; 457}; 458 459&dp2lvds_backlight0 { 460 pwms = <&pwm10 0 25000 0>; 461 pinctrl-names = "default"; 462 pinctrl-0 = <&bl2_enable_pin>; 463 enable-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; 464 status = "okay"; 465}; 466 467&dp2lvds_backlight1 { 468 pwms = <&pwm14 0 25000 0>; 469 pinctrl-names = "default"; 470 pinctrl-0 = <&bl3_enable_pin>; 471 enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; 472 status = "okay"; 473}; 474 475/* 476 * mipi_dcphy0 needs to be enabled 477 * when dsi0 is enabled 478 */ 479&dsi0 { 480 status = "okay"; 481 482 ports { 483 #address-cells = <1>; 484 #size-cells = <0>; 485 486 port@1 { 487 reg = <1>; 488 489 dsi0_out_i2c2_bu18tl82: endpoint { 490 remote-endpoint = <&i2c2_bu18tl82_in_dsi0>; 491 }; 492 }; 493 }; 494}; 495 496&dsi0_in_vp2 { 497 status = "okay"; 498}; 499 500&dsi0_in_vp3 { 501 status = "disabled"; 502}; 503 504/* 505 * mipi_dcphy1 needs to be enabled 506 * when dsi1 is enabled 507 */ 508&dsi1 { 509 status = "okay"; 510 511 ports { 512 #address-cells = <1>; 513 #size-cells = <0>; 514 515 port@1 { 516 reg = <1>; 517 518 dsi1_out_i2c6_bu18tl82: endpoint { 519 remote-endpoint = <&i2c6_bu18tl82_in_dsi1>; 520 }; 521 }; 522 }; 523}; 524 525&dsi1_in_vp2 { 526 status = "disabled"; 527}; 528 529&dsi1_in_vp3 { 530 status = "okay"; 531}; 532 533&edp0 { 534 //split-mode; 535 force-hpd; 536 status = "okay"; 537 538 ports { 539 port@1 { 540 reg = <1>; 541 542 edp0_out_i2c5_bu18tl82: endpoint { 543 remote-endpoint = <&i2c5_bu18tl82_in_edp0>; 544 }; 545 }; 546 }; 547}; 548 549&edp0_in_vp0 { 550 status = "disabled"; 551}; 552 553&edp0_in_vp1 { 554 status = "okay"; 555}; 556 557&edp0_in_vp2 { 558 status = "disabled"; 559}; 560 561&edp1 { 562 force-hpd; 563 status = "disabled"; 564 565 ports { 566 port@1 { 567 reg = <1>; 568 569 edp1_out_i2c7_bu18tl82: endpoint { 570 remote-endpoint = <&i2c7_bu18tl82_in_edp1>; 571 }; 572 }; 573 }; 574}; 575 576&edp1_in_vp0 { 577 status = "disabled"; 578}; 579 580&edp1_in_vp1 { 581 status = "okay"; 582}; 583 584&edp1_in_vp2 { 585 status = "disabled"; 586}; 587 588&edp2lvds_backlight0 { 589 pwms = <&pwm7 0 25000 0>; 590 pinctrl-names = "default"; 591 pinctrl-0 = <&bl4_enable_pin>; 592 enable-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; 593 status = "okay"; 594}; 595 596&edp2lvds_backlight1 { 597 pwms = <&pwm11 0 25000 0>; 598 pinctrl-names = "default"; 599 pinctrl-0 = <&bl5_enable_pin>; 600 enable-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; 601 status = "okay"; 602}; 603 604&hdmi0 { 605 status = "disabled"; 606}; 607 608&hdmi1 { 609 status = "disabled"; 610}; 611 612&hdptxphy0 { 613 status = "okay"; 614}; 615 616&hdptxphy1 { 617 status = "okay"; 618}; 619 620&hdptxphy_hdmi0 { 621 status = "disabled"; 622}; 623 624&hdptxphy_hdmi1 { 625 status = "disabled"; 626}; 627 628&i2c2 { 629 status = "okay"; 630 pinctrl-names = "default"; 631 pinctrl-0 = <&i2c2m4_xfer>; 632 clock-frequency = <400000>; 633 634 bu18tl82: bu18tl82@10 { 635 compatible = "rohm,bu18tl82"; 636 reg = <0x10>; 637 pinctrl-names = "default"; 638 pinctrl-0 = <&ser0_rst_pin>; 639 reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; 640 sel-mipi; 641 status = "okay"; 642 643 serdes-init-sequence = [ 644 0013 0019 645 0014 0008 //014h[3]-lane1 enable 646 0021 0008 647 0023 0009 648 0024 0009 649 022b 0038 650 022c 0072 651 022d 0023 //VPLL=75MHZS 652 //022b 00d8 653 //022c 0089 654 //022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M 655 022e 0080 656 027c 0048 657 027d 0048 //i2c addr 0x48 658 0296 0004 659 0297 0009 //CLLTX0_PLL_GAIN 297h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane 660 //0297 000d //CLLTX0_PLL_GAIN 297h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane 661 0018 00a5 662 0019 0069 663 0267 003d 664 0268 002c 665 0269 002c 666 026a 002c 667 026b 002c 668 0367 003d 669 0368 002c 670 0369 002c 671 036a 002c 672 036b 002c 673 0018 0000 674 0019 0000 675 002a 0018 //gpio0 input lcd_bl_pwm 676 002d 0018 //gpio1 input lcd_pwr_en 677 678 0030 0018 //gpio2 input lcd_rst 679 0033 0018 //gpio3 input tp_rst 680 0034 0005 //bypass des gpio3 681 0036 0000 //gpio4 output tp_int 682 0037 0006 //bypass des gpio4 683 684 02a7 0002 685 02a8 0003 686 02a9 0004 687 02aa 0005 688 0045 0080 689 0046 0007 //1920 690 004b 00d0 691 004c 0002 //720 692 004d 00d0 693 004e 0002 //720 694 0051 0080 695 0052 0007 //1920 696 0053 0024 //CLLCH2_EN 53h[5] 0:1 Clock Tx lane/1:2 Clock Tx lanes 697 0054 0080 698 024d 0061 699 0252 0005 700 0274 0030 //I2C slave address of BU18RL82 for accessing via BU18TL82 701 0275 0020 702 0396 0004 703 0397 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.31 Gbps/lane 704 //0397 000d //CLLTX0_PLL_GAIN 397h[3:2] 1101 2'b11: 2.2~3.60 Gbps/lane 705 0061 0003 //CLLTX0 enable CLLTX1 enable 706 0060 0003 //CLLTX0/1 RGB data output Enable 707 /* TL82 Pattern Gen Set 1 708 * Horizontal Gray Scale 256 steps 709 */ 710 040A 0010 711 040B 0080 712 040C 0080 713 040D 0080 714 0444 0090 715 0446 00d2 716 ]; 717 718 ports { 719 #address-cells = <1>; 720 #size-cells = <0>; 721 722 port@0 { 723 reg = <0>; 724 725 i2c2_bu18tl82_in_dsi0: endpoint { 726 remote-endpoint = <&dsi0_out_i2c2_bu18tl82>; 727 }; 728 }; 729 730 port@1 { 731 reg = <1>; 732 733 i2c2_bu18tl82_out_i2c2_bu18rl82: endpoint { 734 remote-endpoint = <&i2c2_bu18rl82_in_i2c2_bu18tl82>; 735 }; 736 }; 737 }; 738 }; 739 740 bu18rl82: bu18rl82@30 { 741 compatible = "rohm,bu18rl82"; 742 reg = <0x30>; 743 status = "okay"; 744 serdes-init-sequence = [ 745 0011 0003 //Clockless Link Receiver Lane-0+ LVDS portA 746 0012 0003 //Clockless Link Receiver Lane-1+ LVDS portB 747 0013 0000 748 001d 0008 749 001f 0002 //LVDSTX0_REFSEL 750 0020 0002 //LVDSTX1_REFSEL 751 0031 0048 752 0032 0048 //i2c addr 0x48 753 0423 0000 754 0424 0000 755 0425 0020 756 0426 0080 757 0057 0000 758 0058 0002 759 0057 0000 //rl gpio0 output lcd_bl_pwm 760 0058 0002 //bypass ser gpio0 761 005a 0000 //rl gpio1 output lcd_pwr_en 762 005b 0003 //bypass ser gpio1 763 005d 0000 //rl gpio2 output lcd_rst 764 005e 0004 //bypass ser gpio2 765 0060 0000 //rl gpio3 output tp-rst 766 0061 0005 //bypass ser gpio3 767 0063 0018 //rl gpio4 input tp-int 768 0064 0006 //bypass ser gpio4 769 0066 0000 //rl gpio5 output 770 0067 0001 //set gpio5 high 771 772 0073 0080 773 0074 0007 //0x0780 = 1920 774 0075 0080 775 0076 0007 //0x0780 = 1920 776 0079 000a //h[3]: dual lvds mode h[1] single lane / dual lane 777 007b 00d0 778 007c 0002 //0x02d0 = 720 779 007d 00d0 780 007e 0002 //0x02d0 = 720 781 0081 0003 //01---> Sync OFF 782 0082 0010 //Hsync=16clk 783 0084 001c //HBP=28clk 784 0086 0002 //Vsync=2lines 785 0087 0008 //VBP=8lines 786 0088 0000 //VSYNC_CHG=0CLK 787 0089 0010 //Hsync = 16? 788 008b 001c //HFP=28clk? 789 008d 0002 //Vsync=2lines? 790 008e 0008 //VFP=8line? 791 008f 0000 //VSYNC_CHG=0CLK? 792 00d0 0040 //[3]FixHtotalEN 793 00d8 00c0 794 00d9 0003 //DE=960 795 0429 000a //LVDSTX0_PLLGAIN 2'b10: 30 MHz ~ 80 MHz 796 045d 0001 797 0529 000a //LVDSTX1_PLLGAIN 2'b10: 30 MHz ~ 80 MHz 798 055d 0001 799 0091 0003 800 0090 0001 801 /* RL82 Pattern Gen Set 802 * Vertical Gray Scale Color Bar 803 */ 804 060A 00B0 805 060B 00FF 806 060C 00FF 807 060D 00FF 808 0644 0090 809 0646 00d2 810 ]; 811 812 ports { 813 #address-cells = <1>; 814 #size-cells = <0>; 815 816 port@0 { 817 reg = <0>; 818 819 i2c2_bu18rl82_in_i2c2_bu18tl82: endpoint { 820 remote-endpoint = <&i2c2_bu18tl82_out_i2c2_bu18rl82>; 821 }; 822 }; 823 824 port@1 { 825 reg = <1>; 826 827 i2c2_bu18rl82_out_panel0: endpoint { 828 remote-endpoint = <&panel0_in_i2c2_bu18rl82>; 829 }; 830 }; 831 }; 832 }; 833 834 himax@48 { 835 compatible = "himax,hxcommon"; 836 reg = <0x48>; 837 pinctrl-names = "default", "sleep"; 838 pinctrl-0 = <&touch_gpio_dsi0>; 839 pinctrl-1 = <&touch_gpio_dsi0>; 840 himax,location = "himax-touch-dsi0"; 841 //himax,irq-gpio = <&gpio1 RK_PB0 IRQ_TYPE_EDGE_FALLING>; 842 himax,panel-coords = <0 1920 0 720>; 843 himax,display-coords = <0 1920 0 720>; 844 status = "okay"; 845 }; 846}; 847 848&i2c4 { 849 pinctrl-names = "default"; 850 pinctrl-0 = <&i2c4m2_xfer>; 851 clock-frequency = <400000>; 852 status = "okay"; 853 854 bu18tl82@10 { 855 compatible = "rohm,bu18tl82"; 856 reg = <0x10>; 857 status = "okay"; 858 859 serdes-init-sequence = [ 860 0013 001a //013h[3]1-lane1 enable 013h[3] 1-LVDS Receiver Port-A 861 0014 000a //014h[3]1-lane1 enable 014h[3] 1-LVDS Receiver Port-B 862 0021 0008 863 0023 0009 864 0024 0009 865 022b 0038 866 022c 0072 867 022d 0023 //VPLL=75MHZS 868 //022b 00d8 869 //022c 0089 870 //022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M 871 022e 0080 872 027c 0048 873 027d 0048 //i2c addr 0x48 874 0296 0004 875 0297 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.31 Gbps/lane 876 //0297 000d //CLLTX0_PLL_GAIN 297h[3:2] 1101 2'b11: 2.2~3.60 Gbps/lane 877 0018 00a5 878 0019 0069 879 0267 003d 880 0268 002c 881 0269 002c 882 026a 002c 883 026b 002c 884 0367 003d 885 0368 002c 886 0369 002c 887 036a 002c 888 036b 002c 889 0018 0000 890 0019 0000 891 002a 0018 //gpio0 input lcd_bl_pwm 892 002d 0018 //gpio1 input lcd_pwr_en 893 894 0030 0018 //gpio2 input lcd_rst 895 0033 0018 //gpio3 input tp_rst 896 0034 0005 //bypass des gpio3 897 0036 0000 //gpio4 output tp_int 898 0037 0006 //bypass des gpio4 899 900 02a7 0002 901 02a8 0003 902 02a9 0004 903 02aa 0005 904 0045 0080 905 0046 0007 //1920 906 004b 00d0 907 004c 0002 //720 908 004d 00d0 909 004e 0002 //720 910 0051 0080 911 0052 0007 //1920 912 0053 0064 //0053h[6]1:2 Rx ports CLLCH2_EN 53h[5] 1:2 Clock Tx lanes 913 024d 0061 914 0252 0005 915 0274 0030 916 0275 0020 917 0396 0004 918 0397 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane 919 //0397 000d //CLLTX0_PLL_GAIN 397h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane 920 0061 0003 //CLLTX0 enable CLLTX1 enable 921 0060 0003 //CLLTX0/1 RGB data output Enable 922 /* TL82 Pattern Gen Set 1 923 * Horizontal Gray Scale 256 steps 924 */ 925 040A 0010 926 040B 0080 927 040C 0080 928 040D 0080 929 0444 0090 //h_blank=144 930 0446 00d2 //v_blank=210 931 ]; 932 933 ports { 934 #address-cells = <1>; 935 #size-cells = <0>; 936 937 port@0 { 938 reg = <0>; 939 940 i2c4_bu18tl82_in_dp0: endpoint { 941 remote-endpoint = <&dp0_out_i2c4_bu18tl82>; 942 }; 943 }; 944 945 port@1 { 946 reg = <1>; 947 948 i2c4_bu18tl82_out_i2c4_bu18rl82: endpoint { 949 remote-endpoint = <&i2c4_bu18rl82_in_i2c4_bu18tl82>; 950 }; 951 }; 952 }; 953 }; 954 955 bu18rl82@30 { 956 compatible = "rohm,bu18rl82"; 957 reg = <0x30>; 958 status = "okay"; 959 serdes-init-sequence = [ 960 0011 0003 //Clockless Link Receiver Lane-0+ LVDS portA 961 0012 0003 //Clockless Link Receiver Lane-1+ LVDS portB 962 0013 0000 963 001d 0008 964 001f 0002 //LVDSTX0_REFSEL 965 0020 0002 //LVDSTX1_REFSEL 966 0031 0048 967 0032 0048 //i2c addr 0x48 968 0423 0000 969 0424 0000 970 0425 0020 971 0426 0080 972 0057 0000 973 0058 0002 974 0057 0000 //rl gpio0 output lcd_bl_pwm 975 0058 0002 //bypass ser gpio0 976 005a 0000 //rl gpio1 output lcd_pwr_en 977 005b 0003 //bypass ser gpio1 978 005d 0000 //rl gpio2 output lcd_rst 979 005e 0004 //bypass ser gpio2 980 0060 0000 //rl gpio3 output tp-rst 981 0061 0005 //bypass ser gpio3 982 0063 0018 //rl gpio4 input tp-int 983 0064 0006 //bypass ser gpio4 984 0066 0000 //rl gpio5 output 985 0067 0001 //set gpio5 high 986 987 0073 0080 988 0074 0007 //0x0780 = 1920 989 0075 0080 990 0076 0007 //0x0780 = 1920 991 0079 000a //h[3]: dual lvds mode h[1] single lane / dual lane 992 007b 00d0 993 007c 0002 //0x02d0 = 720 994 007d 00d0 995 007e 0002 //0x02d0 = 720 996 0081 0003 //01---> Sync OFF 997 0082 0010 //Hsync=16clk 998 0084 001c //HBP=28clk 999 0086 0002 //Vsync=2lines 1000 0087 0008 //VBP=8lines 1001 0088 0000 //VSYNC_CHG=0CLK 1002 0089 0010 //Hsync = 16? 1003 008b 001c //HFP=28clk? 1004 008d 0002 //Vsync=2lines? 1005 008e 0008 //VFP=8line? 1006 008f 0000 //VSYNC_CHG=0CLK? 1007 00d0 0040 //[3]FixHtotalEN 1008 00d8 00c0 1009 00d9 0003 //DE=960 1010 0429 000a //LVDSTX0_PLLGAIN 2'b10: 30 MHz ~ 80 MHz 1011 045d 0001 1012 0529 000a //LVDSTX1_PLLGAIN 2'b10: 30 MHz ~ 80 MHz 1013 055d 0001 1014 0091 0003 1015 0090 0001 1016 /* RL82 Pattern Gen Set 1017 * Vertical Gray Scale Color Bar 1018 */ 1019 060A 00B0 1020 060B 00FF 1021 060C 00FF 1022 060D 00FF 1023 0644 0090 1024 0646 00d2 1025 ]; 1026 1027 ports { 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 1031 port@0 { 1032 reg = <0>; 1033 1034 i2c4_bu18rl82_in_i2c4_bu18tl82: endpoint { 1035 remote-endpoint = <&i2c4_bu18tl82_out_i2c4_bu18rl82>; 1036 }; 1037 }; 1038 1039 port@1 { 1040 reg = <1>; 1041 1042 i2c4_bu18rl82_out_panel0: endpoint { 1043 remote-endpoint = <&panel0_in_i2c4_bu18rl82>; 1044 }; 1045 }; 1046 }; 1047 }; 1048 1049 himax@48 { 1050 compatible = "himax,hxcommon"; 1051 reg = <0x48>; 1052 pinctrl-names = "default", "sleep"; 1053 pinctrl-0 = <&touch_gpio_dp0>; 1054 pinctrl-1 = <&touch_gpio_dp0>; 1055 himax,location = "himax-touch-dp0"; 1056 himax,irq-gpio = <&gpio0 RK_PC0 IRQ_TYPE_EDGE_FALLING>; 1057 himax,panel-coords = <0 1920 0 720>; 1058 himax,display-coords = <0 1920 0 720>; 1059 status = "okay"; 1060 }; 1061 1062 lt7911d@2b { 1063 compatible = "lontium,lt7911d-fb-notifier"; 1064 reg = <0x2b>; 1065 reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; 1066 status = "okay"; 1067 }; 1068}; 1069 1070&i2c5 { 1071 clock-frequency = <400000>; 1072 status = "okay"; 1073 1074 bu18tl82@10 { 1075 compatible = "rohm,bu18tl82"; 1076 reg = <0x10>; 1077 status = "okay"; 1078 1079 serdes-init-sequence = [ 1080 0013 001a 1081 0014 000a 1082 0021 0008 1083 0023 0009 1084 0024 0009 1085 002a 0018 //gpio0 input lcd_bl_pwm 1086 002d 0018 //gpio1 input lcd_pwr_en 1087 1088 0030 0018 //gpio2 input lcd_rst 1089 0033 0000 //gpio3 output tp_int 1090 0034 0005 //bypass des gpio3 1091 0036 0018 //gpio4 input tp_rst 1092 0037 0006 //bypass des gpio4 1093 027c 0041 1094 027d 0041 1095 0045 0080 1096 0046 0007 1097 004b 0038 1098 004c 0004 1099 0053 0064 1100 022b 0062 1101 022c 0027 1102 022d 002e 1103 0274 0030 1104 0275 0020 1105 0296 0004 1106 0297 000d 1107 02b2 00c8 1108 02b4 0001 1109 02b8 00ff 1110 02b9 000f 1111 02ba 00ff 1112 02bb 000f 1113 02be 00ff 1114 02bf 001f 1115 02c2 00ff 1116 02c3 001f 1117 0396 0004 1118 0397 000d 1119 03b2 00c8 1120 03b4 0001 1121 03b8 00ff 1122 03b9 000f 1123 03ba 00ff 1124 03bb 000f 1125 03be 00ff 1126 03bf 001f 1127 03c2 00ff 1128 03c3 001f 1129 0060 0001 1130 0061 0003 1131 022e 0080 1132 032e 0080 1133 /* TL82 Pattern Gen Set 1 1134 * Horizontal Gray Scale 256 steps 1135 */ 1136 040A 0010 1137 040B 0080 1138 040C 0080 1139 040D 0080 1140 0444 0019 1141 0445 0020 1142 0446 001f 1143 ]; 1144 1145 ports { 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 1149 port@0 { 1150 reg = <0>; 1151 1152 i2c5_bu18tl82_in_edp0: endpoint { 1153 remote-endpoint = <&edp0_out_i2c5_bu18tl82>; 1154 }; 1155 }; 1156 1157 port@1 { 1158 reg = <1>; 1159 1160 i2c5_bu18tl82_out_i2c5_bu18rl82: endpoint { 1161 remote-endpoint = <&i2c5_bu18rl82_in_i2c5_bu18tl82>; 1162 }; 1163 }; 1164 }; 1165 }; 1166 1167 bu18rl82@30 { 1168 compatible = "rohm,bu18rl82"; 1169 reg = <0x30>; 1170 status = "okay"; 1171 serdes-init-sequence = [ 1172 0011 000b 1173 0012 0003 1174 0013 0001 1175 001d 0008 1176 001f 0002 1177 0020 0002 1178 0031 0041 //i2c addr 0x41 1179 0032 0041 //i2c addr 0x41 1180 0057 0000 //rl gpio0 output lcd_bl_pwm 1181 0058 0002 //bypass ser gpio0 1182 005a 0000 //rl gpio1 output lcd_pwr_en 1183 005b 0001 //bypass ser gpio1 1184 005d 0000 //rl gpio2 output lcd_rst 1185 005e 0004 //bypass ser gpio2 1186 0060 0018 //rl gpio3 input tp-int 1187 042e 0005 //bypass ser gpio3 1188 0061 0005 //bypass ser gpio3 1189 0063 0000 //rl gpio4 output tp-rst 1190 042f 0006 //bypass ser gpio4 1191 0064 0006 //bypass ser gpio4 1192 0066 0000 //rl gpio5 output 1193 0067 0007 //bypass ser gpio5 1194 0073 0080 1195 0074 0007 1196 0079 000a 1197 007b 0038 1198 007c 0004 1199 0081 0003 1200 0082 0010 1201 0084 0020 1202 0086 0002 1203 0087 0002 1204 0088 0010 1205 0089 0010 1206 008b 0020 1207 008d 0002 1208 008e 0002 1209 008f 0010 1210 00d0 0040 1211 00d8 0042 1212 00d9 0004 1213 0423 0002 1214 0424 00ec 1215 0425 0027 1216 0429 000a 1217 045d 0001 1218 0529 000a 1219 055d 0003 1220 0090 0001 1221 0091 0003 1222 0426 0080 1223 042d 0004 1224 /* RL82 Pattern Gen Set 1225 * Vertical Gray Scale Color Bar 1226 */ 1227 060A 00B0 1228 060B 00FF 1229 060C 00FF 1230 060D 00FF 1231 0644 0019 1232 0645 0020 1233 0646 001f 1234 ]; 1235 1236 ports { 1237 #address-cells = <1>; 1238 #size-cells = <0>; 1239 1240 port@0 { 1241 reg = <0>; 1242 1243 i2c5_bu18rl82_in_i2c5_bu18tl82: endpoint { 1244 remote-endpoint = <&i2c5_bu18tl82_out_i2c5_bu18rl82>; 1245 }; 1246 }; 1247 1248 port@1 { 1249 reg = <1>; 1250 1251 i2c5_bu18rl82_out_panel0: endpoint { 1252 remote-endpoint = <&panel0_in_i2c5_bu18rl82>; 1253 }; 1254 }; 1255 }; 1256 }; 1257 1258 ilitek@41 { 1259 compatible = "ilitek,ili251x"; 1260 reg = <0x41>; 1261 interrupt-parent = <&gpio0>; 1262 interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>; 1263 pinctrl-names = "default"; 1264 pinctrl-0 = <&touch_gpio_edp0>; 1265 reset-gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_LOW>; 1266 ilitek,name = "ilitek_i2c"; 1267 status = "okay"; 1268 }; 1269 1270 lt7911d@2b { 1271 compatible = "lontium,lt7911d-fb-notifier"; 1272 reg = <0x2b>; 1273 reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_LOW>; 1274 status = "okay"; 1275 }; 1276}; 1277 1278&i2c6 { 1279 status = "okay"; 1280 pinctrl-names = "default"; 1281 pinctrl-0 = <&i2c6m3_xfer>; 1282 clock-frequency = <400000>; 1283 1284 bu18tl82@10 { 1285 compatible = "rohm,bu18tl82"; 1286 reg = <0x10>; 1287 pinctrl-names = "default"; 1288 pinctrl-0 = <&ser1_rst_pin>; 1289 reset-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; 1290 sel-mipi; 1291 status = "okay"; 1292 serdes-init-sequence = [ 1293 0013 0019 1294 0014 0008 //014h[3]-lane1 enable 1295 0021 0008 1296 0023 0009 1297 0024 0009 1298 022b 0038 1299 022c 0072 1300 022d 0023 //VPLL=75MHZS 1301 //022b 00d8 1302 //022c 0089 1303 //022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M 1304 022e 0080 1305 027c 0048 1306 027d 0048 //i2c addr 0x48 1307 0296 0004 1308 0297 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane 1309 //0297 000d //CLLTX0_PLL_GAIN 297h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane 1310 0018 00a5 1311 0019 0069 1312 0267 003d 1313 0268 002c 1314 0269 002c 1315 026a 002c 1316 026b 002c 1317 0367 003d 1318 0368 002c 1319 0369 002c 1320 036a 002c 1321 036b 002c 1322 0018 0000 1323 0019 0000 1324 002a 0018 //gpio0 input lcd_bl_pwm 1325 002d 0018 //gpio1 input lcd_pwr_en 1326 1327 0030 0018 //gpio2 input lcd_rst 1328 0033 0018 //gpio3 input tp_rst 1329 0034 0005 //bypass des gpio3 1330 0036 0000 //gpio4 output tp_int 1331 0037 0006 //bypass des gpio4 1332 1333 02a7 0002 1334 02a8 0003 1335 02a9 0004 1336 02aa 0005 1337 0045 0080 1338 0046 0007 //1920 1339 004b 00d0 1340 004c 0002 //720 1341 004d 00d0 1342 004e 0002 //720 1343 0051 0080 1344 0052 0007 //1920 1345 0053 0024 //CLLCH2_EN 53h[5] 0:1 Clock Tx lane/1:2 Clock Tx lanes 1346 0054 0080 1347 024d 0061 1348 0252 0005 1349 0274 0030 1350 0275 0020 1351 0396 0004 1352 0397 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane 1353 //0397 000d //CLLTX0_PLL_GAIN 397h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane 1354 0061 0003 //CLLTX0 enable CLLTX1 enable 1355 0060 0003 //CLLTX0/1 RGB data output Enable 1356 /* TL82 Pattern Gen Set 1 1357 * Horizontal Gray Scale 256 steps 1358 */ 1359 040A 0010 1360 040B 0080 1361 040C 0080 1362 040D 0080 1363 0444 0090 //h_blank=144 1364 0446 00d2 //v_blank=210 1365 1366 1367 ]; 1368 1369 ports { 1370 #address-cells = <1>; 1371 #size-cells = <0>; 1372 1373 port@0 { 1374 reg = <0>; 1375 1376 i2c6_bu18tl82_in_dsi1: endpoint { 1377 remote-endpoint = <&dsi1_out_i2c6_bu18tl82>; 1378 }; 1379 }; 1380 1381 port@1 { 1382 reg = <1>; 1383 1384 i2c6_bu18tl82_out_i2c6_bu18rl82: endpoint { 1385 remote-endpoint = <&i2c6_bu18rl82_in_i2c6_bu18tl82>; 1386 }; 1387 }; 1388 }; 1389 }; 1390 1391 bu18rl82@30 { 1392 compatible = "rohm,bu18rl82"; 1393 reg = <0x30>; 1394 status = "okay"; 1395 serdes-init-sequence = [ 1396 0011 0003 //Clockless Link Receiver Lane-0+ LVDS portA 1397 0012 0003 //Clockless Link Receiver Lane-1+ LVDS portB 1398 0013 0000 1399 001d 0008 1400 001f 0002 //LVDSTX0_REFSEL 1401 0020 0002 //LVDSTX1_REFSEL 1402 0031 0048 1403 0032 0048 //i2c addr 0x48 1404 0423 0000 1405 0424 0000 1406 0425 0020 1407 0426 0080 1408 0057 0000 1409 0058 0002 1410 0057 0000 //rl gpio0 output lcd_bl_pwm 1411 0058 0002 //bypass ser gpio0 1412 005a 0000 //rl gpio1 output lcd_pwr_en 1413 005b 0003 //bypass ser gpio1 1414 005d 0000 //rl gpio2 output lcd_rst 1415 005e 0004 //bypass ser gpio2 1416 0060 0000 //rl gpio3 output tp-rst 1417 0061 0005 //bypass ser gpio3 1418 0063 0018 //rl gpio4 input tp-int 1419 0064 0006 //bypass ser gpio4 1420 0066 0000 //rl gpio5 output 1421 0067 0001 //set gpio5 high 1422 1423 0073 0080 1424 0074 0007 //0x0780 = 1920 1425 0075 0080 1426 0076 0007 //0x0780 = 1920 1427 0079 000a //h[3]: dual lvds mode h[1] single lane / dual lane 1428 007b 00d0 1429 007c 0002 //0x02d0 = 720 1430 007d 00d0 1431 007e 0002 //0x02d0 = 720 1432 0081 0003 //01---> Sync OFF 1433 0082 0010 //Hsync=16clk 1434 0084 001c //HBP=28clk 1435 0086 0002 //Vsync=2lines 1436 0087 0008 //VBP=8lines 1437 0088 0000 //VSYNC_CHG=0CLK 1438 0089 0010 //Hsync = 16? 1439 008b 001c //HFP=28clk? 1440 008d 0002 //Vsync=2lines? 1441 008e 0008 //VFP=8line? 1442 008f 0000 //VSYNC_CHG=0CLK? 1443 00d0 0040 //[3]FixHtotalEN 1444 00d8 00c0 1445 00d9 0003 //DE=960 1446 0429 000a //LVDSTX0_PLLGAIN 2'b10: 30 MHz ~ 80 MHz 1447 045d 0001 1448 0529 000a //LVDSTX1_PLLGAIN 2'b10: 30 MHz ~ 80 MHz 1449 055d 0001 1450 0091 0003 1451 0090 0001 1452 /* RL82 Pattern Gen Set 1453 * Vertical Gray Scale Color Bar 1454 */ 1455 060A 00B0 1456 060B 00FF 1457 060C 00FF 1458 060D 00FF 1459 0644 0090 1460 0646 00d2 1461 ]; 1462 1463 ports { 1464 #address-cells = <1>; 1465 #size-cells = <0>; 1466 1467 port@0 { 1468 reg = <0>; 1469 1470 i2c6_bu18rl82_in_i2c6_bu18tl82: endpoint { 1471 remote-endpoint = <&i2c6_bu18tl82_out_i2c6_bu18rl82>; 1472 }; 1473 }; 1474 1475 port@1 { 1476 reg = <1>; 1477 1478 i2c6_bu18rl82_out_panel1: endpoint { 1479 remote-endpoint = <&panel1_in_i2c6_bu18rl82>; 1480 }; 1481 }; 1482 }; 1483 }; 1484 1485 himax@48 { 1486 compatible = "himax,hxcommon"; 1487 reg = <0x48>; 1488 pinctrl-names = "default", "sleep"; 1489 pinctrl-0 = <&touch_gpio_dsi1>; 1490 pinctrl-1 = <&touch_gpio_dsi1>; 1491 himax,location = "himax-touch-dsi1"; 1492 himax,irq-gpio = <&gpio1 RK_PB1 IRQ_TYPE_EDGE_FALLING>; 1493 himax,panel-coords = <0 1920 0 720>; 1494 himax,display-coords = <0 1920 0 720>; 1495 status = "okay"; 1496 }; 1497}; 1498 1499&i2c7 { 1500 pinctrl-names = "default"; 1501 pinctrl-0 = <&i2c7m3_xfer>; 1502 clock-frequency = <400000>; 1503 status = "disabled"; 1504 1505 bu18tl82@10 { 1506 compatible = "rohm,bu18tl82"; 1507 reg = <0x10>; 1508 status = "okay"; 1509 1510 serdes-init-sequence = [ 1511 0013 001a 1512 0014 000a 1513 0021 0008 1514 0023 0009 1515 0024 0009 1516 002a 0018 //gpio0 input lcd_bl_pwm 1517 002d 0018 //gpio1 input lcd_pwr_en 1518 1519 0030 0018 //gpio2 input lcd_rst 1520 0033 0000 //gpio3 output tp_int 1521 0034 0005 //bypass des gpio3 1522 0036 0018 //gpio4 input tp_rst 1523 0037 0006 //bypass des gpio4 1524 027c 0041 1525 027d 0041 1526 0045 0080 1527 0046 0007 1528 004b 0038 1529 004c 0004 1530 0053 0064 1531 022b 0062 1532 022c 0027 1533 022d 002e 1534 0274 0030 1535 0275 0020 1536 0296 0004 1537 0297 000d 1538 02b2 00c8 1539 02b4 0001 1540 02b8 00ff 1541 02b9 000f 1542 02ba 00ff 1543 02bb 000f 1544 02be 00ff 1545 02bf 001f 1546 02c2 00ff 1547 02c3 001f 1548 0396 0004 1549 0397 000d 1550 03b2 00c8 1551 03b4 0001 1552 03b8 00ff 1553 03b9 000f 1554 03ba 00ff 1555 03bb 000f 1556 03be 00ff 1557 03bf 001f 1558 03c2 00ff 1559 03c3 001f 1560 0060 0001 1561 0061 0003 1562 022e 0080 1563 032e 0080 1564 /* TL82 Pattern Gen Set 1 1565 * Horizontal Gray Scale 256 steps 1566 */ 1567 040A 0010 1568 040B 0080 1569 040C 0080 1570 040D 0080 1571 0444 0019 1572 0445 0020 1573 0446 001f 1574 ]; 1575 1576 ports { 1577 #address-cells = <1>; 1578 #size-cells = <0>; 1579 1580 port@0 { 1581 reg = <0>; 1582 1583 i2c7_bu18tl82_in_edp1: endpoint { 1584 remote-endpoint = <&edp1_out_i2c7_bu18tl82>; 1585 }; 1586 }; 1587 1588 port@1 { 1589 reg = <1>; 1590 1591 i2c7_bu18tl82_out_i2c7_bu18rl82: endpoint { 1592 remote-endpoint = <&i2c7_bu18rl82_in_i2c7_bu18tl82>; 1593 }; 1594 }; 1595 }; 1596 }; 1597 1598 bu18rl82@30 { 1599 compatible = "rohm,bu18rl82"; 1600 reg = <0x30>; 1601 status = "okay"; 1602 serdes-init-sequence = [ 1603 0011 000b 1604 0012 0003 1605 0013 0001 1606 001d 0008 1607 001f 0002 1608 0020 0002 1609 0031 0041 //i2c addr 0x41 1610 0032 0041 //i2c addr 0x41 1611 0057 0000 //rl gpio0 output lcd_bl_pwm 1612 0058 0002 //bypass ser gpio0 1613 005a 0000 //rl gpio1 output lcd_pwr_en 1614 005b 0001 //bypass ser gpio1 1615 005d 0000 //rl gpio2 output lcd_rst 1616 005e 0004 //bypass ser gpio2 1617 0060 0018 //rl gpio3 input tp-int 1618 042e 0005 //bypass ser gpio3 1619 0061 0005 //bypass ser gpio3 1620 0063 0000 //rl gpio4 output tp-rst 1621 0064 0006 //bypass ser gpio4 1622 0066 0000 //rl gpio5 output 1623 0067 0007 //bypass ser gpio5 1624 0073 0080 1625 0074 0007 1626 0079 000a 1627 007b 0038 1628 007c 0004 1629 0081 0003 1630 0082 0010 1631 0084 0020 1632 0086 0002 1633 0087 0002 1634 0088 0010 1635 0089 0010 1636 008b 0020 1637 008d 0002 1638 008e 0002 1639 008f 0010 1640 00d0 0040 1641 00d8 0042 1642 00d9 0004 1643 0423 0002 1644 0424 00ec 1645 0425 0027 1646 0429 000a 1647 045d 0001 1648 0529 000a 1649 055d 0003 1650 0090 0001 1651 0091 0003 1652 0426 0080 1653 042d 0004 1654 /* RL82 Pattern Gen Set 1655 * Vertical Gray Scale Color Bar 1656 */ 1657 060A 00B0 1658 060B 00FF 1659 060C 00FF 1660 060D 00FF 1661 0644 0019 1662 0645 0020 1663 0646 001f 1664 ]; 1665 1666 ports { 1667 #address-cells = <1>; 1668 #size-cells = <0>; 1669 1670 port@0 { 1671 reg = <0>; 1672 1673 i2c7_bu18rl82_in_i2c7_bu18tl82: endpoint { 1674 remote-endpoint = <&i2c7_bu18tl82_out_i2c7_bu18rl82>; 1675 }; 1676 }; 1677 1678 port@1 { 1679 reg = <1>; 1680 1681 i2c7_bu18rl82_out_panel1: endpoint { 1682 remote-endpoint = <&panel1_in_i2c7_bu18rl82>; 1683 }; 1684 }; 1685 }; 1686 }; 1687 1688 lt7911d@2b { 1689 compatible = "lontium,lt7911d-fb-notifier"; 1690 reg = <0x2b>; 1691 reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>; 1692 status = "okay"; 1693 }; 1694}; 1695 1696&i2c8 { 1697 pinctrl-names = "default"; 1698 pinctrl-0 = <&i2c8m2_xfer>; 1699 clock-frequency = <400000>; 1700 status = "disabled"; 1701 1702 bu18tl82@10 { 1703 compatible = "rohm,bu18tl82"; 1704 reg = <0x10>; 1705 status = "okay"; 1706 1707 serdes-init-sequence = [ 1708 0013 001a //013h[3]1-lane1 enable 013h[3] 1-LVDS Receiver Port-A 1709 0014 000a //014h[3]1-lane1 enable 014h[3] 1-LVDS Receiver Port-B 1710 0021 0008 1711 0023 0009 1712 0024 0009 1713 022b 0038 1714 022c 0072 1715 022d 0023 //VPLL=75MHZS 1716 //022b 00d8 1717 //022c 0089 1718 //022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M 1719 022e 0080 1720 027c 0048 1721 027d 0048 //i2c addr 0x48 1722 0296 0004 1723 0297 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane 1724 //0297 000d //CLLTX0_PLL_GAIN 297h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane 1725 0018 00a5 1726 0019 0069 1727 0267 003d 1728 0268 002c 1729 0269 002c 1730 026a 002c 1731 026b 002c 1732 0367 003d 1733 0368 002c 1734 0369 002c 1735 036a 002c 1736 036b 002c 1737 0018 0000 1738 0019 0000 1739 002a 0018 //gpio0 input lcd_bl_pwm 1740 002d 0018 //gpio1 input lcd_pwr_en 1741 1742 0030 0018 //gpio2 input lcd_rst 1743 0033 0018 //gpio3 input tp_rst 1744 0034 0005 //bypass des gpio3 1745 0036 0000 //gpio4 output tp_int 1746 0037 0006 //bypass des gpio4 1747 1748 02a7 0002 1749 02a8 0003 1750 02a9 0004 1751 02aa 0005 1752 0045 0080 1753 0046 0007 //1920 1754 004b 00d0 1755 004c 0002 //720 1756 004d 00d0 1757 004e 0002 //720 1758 0051 0080 1759 0052 0007 //1920 1760 0053 0064 //0053h[6]1:2 Rx ports CLLCH2_EN 53h[5] 1:2 Clock Tx lanes 1761 024d 0061 1762 0252 0005 1763 0274 0030 1764 0275 0020 1765 0396 0004 1766 0397 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane 1767 //0397 000d //CLLTX0_PLL_GAIN 397h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane 1768 0061 0003 //CLLTX0 enable CLLTX1 enable 1769 0060 0003 //CLLTX0/1 RGB data output Enable 1770 /* TL82 Pattern Gen Set 1 1771 * Horizontal Gray Scale 256 steps 1772 */ 1773 040A 0010 1774 040B 0080 1775 040C 0080 1776 040D 0080 1777 0444 0090 //h_blank=144 1778 0446 00d2 //v_blank=210 1779 ]; 1780 1781 ports { 1782 #address-cells = <1>; 1783 #size-cells = <0>; 1784 1785 port@0 { 1786 reg = <0>; 1787 1788 i2c8_bu18tl82_in_dp1: endpoint { 1789 remote-endpoint = <&dp1_out_i2c8_bu18tl82>; 1790 }; 1791 }; 1792 1793 port@1 { 1794 reg = <1>; 1795 1796 i2c8_bu18tl82_out_i2c8_bu18rl82: endpoint { 1797 remote-endpoint = <&i2c8_bu18rl82_in_i2c8_bu18tl82>; 1798 }; 1799 }; 1800 }; 1801 }; 1802 1803 bu18rl82@30 { 1804 compatible = "rohm,bu18rl82"; 1805 reg = <0x30>; 1806 status = "okay"; 1807 serdes-init-sequence = [ 1808 0011 0003 //Clockless Link Receiver Lane-0+ LVDS portA 1809 0012 0003 //Clockless Link Receiver Lane-1+ LVDS portB 1810 0013 0000 1811 001d 0008 1812 001f 0002 //LVDSTX0_REFSEL 1813 0020 0002 //LVDSTX1_REFSEL 1814 0031 0048 1815 0032 0048 //i2c addr 0x48 1816 0423 0000 1817 0424 0000 1818 0425 0020 1819 0426 0080 1820 0057 0000 1821 0058 0002 1822 0057 0000 //rl gpio0 output lcd_bl_pwm 1823 0058 0002 //bypass ser gpio0 1824 005a 0000 //rl gpio1 output lcd_pwr_en 1825 005b 0003 //bypass ser gpio1 1826 005d 0000 //rl gpio2 output lcd_rst 1827 005e 0004 //bypass ser gpio2 1828 0060 0000 //rl gpio3 output tp-rst 1829 0061 0005 //bypass ser gpio3 1830 0063 0018 //rl gpio4 input tp-int 1831 0064 0006 //bypass ser gpio4 1832 0066 0000 //rl gpio5 output 1833 0067 0001 //set gpio5 high 1834 1835 0073 0080 1836 0074 0007 //0x0780 = 1920 1837 0075 0080 1838 0076 0007 //0x0780 = 1920 1839 0079 000a //h[3]: dual lvds mode h[1] single lane / dual lane 1840 007b 00d0 1841 007c 0002 //0x02d0 = 720 1842 007d 00d0 1843 007e 0002 //0x02d0 = 720 1844 0081 0003 //01---> Sync OFF 1845 0082 0010 //Hsync=16clk 1846 0084 001c //HBP=28clk 1847 0086 0002 //Vsync=2lines 1848 0087 0008 //VBP=8lines 1849 0088 0000 //VSYNC_CHG=0CLK 1850 0089 0010 //Hsync = 16? 1851 008b 001c //HFP=28clk? 1852 008d 0002 //Vsync=2lines? 1853 008e 0008 //VFP=8line? 1854 008f 0000 //VSYNC_CHG=0CLK? 1855 00d0 0040 //[3]FixHtotalEN 1856 00d8 00c0 1857 00d9 0003 //DE=960 1858 0429 000a //LVDSTX0_PLLGAIN 2'b10: 30 MHz ~ 80 MHz 1859 045d 0001 1860 0529 000a //LVDSTX1_PLLGAIN 2'b10: 30 MHz ~ 80 MHz 1861 055d 0001 1862 0091 0003 1863 0090 0001 1864 /* RL82 Pattern Gen Set 1865 * Vertical Gray Scale Color Bar 1866 */ 1867 060A 00B0 1868 060B 00FF 1869 060C 00FF 1870 060D 00FF 1871 0644 0090 1872 0646 00d2 1873 ]; 1874 1875 ports { 1876 #address-cells = <1>; 1877 #size-cells = <0>; 1878 1879 port@0 { 1880 reg = <0>; 1881 1882 i2c8_bu18rl82_in_i2c8_bu18tl82: endpoint { 1883 remote-endpoint = <&i2c8_bu18tl82_out_i2c8_bu18rl82>; 1884 }; 1885 }; 1886 1887 port@1 { 1888 reg = <1>; 1889 1890 i2c8_bu18rl82_out_panel1: endpoint { 1891 remote-endpoint = <&panel1_in_i2c8_bu18rl82>; 1892 }; 1893 }; 1894 }; 1895 }; 1896 1897 lt7911d@2b { 1898 compatible = "lontium,lt7911d-fb-notifier"; 1899 reg = <0x2b>; 1900 reset-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; 1901 status = "okay"; 1902 }; 1903}; 1904 1905&mipi_dcphy0 { 1906 status = "okay"; 1907}; 1908 1909&mipi_dcphy1 { 1910 status = "okay"; 1911}; 1912 1913 1914&pinctrl { 1915 1916 bl { 1917 bl0_enable_pin: bl0-enable-pin { 1918 rockchip,pins = 1919 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, 1920 <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, 1921 <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 1922 1923 }; 1924 1925 bl1_enable_pin: bl1-enable-pin { 1926 rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; 1927 }; 1928 1929 bl2_enable_pin: bl2-enable-pin { 1930 rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; 1931 }; 1932 1933 bl3_enable_pin: bl3-enable-pin { 1934 rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 1935 }; 1936 1937 bl4_enable_pin: bl4-enable-pin { 1938 rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; 1939 }; 1940 1941 bl5_enable_pin: bl5-enable-pin { 1942 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1943 }; 1944 }; 1945 1946 serdes { 1947 //dsi0 1948 ser0_rst_pin: ser0-rst-pin { 1949 rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 1950 }; 1951 1952 //dsi1 1953 ser1_rst_pin: ser1-rst-pin { 1954 rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1955 }; 1956 }; 1957 1958 touch { 1959 //dsi0-i2c2 1960 touch_gpio_dsi0: touch-gpio-dsi0 { 1961 rockchip,pins = 1962 //<1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, //INT 1963 <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; //RST 1964 }; 1965 //dsi1-i2c6 1966 touch_gpio_dsi1: touch-gpio-dsi1 { 1967 rockchip,pins = 1968 <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>, //INT 1969 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; //RST 1970 }; 1971 //dp0-i2c4 1972 touch_gpio_dp0: touch-gpio-dp0 { 1973 rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; 1974 }; 1975 //edp0-i2c5 1976 touch_gpio_edp0: touch-gpio-edp0 { 1977 rockchip,pins = 1978 <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>, //INT 1979 <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; //RST 1980 }; 1981 }; 1982}; 1983 1984/* dsi0->serdes->lvds_panel */ 1985&pwm0 { 1986 status = "okay"; 1987 pinctrl-0 = <&pwm0m2_pins>; 1988}; 1989 1990/* dp0->serdes->lvds_panel */ 1991&pwm10 { 1992 pinctrl-0 = <&pwm10m2_pins>; 1993 status = "okay"; 1994}; 1995 1996/* edp1->serdes->lvds_panel */ 1997&pwm11 { 1998 pinctrl-0 = <&pwm11m3_pins>; 1999 status = "okay"; 2000}; 2001 2002/* edp0->serdes->lvds_panel */ 2003&pwm7 { 2004 pinctrl-0 = <&pwm7m0_pins>; 2005 status = "okay"; 2006}; 2007 2008/* dsi1->serdes->lvds_panel */ 2009&pwm13 { 2010 status = "okay"; 2011 pinctrl-0 = <&pwm13m1_pins>; 2012}; 2013 2014/* dp1->serdes->lvds_panel */ 2015&pwm14 { 2016 pinctrl-0 = <&pwm14m0_pins>; 2017 status = "okay"; 2018}; 2019 2020&route_dp0 { 2021 status = "disabled"; 2022 connect = <&vp0_out_dp0>; 2023 logo,uboot = "logo34.bmp"; 2024 logo,kernel = "logo34.bmp"; 2025}; 2026 2027&route_dp1 { 2028 status = "disabled"; 2029 connect = <&vp0_out_dp1>; 2030 logo,uboot = "logo34.bmp"; 2031 logo,kernel = "logo34.bmp"; 2032}; 2033 2034&route_dsi0 { 2035 status = "okay"; 2036 connect = <&vp2_out_dsi0>; 2037 logo,uboot = "logo1.bmp"; 2038 logo,kernel = "logo1.bmp"; 2039}; 2040 2041&route_dsi1 { 2042 status = "okay"; 2043 connect = <&vp3_out_dsi1>; 2044 logo,uboot = "logo2.bmp"; 2045 logo,kernel = "logo2.bmp"; 2046}; 2047 2048&route_edp0 { 2049 status = "disabled"; 2050 connect = <&vp1_out_edp0>; 2051 logo,uboot = "logo56.bmp"; 2052 logo,kernel = "logo56.bmp"; 2053}; 2054 2055&route_edp1 { 2056 status = "disabled"; 2057 connect = <&vp1_out_edp1>; 2058 logo,uboot = "logo56.bmp"; 2059 logo,kernel = "logo56.bmp"; 2060}; 2061 2062&usbdp_phy0 { 2063 rockchip,dp-lane-mux = <0 1 2 3>; 2064 status = "okay"; 2065}; 2066 2067&usbdp_phy1 { 2068 rockchip,dp-lane-mux = <0 1 2 3>; 2069 status = "okay"; 2070}; 2071 2072&vop { 2073 assigned-clocks = <&cru PLL_V0PLL>; 2074 assigned-clock-rates = <1152000000>; 2075}; 2076 2077&vp0 { 2078 assigned-clocks = <&cru DCLK_VOP0_SRC>; 2079 assigned-clock-parents = <&cru PLL_V0PLL>; 2080}; 2081 2082&vp1 { 2083 assigned-clocks = <&cru DCLK_VOP1_SRC>; 2084 assigned-clock-parents = <&cru PLL_GPLL>; 2085}; 2086 2087&vp2 { 2088 assigned-clocks = <&cru DCLK_VOP2_SRC>; 2089 assigned-clock-parents = <&cru PLL_V0PLL>; 2090}; 2091 2092&vp3 { 2093 assigned-clocks = <&cru DCLK_VOP3>; 2094 assigned-clock-parents = <&cru PLL_V0PLL>; 2095}; 2096
