xref: /rk3399_rockchip-uboot/arch/arm/dts/rk3588-u-boot.dtsi (revision 6a1150a873d2da85fbb7785a896050e177bdee4c) 
1/*
2 * (C) Copyright 2021 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier:     GPL-2.0+
5 */
6
7#include <dt-bindings/gpio/gpio.h>
8
9/ {
10	aliases {
11		mmc0 = &sdhci;
12		mmc1 = &sdmmc;
13	};
14
15	chosen {
16		stdout-path = &uart2;
17		u-boot,spl-boot-order = &sdmmc, &sdhci, &spi_nand, &spi_nor;
18	};
19
20	secure-otp@fe3a0000 {
21		u-boot,dm-spl;
22		compatible = "rockchip,rk3588-secure-otp";
23		reg = <0x0 0xfe3a0000 0x0 0x4000>;
24	};
25};
26
27&firmware {
28	u-boot,dm-spl;
29};
30
31&gpio0 {
32	u-boot,dm-spl;
33	status = "okay";
34};
35&gpio1 {
36	u-boot,dm-pre-reloc;
37	status = "okay";
38};
39
40&gpio2 {
41	u-boot,dm-pre-reloc;
42	status = "okay";
43};
44&gpio3 {
45	u-boot,dm-pre-reloc;
46	status = "okay";
47};
48
49&gpio4 {
50	u-boot,dm-pre-reloc;
51	status = "okay";
52};
53
54&scmi {
55	u-boot,dm-spl;
56};
57
58&scmi_clk {
59	u-boot,dm-spl;
60};
61
62&sram {
63	u-boot,dm-spl;
64};
65
66&scmi_shmem {
67	u-boot,dm-spl;
68};
69
70&xin24m {
71	u-boot,dm-pre-reloc;
72	status = "okay";
73};
74
75&cru {
76	u-boot,dm-spl;
77	status = "okay";
78};
79
80&psci {
81	u-boot,dm-pre-reloc;
82	status = "okay";
83};
84
85&crypto {
86	u-boot,dm-spl;
87	status = "okay";
88};
89
90&sys_grf {
91	u-boot,dm-spl;
92	status = "okay";
93};
94
95&pcie30_phy_grf {
96	u-boot,dm-pre-reloc;
97	status = "okay";
98};
99
100&php_grf {
101	u-boot,dm-pre-reloc;
102	status = "okay";
103};
104
105&pipe_phy0_grf {
106	u-boot,dm-pre-reloc;
107	status = "okay";
108};
109
110&pipe_phy1_grf {
111	u-boot,dm-pre-reloc;
112	status = "okay";
113};
114
115&pipe_phy2_grf {
116	u-boot,dm-pre-reloc;
117	status = "okay";
118};
119
120&uart2 {
121	u-boot,dm-spl;
122	status = "okay";
123};
124
125&hw_decompress {
126	u-boot,dm-spl;
127	status = "okay";
128};
129
130&rng {
131	u-boot,dm-pre-reloc;
132	status = "okay";
133};
134
135&sfc {
136	u-boot,dm-spl;
137	status = "okay";
138
139	#address-cells = <1>;
140	#size-cells = <0>;
141	spi_nand: flash@0 {
142		u-boot,dm-spl;
143		compatible = "spi-nand";
144		reg = <0>;
145		spi-tx-bus-width = <1>;
146		spi-rx-bus-width = <4>;
147		spi-max-frequency = <80000000>;
148	};
149
150	spi_nor: flash@1 {
151		u-boot,dm-spl;
152		compatible = "jedec,spi-nor";
153		label = "sfc_nor";
154		reg = <0>;
155		spi-tx-bus-width = <1>;
156		spi-rx-bus-width = <4>;
157		spi-max-frequency = <80000000>;
158	};
159};
160
161&saradc {
162	u-boot,dm-pre-reloc;
163	status = "okay";
164};
165
166&sdmmc {
167	bus-width = <4>;
168	u-boot,dm-spl;
169	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
170	status = "okay";
171};
172
173&sdhci {
174	bus-width = <8>;
175	u-boot,dm-spl;
176	mmc-hs400-1_8v;
177	mmc-hs400-enhanced-strobe;
178	non-removable;
179	status = "okay";
180};
181
182&usb2phy0_grf {
183	u-boot,dm-pre-reloc;
184};
185
186&u2phy0 {
187	u-boot,dm-pre-reloc;
188	status = "okay";
189};
190
191&u2phy0_otg {
192	u-boot,dm-pre-reloc;
193	status = "okay";
194};
195
196&usb_grf{
197	u-boot,dm-pre-reloc;
198};
199
200&usbdpphy0_grf{
201	u-boot,dm-pre-reloc;
202};
203
204&usbdp_phy0{
205	u-boot,dm-pre-reloc;
206	status = "okay";
207};
208
209&usbdp_phy0_u3{
210	u-boot,dm-pre-reloc;
211	status = "okay";
212};
213
214/* Support SPL-PINCTRL:
215 * 1. ioc
216 * 2. pinctrl(sdmmc)
217 * 3. gpio if need
218 */
219&ioc {
220	u-boot,dm-spl;
221};
222
223&pinctrl {
224	u-boot,dm-spl;
225	/delete-node/ sdmmc;
226	sdmmc {
227		u-boot,dm-spl;
228		sdmmc_bus4: sdmmc-bus4 {
229			u-boot,dm-spl;
230			rockchip,pins =
231				/* sdmmc_d0 */
232				<4 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
233				/* sdmmc_d1 */
234				<4 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
235				/* sdmmc_d2 */
236				<4 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
237				/* sdmmc_d3 */
238				<4 RK_PD3 1 &pcfg_pull_up_drv_level_2>;
239		};
240
241		sdmmc_clk: sdmmc-clk {
242			u-boot,dm-spl;
243			rockchip,pins =
244				/* sdmmc_clk */
245				<4 RK_PD5 1 &pcfg_pull_up_drv_level_2>;
246		};
247
248		sdmmc_cmd: sdmmc-cmd {
249			u-boot,dm-spl;
250			rockchip,pins =
251				/* sdmmc_cmd */
252				<4 RK_PD4 1 &pcfg_pull_up_drv_level_2>;
253		};
254
255		sdmmc_det: sdmmc-det {
256			u-boot,dm-spl;
257			rockchip,pins =
258				/* sdmmc_det */
259				<0 RK_PA4 1 &pcfg_pull_up>;
260		};
261
262		sdmmc_pwren: sdmmc-pwren {
263			u-boot,dm-spl;
264			rockchip,pins =
265				/* sdmmc_pwren */
266				<0 RK_PA5 2 &pcfg_pull_none>;
267		};
268	};
269};
270
271&pcfg_pull_up_drv_level_2 {
272	u-boot,dm-spl;
273};
274
275&pcfg_pull_up {
276	u-boot,dm-spl;
277};
278
279&pcfg_pull_none
280{
281	u-boot,dm-spl;
282};
283