1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7/ { 8 chosen: chosen { 9 bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 irqchip.gicv3_pseudo_nmi=0"; 10 }; 11 12 cspmu: cspmu@fd10c000 { 13 compatible = "rockchip,cspmu"; 14 reg = <0x0 0xfd10c000 0x0 0x1000>, 15 <0x0 0xfd10d000 0x0 0x1000>, 16 <0x0 0xfd10e000 0x0 0x1000>, 17 <0x0 0xfd10f000 0x0 0x1000>, 18 <0x0 0xfd12c000 0x0 0x1000>, 19 <0x0 0xfd12d000 0x0 0x1000>, 20 <0x0 0xfd12e000 0x0 0x1000>, 21 <0x0 0xfd12f000 0x0 0x1000>; 22 }; 23 24 debug: debug@fd104000 { 25 compatible = "rockchip,debug"; 26 reg = <0x0 0xfd104000 0x0 0x1000>, 27 <0x0 0xfd105000 0x0 0x1000>, 28 <0x0 0xfd106000 0x0 0x1000>, 29 <0x0 0xfd107000 0x0 0x1000>, 30 <0x0 0xfd124000 0x0 0x1000>, 31 <0x0 0xfd125000 0x0 0x1000>, 32 <0x0 0xfd126000 0x0 0x1000>, 33 <0x0 0xfd127000 0x0 0x1000>; 34 }; 35 36 fiq_debugger: fiq-debugger { 37 compatible = "rockchip,fiq-debugger"; 38 rockchip,serial-id = <2>; 39 rockchip,wake-irq = <0>; 40 /* If enable uart uses irq instead of fiq */ 41 rockchip,irq-mode-enable = <1>; 42 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 43 interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_LOW>; 44 pinctrl-names = "default"; 45 pinctrl-0 = <&uart2m0_xfer>; 46 status = "okay"; 47 }; 48 49 firmware { 50 optee: optee { 51 compatible = "linaro,optee-tz"; 52 method = "smc"; 53 }; 54 }; 55 56 minidump: minidump { 57 compatible = "rockchip,minidump"; 58 smem-region = <&minidump_smem>; 59 minidump-region = <&minidump_mem>; 60 status = "disabled"; 61 }; 62 63 reserved-memory { 64 #address-cells = <2>; 65 #size-cells = <2>; 66 ranges; 67 68 cma { 69 compatible = "shared-dma-pool"; 70 reusable; 71 size = <0x0 (8 * 0x100000)>; 72 linux,cma-default; 73 }; 74 75 drm_logo: drm-logo@00000000 { 76 compatible = "rockchip,drm-logo"; 77 reg = <0x0 0x0 0x0 0x0>; 78 }; 79 80 drm_cubic_lut: drm-cubic-lut@00000000 { 81 compatible = "rockchip,drm-cubic-lut"; 82 reg = <0x0 0x0 0x0 0x0>; 83 }; 84 85 vendor_storage_rm: vendor-storage-rm@00000000 { 86 compatible = "rockchip,vendor-storage-rm"; 87 reg = <0x0 0x0 0x0 0x0>; 88 }; 89 90 ramoops: ramoops@110000 { 91 compatible = "ramoops"; 92 /* 0x110000 to 0x1f0000 is for ramoops */ 93 reg = <0x0 0x110000 0x0 0xe0000>; 94 boot-log-size = <0x8000>; /* do not change */ 95 boot-log-count = <0x1>; /* do not change */ 96 console-size = <0x80000>; 97 pmsg-size = <0x30000>; 98 ftrace-size = <0x00000>; 99 record-size = <0x14000>; 100 }; 101 102 minidump_smem: minidump-smem@1f0000 { 103 reg = <0x0 0x1f0000 0x0 0x100>; /* do not change */ 104 no-map; 105 status = "disabled"; 106 }; 107 108 minidump_mem: minidump-mem@c000000 { 109 reg = <0x0 0x0c000000 0x0 0x2000000>; /* changing according to your project */ 110 no-map; 111 status = "disabled"; 112 }; 113 }; 114 115 vendor_storage: vendor-storage { 116 compatible = "rockchip,ram-vendor-storage"; 117 memory-region = <&vendor_storage_rm>; 118 status = "okay"; 119 }; 120}; 121 122&display_subsystem { 123 memory-region = <&drm_logo>; 124 memory-region-names = "drm-logo"; 125}; 126 127&dfi { 128 status = "okay"; 129}; 130 131&dmc { 132 status = "okay"; 133 center-supply = <&vdd_ddr_s0>; 134 mem-supply = <&vdd_log_s0>; 135}; 136 137&rng { 138 status = "okay"; 139}; 140 141&vop { 142 support-multi-area; 143}; 144