1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7/ { 8 chosen: chosen { 9 bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait"; 10 }; 11 12 fiq-debugger { 13 compatible = "rockchip,fiq-debugger"; 14 rockchip,serial-id = <2>; 15 rockchip,wake-irq = <0>; 16 /* If enable uart uses irq instead of fiq */ 17 rockchip,irq-mode-enable = <1>; 18 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 19 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>; 20 pinctrl-names = "default"; 21 pinctrl-0 = <&uart2m0_xfer>; 22 status = "okay"; 23 }; 24 25 debug: debug@fd904000 { 26 compatible = "rockchip,debug"; 27 reg = <0x0 0xfd904000 0x0 0x1000>, 28 <0x0 0xfd905000 0x0 0x1000>, 29 <0x0 0xfd906000 0x0 0x1000>, 30 <0x0 0xfd907000 0x0 0x1000>; 31 }; 32 33 cspmu: cspmu@fd90c000 { 34 compatible = "rockchip,cspmu"; 35 reg = <0x0 0xfd90c000 0x0 0x1000>, 36 <0x0 0xfd90d000 0x0 0x1000>, 37 <0x0 0xfd90e000 0x0 0x1000>, 38 <0x0 0xfd90f000 0x0 0x1000>; 39 }; 40}; 41 42&reserved_memory { 43 ramoops: ramoops@110000 { 44 compatible = "ramoops"; 45 reg = <0x0 0x110000 0x0 0xf0000>; 46 record-size = <0x20000>; 47 console-size = <0x80000>; 48 ftrace-size = <0x00000>; 49 pmsg-size = <0x50000>; 50 }; 51}; 52 53&rng { 54 status = "okay"; 55}; 56