1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7/ { 8 chosen: chosen { 9 bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0"; 10 }; 11 12 aliases { 13 mmc0 = &sdmmc0; 14 mmc1 = &sdmmc1; 15 mmc2 = &sdhci; 16 mmc3 = &sdmmc2; 17 }; 18 19 fiq-debugger { 20 compatible = "rockchip,fiq-debugger"; 21 rockchip,serial-id = <2>; 22 rockchip,wake-irq = <0>; 23 /* If enable uart uses irq instead of fiq */ 24 rockchip,irq-mode-enable = <1>; 25 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 26 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>; 27 pinctrl-names = "default"; 28 pinctrl-0 = <&uart2m0_xfer>; 29 status = "okay"; 30 }; 31 32 firmware { 33 optee: optee { 34 compatible = "linaro,optee-tz"; 35 method = "smc"; 36 }; 37 }; 38 39 debug: debug@fd904000 { 40 compatible = "rockchip,debug"; 41 reg = <0x0 0xfd904000 0x0 0x1000>, 42 <0x0 0xfd905000 0x0 0x1000>, 43 <0x0 0xfd906000 0x0 0x1000>, 44 <0x0 0xfd907000 0x0 0x1000>; 45 }; 46 47 cspmu: cspmu@fd90c000 { 48 compatible = "rockchip,cspmu"; 49 reg = <0x0 0xfd90c000 0x0 0x1000>, 50 <0x0 0xfd90d000 0x0 0x1000>, 51 <0x0 0xfd90e000 0x0 0x1000>, 52 <0x0 0xfd90f000 0x0 0x1000>; 53 }; 54 55 vendor_storage: vendor-storage { 56 compatible = "rockchip,ram-vendor-storage"; 57 memory-region = <&vendor_storage_rm>; 58 status = "okay"; 59 }; 60}; 61 62&reserved_memory { 63 linux,cma { 64 compatible = "shared-dma-pool"; 65 inactive; 66 reusable; 67 reg = <0x0 0x10000000 0x0 0x00800000>; 68 linux,cma-default; 69 }; 70 71 ramoops: ramoops@110000 { 72 compatible = "ramoops"; 73 reg = <0x0 0x110000 0x0 0xf0000>; 74 record-size = <0x20000>; 75 console-size = <0x80000>; 76 ftrace-size = <0x00000>; 77 pmsg-size = <0x50000>; 78 }; 79 80 vendor_storage_rm: vendor-storage-rm@00000000 { 81 compatible = "rockchip,vendor-storage-rm"; 82 reg = <0x0 0x0 0x0 0x0>; 83 }; 84}; 85 86&rng { 87 status = "okay"; 88}; 89 90&rockchip_suspend { 91 status = "okay"; 92}; 93 94&vop { 95 support-multi-area; 96}; 97