xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/rk3562-u-boot.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1/*
2 * (C) Copyright 2022 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier:     GPL-2.0+
5 */
6
7/ {
8	aliases {
9		mmc0 = &sdhci;
10		mmc1 = &sdmmc0;
11	};
12
13	chosen {
14		stdout-path = &uart2;
15		u-boot,spl-boot-order = &sdmmc0, &sdhci, &spi_nand, &spi_nor;
16	};
17
18	secure-otp@ff920000 {
19		compatible = "rockchip,rk3562-secure-otp";
20		reg = <0x0 0xff920000 0x0 0x4000>;
21		secure_conf = <0xff020034>;
22		mask_addr = <0x0>;
23		cru_rst_addr = <0xff130438>;
24		u-boot,dm-spl;
25		status = "okay";
26	};
27};
28
29&sys_grf {
30	u-boot,dm-spl;
31	status = "okay";
32};
33
34&ioc_grf {
35	u-boot,dm-spl;
36	status = "okay";
37};
38
39&pmu_grf {
40	u-boot,dm-spl;
41	status = "okay";
42};
43
44&usbphy_grf {
45	u-boot,dm-pre-reloc;
46	status = "okay";
47};
48
49&firmware {
50	u-boot,dm-spl;
51};
52
53&scmi {
54	u-boot,dm-spl;
55};
56
57&scmi_clk {
58	u-boot,dm-spl;
59};
60
61&scmi_shmem {
62	u-boot,dm-spl;
63};
64
65&cru {
66	u-boot,dm-spl;
67	status = "okay";
68};
69
70&crypto {
71	u-boot,dm-spl;
72	status = "okay";
73};
74
75&rng {
76	u-boot,dm-pre-reloc;
77	status = "okay";
78};
79
80&uart2 {
81	clock-frequency = <24000000>;
82	u-boot,dm-spl;
83	status = "okay";
84};
85
86&saradc0 {
87	u-boot,dm-pre-reloc;
88	status = "okay";
89};
90
91&psci {
92	u-boot,dm-pre-reloc;
93	status = "okay";
94};
95
96&sdhci {
97	bus-width = <8>;
98	u-boot,dm-spl;
99	/delete-property/ pinctrl-names;
100	/delete-property/ pinctrl-0;
101	mmc-hs400-1_8v;
102	mmc-hs400-enhanced-strobe;
103	fixed-emmc-driver-type = <1>;
104	status = "okay";
105};
106
107&sdmmc0 {
108	u-boot,dm-spl;
109	pinctrl-names = "default";
110	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
111	status = "okay";
112};
113
114&sdmmc0_pins {
115	u-boot,dm-spl;
116};
117
118&sdmmc0_bus4 {
119	u-boot,dm-spl;
120};
121
122&sdmmc0_clk {
123	u-boot,dm-spl;
124};
125
126&sdmmc0_cmd {
127	u-boot,dm-spl;
128};
129
130&sdmmc0_det {
131	u-boot,dm-spl;
132};
133
134&sfc {
135	u-boot,dm-spl;
136	status = "okay";
137
138	#address-cells = <1>;
139	#size-cells = <0>;
140	spi_nand: flash@0 {
141		u-boot,dm-spl;
142		compatible = "spi-nand";
143		reg = <0>;
144		spi-tx-bus-width = <1>;
145		spi-rx-bus-width = <4>;
146		spi-max-frequency = <80000000>;
147	};
148
149	spi_nor: flash@1 {
150		u-boot,dm-spl;
151		compatible = "jedec,spi-nor";
152		label = "sfc_nor";
153		reg = <0>;
154		spi-tx-bus-width = <1>;
155		spi-rx-bus-width = <4>;
156		spi-max-frequency = <80000000>;
157	};
158};
159
160&pinctrl {
161	u-boot,dm-spl;
162	status = "okay";
163};
164
165&gpio0 {
166	u-boot,dm-pre-reloc;
167};
168
169&gpio1 {
170	u-boot,dm-pre-reloc;
171};
172
173&gpio2 {
174	u-boot,dm-pre-reloc;
175};
176
177&gpio3 {
178	u-boot,dm-pre-reloc;
179};
180
181&gpio4 {
182	u-boot,dm-pre-reloc;
183};
184
185&pcfg_pull_up_drv_level_2 {
186	u-boot,dm-spl;
187	status = "okay";
188};
189
190&pcfg_pull_up {
191	u-boot,dm-spl;
192	status = "okay";
193};
194
195&u2phy {
196	u-boot,dm-pre-reloc;
197	status = "okay";
198};
199
200&u2phy_otg {
201	u-boot,dm-pre-reloc;
202	status = "okay";
203};
204