1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 * 5 */ 6/ { 7 vcc_mipipwr: vcc-mipipwr-regulator { 8 compatible = "regulator-fixed"; 9 gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; 10 pinctrl-names = "default"; 11 pinctrl-0 = <&mipicam_pwr>; 12 regulator-name = "vcc_mipipwr"; 13 enable-active-high; 14 }; 15}; 16 17&csi2_dphy0 { 18 status = "okay"; 19 20 ports { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 port@0 { 25 reg = <0>; 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 mipi_in_ucam0: endpoint@1 { 30 reg = <1>; 31 remote-endpoint = <&ov13855_out0>; 32 data-lanes = <1 2 3 4>; 33 }; 34 }; 35 36 port@1 { 37 reg = <1>; 38 #address-cells = <1>; 39 #size-cells = <0>; 40 41 csidphy0_out: endpoint@0 { 42 reg = <0>; 43 remote-endpoint = <&mipi0_csi2_input>; 44 data-lanes = <1 2 3 4>; 45 }; 46 }; 47 }; 48}; 49 50&csi2_dphy4 { 51 status = "okay"; 52 53 ports { 54 #address-cells = <1>; 55 #size-cells = <0>; 56 57 port@0 { 58 reg = <0>; 59 #address-cells = <1>; 60 #size-cells = <0>; 61 62 mipi_in_ucam1: endpoint@1 { 63 reg = <1>; 64 remote-endpoint = <&gc8034_out0>; 65 data-lanes = <1 2>; 66 }; 67 }; 68 69 port@1 { 70 reg = <1>; 71 #address-cells = <1>; 72 #size-cells = <0>; 73 74 csidphy4_out: endpoint@0 { 75 reg = <0>; 76 remote-endpoint = <&mipi2_csi2_input>; 77 data-lanes = <1 2>; 78 }; 79 }; 80 }; 81}; 82 83&i2c4 { 84 status = "okay"; 85 pinctrl-names = "default"; 86 pinctrl-0 = <&i2c4m0_xfer>; 87 88 dw9763: dw9763@c { 89 compatible = "dongwoon,dw9763"; 90 status = "okay"; 91 reg = <0x0c>; 92 rockchip,vcm-max-current = <120>; 93 rockchip,vcm-start-current = <20>; 94 rockchip,vcm-rated-current = <90>; 95 rockchip,vcm-step-mode = <3>; 96 rockchip,vcm-t-src = <0x20>; 97 rockchip,vcm-t-div = <1>; 98 rockchip,camera-module-index = <0>; 99 rockchip,camera-module-facing = "back"; 100 }; 101 102 ov13855: ov13855@36 { 103 status = "okay"; 104 compatible = "ovti,ov13855"; 105 reg = <0x36>; 106 clocks = <&cru CLK_CAM0_OUT2IO>; 107 clock-names = "xvclk"; 108 pwdn-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; 109 avdd-supply = <&vcc2v8_dvp>; 110 dovdd-supply = <&vcc_mipipwr>; 111 dvdd-supply = <&vcc1v2_dvp>; 112 rockchip,camera-module-index = <0>; 113 rockchip,camera-module-facing = "back"; 114 rockchip,camera-module-name = "KYT-10203-v1"; 115 rockchip,camera-module-lens-name = "default"; 116 lens-focus = <&dw9763>; 117 118 port { 119 ov13855_out0: endpoint { 120 remote-endpoint = <&mipi_in_ucam0>; 121 data-lanes = <1 2 3 4>; 122 }; 123 }; 124 }; 125 126 gc8034: gc8034@37 { 127 compatible = "galaxycore,gc8034"; 128 status = "okay"; 129 reg = <0x37>; 130 clocks = <&cru CLK_CAM0_OUT2IO>; 131 clock-names = "xvclk"; 132 pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; 133 avdd-supply = <&vcc2v8_dvp>; 134 dovdd-supply = <&vcc_mipipwr>; 135 dvdd-supply = <&vcc1v2_dvp>; 136 rockchip,camera-module-index = <1>; 137 rockchip,camera-module-facing = "front"; 138 rockchip,camera-module-name = "KYT-10203-v1"; 139 rockchip,camera-module-lens-name = "default"; 140 port { 141 gc8034_out0: endpoint { 142 remote-endpoint = <&mipi_in_ucam1>; 143 data-lanes = <1 2>; 144 }; 145 }; 146 }; 147}; 148 149&csi2_dphy0_hw { 150 status = "okay"; 151}; 152 153&csi2_dphy1_hw { 154 status = "okay"; 155}; 156 157&mipi0_csi2 { 158 status = "okay"; 159 160 ports { 161 #address-cells = <1>; 162 #size-cells = <0>; 163 164 port@0 { 165 reg = <0>; 166 #address-cells = <1>; 167 #size-cells = <0>; 168 169 mipi0_csi2_input: endpoint@1 { 170 reg = <1>; 171 remote-endpoint = <&csidphy0_out>; 172 data-lanes = <1 2 3 4>; 173 }; 174 }; 175 176 port@1 { 177 reg = <1>; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 181 mipi0_csi2_output: endpoint@0 { 182 reg = <0>; 183 remote-endpoint = <&cif_mipi_in>; 184 data-lanes = <1 2 3 4>; 185 }; 186 }; 187 }; 188}; 189 190&mipi2_csi2 { 191 status = "okay"; 192 193 ports { 194 #address-cells = <1>; 195 #size-cells = <0>; 196 197 port@0 { 198 reg = <0>; 199 #address-cells = <1>; 200 #size-cells = <0>; 201 202 mipi2_csi2_input: endpoint@1 { 203 reg = <1>; 204 remote-endpoint = <&csidphy4_out>; 205 data-lanes = <1 2>; 206 }; 207 }; 208 209 port@1 { 210 reg = <1>; 211 #address-cells = <1>; 212 #size-cells = <0>; 213 214 mipi2_csi2_output: endpoint@0 { 215 reg = <0>; 216 remote-endpoint = <&cif_mipi_in2>; 217 data-lanes = <1 2>; 218 }; 219 }; 220 }; 221}; 222 223&rkcif { 224 status = "okay"; 225 pinctrl-names = "default"; 226 pinctrl-0 = <&camm0_clk0_out>; 227}; 228 229&rkcif_mipi_lvds { 230 status = "okay"; 231 232 port { 233 cif_mipi_in: endpoint { 234 remote-endpoint = <&mipi0_csi2_output>; 235 }; 236 }; 237}; 238 239&rkcif_mipi_lvds2 { 240 status = "okay"; 241 242 port { 243 cif_mipi_in2: endpoint { 244 remote-endpoint = <&mipi2_csi2_output>; 245 }; 246 }; 247}; 248 249&rkcif_mipi_lvds_sditf { 250 status = "okay"; 251 252 port { 253 mipi_lvds_sditf: endpoint { 254 remote-endpoint = <&isp_vir0_in0>; 255 }; 256 }; 257}; 258 259&rkcif_mipi_lvds2_sditf { 260 status = "okay"; 261 262 port { 263 mipi_lvds2_sditf: endpoint { 264 remote-endpoint = <&isp_vir0_in1>; 265 }; 266 }; 267}; 268 269&rkcif_mmu { 270 status = "okay"; 271}; 272 273&rkisp { 274 status = "okay"; 275}; 276 277&rkisp_mmu { 278 status = "okay"; 279}; 280 281&rkisp_vir0 { 282 status = "okay"; 283 284 port { 285 #address-cells = <1>; 286 #size-cells = <0>; 287 288 isp_vir0_in0: endpoint@0 { 289 reg = <0>; 290 remote-endpoint = <&mipi_lvds_sditf>; 291 }; 292 isp_vir0_in1: endpoint@1 { 293 reg = <1>; 294 remote-endpoint = <&mipi_lvds2_sditf>; 295 }; 296 }; 297}; 298 299&pinctrl { 300 cam { 301 mipicam_pwr: mipicam-pwr { 302 rockchip,pins = 303 /* camera power en */ 304 <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; 305 }; 306 }; 307}; 308