1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7/{ 8 reserved-memory { 9 #address-cells = <2>; 10 #size-cells = <2>; 11 ranges; 12 13 drm_vehicle: drm-vehicle@0{ 14 compatible = "shared-dma-pool"; 15 inactive; 16 reusable; 17 reg = <0x0 (512 * 0x100000) 0x0 (256 * 0x100000)>;//512M ~ 512M+256M 18 linux,cma-default; 19 }; 20 }; 21 22 gpio_det: gpio-det { 23 status = "okay"; 24 25 pinctrl-names = "default"; 26 pinctrl-0 = <&vehicle_gpios>; 27 28 /*if use the reverse, please config this*/ 29 car-reverse { 30 car-reverse-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; 31 linux,debounce-ms = <5>; 32 label = "car-reverse"; 33 gpio,wakeup; 34 }; 35 }; 36 37 vehicle: vehicle { 38 compatible = "rockchip,vehicle"; 39 status = "okay"; 40 41 // pinctrl-names = "default"; 42 // pinctrl-0 = <&camm0_clk0_out>; 43 44 clocks = <&cru ACLK_VICAP>, 45 <&cru HCLK_VICAP>, 46 <&cru DCLK_VICAP>, 47 <&cru CSIRX0_CLK_DATA>, 48 <&cru CSIRX1_CLK_DATA>, 49 <&cru CSIRX2_CLK_DATA>, 50 <&cru CSIRX3_CLK_DATA>; 51 clock-names = "aclk_cif", 52 "hclk_cif", 53 "dclk_cif", 54 "csirx0_data", 55 "csirx1_data", 56 "csirx2_data", 57 "csirx3_data"; 58 resets = <&cru SRST_A_VICAP>, 59 <&cru SRST_H_VICAP>, 60 <&cru SRST_D_VICAP>, 61 <&cru SRST_I0_VICAP>, 62 <&cru SRST_I1_VICAP>, 63 <&cru SRST_I2_VICAP>, 64 <&cru SRST_I3_VICAP>; 65 reset-names = "rst_cif_a", 66 "rst_cif_h", 67 "rst_cif_d", 68 "rst_cif_i0", 69 "rst_cif_i1", 70 "rst_cif_i2", 71 "rst_cif_i3"; 72 power-domains = <&power RK3562_PD_VI>; 73 cif,drop-frames = <4>; //frames to drop 74 cif,chip-id = <2>; /*0:rk3568 1:rk3588 2:rk3562*/ 75 rockchip,grf = <&sys_grf>; 76 rockchip,cru = <&cru>; 77 rockchip,cif = <&rkcif>; 78 rockchip,gpio-det = <&gpio_det>; 79 rockchip,cif-sensor = <&cif_sensor>; 80 rockchip,cif-phy = <&cif_phy>; 81 ad,fix-format = <0>;//0:auto detect,1:pal;2:ntsc;3:720p50;4:720p30;5:720p25 82 /*0:no, 1:90; 2:180; 4:270; 0x10:mirror-y; 0x20:mirror-x*/ 83 vehicle,rotate-mirror = <0x00>; 84 vehicle,crtc_name = "video_port0"; 85 vehicle,plane_name = "Esmart0-win0"; 86 }; 87 88 cif_phy: cif_phy { 89 status = "okay"; 90 91 csi2_dphy0 { 92 status = "okay"; 93 clocks = <&cru CLK_CAM0_OUT2IO>, 94 <&cru PCLK_CSIPHY0>, 95 <&cru PCLK_CSIHOST0>; 96 clock-names = "xvclk", 97 "pclk", 98 "pclk_csi2host"; 99 resets = <&cru SRST_P_CSIPHY0>, 100 <&cru SRST_P_CSIHOST0>; 101 reset-names = "srst_p_csiphy", 102 "srst_csihost_p"; 103 csihost-idx = <0>; 104 rockchip,csi2-dphy = <&csi2_dphy0_hw>; 105 rockchip,csi2 = <&mipi0_csi2>; 106 }; 107 csi2_dphy3 { 108 status = "disabled"; 109 clocks = <&cru CLK_CAM2_OUT2IO>, 110 <&cru PCLK_CSIPHY1>, 111 <&cru PCLK_CSIHOST2>; 112 clock-names = "xvclk", 113 "pclk", 114 "pclk_csi2host"; 115 resets = <&cru SRST_P_CSIPHY1>, 116 <&cru SRST_P_CSIHOST2>; 117 reset-names = "srst_p_csiphy", 118 "srst_csihost_p"; 119 csihost-idx = <2>; 120 rockchip,csi2-dphy = <&csi2_dphy1_hw>; 121 rockchip,csi2 = <&mipi2_csi2>; 122 }; 123 }; 124 125 cif_sensor: cif_sensor { 126 compatible = "rockchip,sensor"; 127 status = "okay"; 128 129 nvp6324 { 130 status = "okay"; 131 // dphy0 132 powerdown-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; 133 pwdn_active = <1>; 134 reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; 135 rst_active = <1>; 136 // dphy3 137 // powerdown-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; 138 // pwdn_active = <1>; 139 // reset-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; 140 // rst_active = <1>; 141 142 orientation = <90>; 143 i2c_add = <0x60>; 144 i2c_chl = <4>; 145 cif_chl = <0>; 146 ad_chl = <0>; 147 mclk_rate = <24>; 148 rockchip,camera-module-defrect0 = <1920 1080 0 0 1920 1080>; 149 }; 150 }; 151}; 152 153&display_subsystem { 154 memory-region = <&drm_logo>, <&drm_vehicle>; 155 memory-region-names = "drm-logo", "drm-vehicle"; 156}; 157 158&i2c4 { 159 status = "okay"; 160}; 161 162&pinctrl { 163 vehicle { 164 vehicle_gpios: vehicle-pins { 165 /* gpios */ 166 rockchip,pins = 167 /* car-reverse */ 168 <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 169 }; 170 }; 171}; 172