1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7/ { 8 vcc_mipicsi0: vcc-mipicsi0-regulator { 9 compatible = "regulator-fixed"; 10 gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; 11 pinctrl-names = "default"; 12 pinctrl-0 = <&mipicsi0_pwr>; 13 regulator-name = "vcc_mipicsi0"; 14 enable-active-high; 15 regulator-always-on; 16 regulator-boot-on; 17 }; 18 19 vcc_mipicsi1: vcc-mipicsi1-regulator { 20 compatible = "regulator-fixed"; 21 gpio = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>; 22 pinctrl-names = "default"; 23 pinctrl-0 = <&mipicsi1_pwr>; 24 regulator-name = "vcc_mipicsi1"; 25 enable-active-high; 26 regulator-always-on; 27 regulator-boot-on; 28 }; 29}; 30 31&csi2_dphy0 { 32 status = "okay"; 33 34 ports { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 port@0 { 38 reg = <0>; 39 #address-cells = <1>; 40 #size-cells = <0>; 41 42 mipi_in_ucam0: endpoint@1 { 43 reg = <1>; 44 remote-endpoint = <&gc8034_out0>; 45 data-lanes = <1 2 3 4>; 46 }; 47 }; 48 port@1 { 49 reg = <1>; 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 csidphy0_out: endpoint@0 { 54 reg = <0>; 55 remote-endpoint = <&mipi0_csi2_input>; 56 }; 57 }; 58 }; 59}; 60 61&csi2_dphy3 { 62 status = "okay"; 63 64 ports { 65 #address-cells = <1>; 66 #size-cells = <0>; 67 port@0 { 68 reg = <0>; 69 #address-cells = <1>; 70 #size-cells = <0>; 71 72 mipi_in_ucam1: endpoint@1 { 73 reg = <1>; 74 remote-endpoint = <&gc8034_out1>; 75 data-lanes = <1 2 3 4>; 76 }; 77 }; 78 port@1 { 79 reg = <1>; 80 #address-cells = <1>; 81 #size-cells = <0>; 82 83 csidphy3_out: endpoint@0 { 84 reg = <0>; 85 remote-endpoint = <&mipi2_csi2_input>; 86 }; 87 }; 88 }; 89}; 90 91&i2c4 { 92 status = "okay"; 93 94 dw9714: dw9714@c { 95 compatible = "dongwoon,dw9714"; 96 status = "okay"; 97 reg = <0x0c>; 98 rockchip,vcm-start-current = <10>; 99 rockchip,vcm-rated-current = <85>; 100 rockchip,vcm-step-mode = <5>; 101 rockchip,camera-module-index = <0>; 102 rockchip,camera-module-facing = "back"; 103 }; 104 105 gc8034: gc8034@37 { 106 compatible = "galaxycore,gc8034"; 107 reg = <0x37>; 108 clocks = <&cru CLK_CAM0_OUT2IO>; 109 clock-names = "xvclk"; 110 pinctrl-names = "default"; 111 pinctrl-0 = <&camm0_clk0_out>; 112 reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; 113 pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; 114 // dvdd-supply = <&vcc_mipicsi0>; 115 rockchip,camera-module-index = <0>; 116 rockchip,camera-module-facing = "back"; 117 rockchip,camera-module-name = "RK-CMK-8M-2-v1"; 118 rockchip,camera-module-lens-name = "CK8401"; 119 lens-focus = <&dw9714>; 120 port { 121 gc8034_out0: endpoint { 122 remote-endpoint = <&mipi_in_ucam0>; 123 data-lanes = <1 2 3 4>; 124 }; 125 }; 126 }; 127}; 128 129&i2c5 { 130 status = "okay"; 131 132 dw9714_1: dw9714_1@c { 133 compatible = "dongwoon,dw9714"; 134 status = "okay"; 135 reg = <0x0c>; 136 rockchip,vcm-start-current = <10>; 137 rockchip,vcm-rated-current = <85>; 138 rockchip,vcm-step-mode = <5>; 139 rockchip,camera-module-index = <1>; 140 rockchip,camera-module-facing = "front"; 141 }; 142 143 gc8034_1: gc8034_1@37 { 144 compatible = "galaxycore,gc8034"; 145 reg = <0x37>; 146 clocks = <&cru CLK_CAM2_OUT2IO>; 147 clock-names = "xvclk"; 148 pinctrl-names = "default"; 149 pinctrl-0 = <&cam_clk2_out>; 150 reset-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; 151 pwdn-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; 152 // dvdd-supply = <&vcc_mipicsi1>; 153 rockchip,camera-module-index = <1>; 154 rockchip,camera-module-facing = "front"; 155 rockchip,camera-module-name = "RK-CMK-8M-2-v1"; 156 rockchip,camera-module-lens-name = "CK8401"; 157 lens-focus = <&dw9714_1>; 158 port { 159 gc8034_out1: endpoint { 160 remote-endpoint = <&mipi_in_ucam1>; 161 data-lanes = <1 2 3 4>; 162 }; 163 }; 164 }; 165}; 166 167&csi2_dphy0_hw { 168 status = "okay"; 169}; 170 171&csi2_dphy1_hw { 172 status = "okay"; 173}; 174 175&mipi0_csi2 { 176 status = "okay"; 177 178 ports { 179 #address-cells = <1>; 180 #size-cells = <0>; 181 182 port@0 { 183 reg = <0>; 184 #address-cells = <1>; 185 #size-cells = <0>; 186 187 mipi0_csi2_input: endpoint@1 { 188 reg = <1>; 189 remote-endpoint = <&csidphy0_out>; 190 }; 191 }; 192 193 port@1 { 194 reg = <1>; 195 #address-cells = <1>; 196 #size-cells = <0>; 197 198 mipi0_csi2_output: endpoint@0 { 199 reg = <0>; 200 remote-endpoint = <&cif_mipi_in0>; 201 }; 202 }; 203 }; 204}; 205 206&mipi2_csi2 { 207 status = "okay"; 208 209 ports { 210 #address-cells = <1>; 211 #size-cells = <0>; 212 213 port@0 { 214 reg = <0>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 218 mipi2_csi2_input: endpoint@1 { 219 reg = <1>; 220 remote-endpoint = <&csidphy3_out>; 221 }; 222 }; 223 224 port@1 { 225 reg = <1>; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 229 mipi2_csi2_output: endpoint@0 { 230 reg = <0>; 231 remote-endpoint = <&cif_mipi_in1>; 232 }; 233 }; 234 }; 235}; 236 237&rkcif { 238 status = "okay"; 239}; 240 241&rkcif_mipi_lvds { 242 status = "okay"; 243 244 port { 245 cif_mipi_in0: endpoint { 246 remote-endpoint = <&mipi0_csi2_output>; 247 }; 248 }; 249}; 250 251&rkcif_mipi_lvds2 { 252 status = "okay"; 253 254 port { 255 cif_mipi_in1: endpoint { 256 remote-endpoint = <&mipi2_csi2_output>; 257 }; 258 }; 259}; 260 261&rkcif_mipi_lvds_sditf { 262 status = "okay"; 263 264 port { 265 mipi_lvds_sditf: endpoint { 266 remote-endpoint = <&isp_vir0>; 267 }; 268 }; 269}; 270 271&rkcif_mipi_lvds2_sditf { 272 status = "okay"; 273 274 port { 275 mipi_lvds2_sditf: endpoint { 276 remote-endpoint = <&isp_vir1>; 277 }; 278 }; 279}; 280 281&rkcif_mmu { 282 status = "okay"; 283}; 284 285&rkisp { 286 status = "okay"; 287}; 288 289&rkisp_mmu { 290 status = "okay"; 291}; 292 293&rkisp_vir0 { 294 status = "okay"; 295 296 port { 297 #address-cells = <1>; 298 #size-cells = <0>; 299 300 isp_vir0: endpoint@0 { 301 reg = <0>; 302 remote-endpoint = <&mipi_lvds_sditf>; 303 }; 304 isp_vir1: endpoint@1 { 305 reg = <1>; 306 remote-endpoint = <&mipi_lvds2_sditf>; 307 }; 308 }; 309}; 310 311&pinctrl { 312 cam { 313 mipicsi0_pwr: mipicsi0-pwr { 314 rockchip,pins = 315 /* camera power en */ 316 <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; 317 }; 318 mipicsi1_pwr: mipicsi1-pwr { 319 rockchip,pins = 320 /* camera1 power en */ 321 <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; 322 }; 323 }; 324}; 325 326