xref: /rk3399_rockchip-uboot/arch/arm/dts/rk3506-pinctrl.dtsi (revision 85e5c21076b78fe71b961926fac1aa66a345c2bf)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/pinctrl/rockchip.h>
7#include "rockchip-pinconf.dtsi"
8
9/*
10 * This file is auto generated by pin2dts tool, please keep these code
11 * by adding changes at end of this file.
12 */
13&pinctrl {
14	aupll_clk {
15		aupll_clk_pins: aupll-clk-pins {
16			rockchip,pins =
17				/* aupll_clk_in */
18				<0 RK_PC4 2 &pcfg_pull_none>;
19		};
20	};
21
22	cpu {
23		cpu_pins: cpu-pins {
24			rockchip,pins =
25				/* cpu_avs */
26				<0 RK_PC5 1 &pcfg_pull_none>;
27		};
28	};
29
30	dsm_aud {
31		dsm_audm0_ln_pins: dsm-audm0-ln-pins {
32			rockchip,pins =
33				/* dsm_aud_ln_m0 */
34				<1 RK_PD0 4 &pcfg_pull_none>;
35		};
36
37		dsm_audm0_lp_pins: dsm-audm0-lp-pins {
38			rockchip,pins =
39				/* dsm_aud_lp_m0 */
40				<1 RK_PD1 4 &pcfg_pull_none>;
41		};
42
43		dsm_audm0_rn_pins: dsm-audm0-rn-pins {
44			rockchip,pins =
45				/* dsm_aud_rn_m0 */
46				<1 RK_PC1 4 &pcfg_pull_none>;
47		};
48
49		dsm_audm0_rp_pins: dsm-audm0-rp-pins {
50			rockchip,pins =
51				/* dsm_aud_rp_m0 */
52				<1 RK_PC2 4 &pcfg_pull_none>;
53		};
54
55		dsm_audm1_ln_pins: dsm-audm1-ln-pins {
56			rockchip,pins =
57				/* dsm_aud_ln_m1 */
58				<2 RK_PB6 2 &pcfg_pull_none>;
59		};
60
61		dsm_audm1_lp_pins: dsm-audm1-lp-pins {
62			rockchip,pins =
63				/* dsm_aud_lp_m1 */
64				<2 RK_PB7 2 &pcfg_pull_none>;
65		};
66
67		dsm_audm1_rn_pins: dsm-audm1-rn-pins {
68			rockchip,pins =
69				/* dsm_aud_rn_m1 */
70				<2 RK_PB4 2 &pcfg_pull_none>;
71		};
72
73		dsm_audm1_rp_pins: dsm-audm1-rp-pins {
74			rockchip,pins =
75				/* dsm_aud_rp_m1 */
76				<2 RK_PB5 2 &pcfg_pull_none>;
77		};
78	};
79
80	dsmc {
81		dsmc_clkn_pins: dsmc-clkn-pins {
82			rockchip,pins =
83				/* dsmc_clkn */
84				<1 RK_PA1 2 &pcfg_pull_none>;
85		};
86		dsmc_clkp_pins: dsmc-clkp-pins {
87			rockchip,pins =
88				/* dsmc_clkp */
89				<1 RK_PA0 2 &pcfg_pull_none>;
90		};
91		dsmc_csn0_pins: dsmc-csn0-pins {
92			rockchip,pins =
93				/* dsmc_csn0 */
94				<1 RK_PB6 2 &pcfg_pull_none>;
95		};
96		dsmc_csn1_pins: dsmc-csn1-pins {
97			rockchip,pins =
98				/* dsmc_csn1 */
99				<1 RK_PB1 2 &pcfg_pull_none>;
100		};
101		dsmc_csn2_pins: dsmc-csn2-pins {
102			rockchip,pins =
103				/* dsmc_csn2 */
104				<1 RK_PD2 2 &pcfg_pull_none>;
105		};
106		dsmc_csn3_pins: dsmc-csn3-pins {
107			rockchip,pins =
108				/* dsmc_csn3 */
109				<1 RK_PD3 2 &pcfg_pull_none>;
110		};
111		dsmc_d0_pins: dsmc-d0-pins {
112			rockchip,pins =
113				/* dsmc_d0 */
114				<1 RK_PA3 2 &pcfg_pull_none>;
115		};
116		dsmc_d1_pins: dsmc-d1-pins {
117			rockchip,pins =
118				/* dsmc_d1 */
119				<1 RK_PA4 2 &pcfg_pull_none>;
120		};
121		dsmc_d2_pins: dsmc-d2-pins {
122			rockchip,pins =
123				/* dsmc_d2 */
124				<1 RK_PA5 2 &pcfg_pull_none>;
125		};
126		dsmc_d3_pins: dsmc-d3-pins {
127			rockchip,pins =
128				/* dsmc_d3 */
129				<1 RK_PA6 2 &pcfg_pull_none>;
130		};
131		dsmc_d4_pins: dsmc-d4-pins {
132			rockchip,pins =
133				/* dsmc_d4 */
134				<1 RK_PA7 2 &pcfg_pull_none>;
135		};
136		dsmc_d5_pins: dsmc-d5-pins {
137			rockchip,pins =
138				/* dsmc_d5 */
139				<1 RK_PB0 2 &pcfg_pull_none>;
140		};
141		dsmc_d6_pins: dsmc-d6-pins {
142			rockchip,pins =
143				/* dsmc_d6 */
144				<1 RK_PB4 2 &pcfg_pull_none>;
145		};
146		dsmc_d7_pins: dsmc-d7-pins {
147			rockchip,pins =
148				/* dsmc_d7 */
149				<1 RK_PB5 2 &pcfg_pull_none>;
150		};
151		dsmc_d8_pins: dsmc-d8-pins {
152			rockchip,pins =
153				/* dsmc_d8 */
154				<1 RK_PC1 2 &pcfg_pull_none>;
155		};
156		dsmc_d9_pins: dsmc-d9-pins {
157			rockchip,pins =
158				/* dsmc_d9 */
159				<1 RK_PC2 2 &pcfg_pull_none>;
160		};
161		dsmc_d10_pins: dsmc-d10-pins {
162			rockchip,pins =
163				/* dsmc_d10 */
164				<1 RK_PC3 2 &pcfg_pull_none>;
165		};
166		dsmc_d11_pins: dsmc-d11-pins {
167			rockchip,pins =
168				/* dsmc_d11 */
169				<1 RK_PC4 2 &pcfg_pull_none>;
170		};
171		dsmc_d12_pins: dsmc-d12-pins {
172			rockchip,pins =
173				/* dsmc_d12 */
174				<1 RK_PC5 2 &pcfg_pull_none>;
175		};
176		dsmc_d13_pins: dsmc-d13-pins {
177			rockchip,pins =
178				/* dsmc_d13 */
179				<1 RK_PC6 2 &pcfg_pull_none>;
180		};
181		dsmc_d14_pins: dsmc-d14-pins {
182			rockchip,pins =
183				/* dsmc_d14 */
184				<1 RK_PC7 2 &pcfg_pull_none>;
185		};
186		dsmc_d15_pins: dsmc-d15-pins {
187			rockchip,pins =
188				/* dsmc_d15 */
189				<1 RK_PD0 2 &pcfg_pull_none>;
190		};
191		dsmc_dqs0_pins: dsmc-dqs0-pins {
192			rockchip,pins =
193				/* dsmc_dqs0 */
194				<1 RK_PA2 2 &pcfg_pull_none>;
195		};
196		dsmc_dqs1_pins: dsmc-dqs1-pins {
197			rockchip,pins =
198				/* dsmc_dqs1 */
199				<1 RK_PD1 2 &pcfg_pull_none>;
200		};
201		dsmc_int0_pins: dsmc-int0-pins {
202			rockchip,pins =
203				/* dsmc_int0 */
204				<1 RK_PA1 4 &pcfg_pull_none>;
205		};
206		dsmc_int1_pins: dsmc-int1-pins {
207			rockchip,pins =
208				/* dsmc_int1 */
209				<1 RK_PC0 4 &pcfg_pull_none>;
210		};
211		dsmc_int2_pins: dsmc-int2-pins {
212			rockchip,pins =
213				/* dsmc_int2 */
214				<1 RK_PB2 2 &pcfg_pull_none>;
215		};
216		dsmc_int3_pins: dsmc-int3-pins {
217			rockchip,pins =
218				/* dsmc_int3 */
219				<1 RK_PB3 2 &pcfg_pull_none>;
220		};
221		dsmc_rdyn_pins: dsmc-rdyn-pins {
222			rockchip,pins =
223				/* dsmc_rdyn */
224				<1 RK_PB7 2 &pcfg_pull_none>;
225		};
226		dsmc_resetn_pins: dsmc-resetn-pins {
227			rockchip,pins =
228				/* dsmc_resetn */
229				<1 RK_PC0 2 &pcfg_pull_none>;
230		};
231	};
232
233	dsmc_slv {
234		dsmc_slv_clk_pins: dsmc-slv-clk-pins {
235			rockchip,pins =
236				/* dsmc_slv_clk */
237				<1 RK_PC0 8 &pcfg_pull_none>;
238		};
239		dsmc_slv_csn0_pins: dsmc-slv-csn0-pins {
240			rockchip,pins =
241				/* dsmc_slv_csn0 */
242				<1 RK_PD2 8 &pcfg_pull_none>;
243		};
244		dsmc_slv_d0_pins: dsmc-slv-d0-pins {
245			rockchip,pins =
246				/* dsmc_slv_d0 */
247				<1 RK_PC2 8 &pcfg_pull_none>;
248		};
249		dsmc_slv_d1_pins: dsmc-slv-d1-pins {
250			rockchip,pins =
251				/* dsmc_slv_d1 */
252				<1 RK_PC3 8 &pcfg_pull_none>;
253		};
254		dsmc_slv_d2_pins: dsmc-slv-d2-pins {
255			rockchip,pins =
256				/* dsmc_slv_d2 */
257				<1 RK_PC4 8 &pcfg_pull_none>;
258		};
259		dsmc_slv_d3_pins: dsmc-slv-d3-pins {
260			rockchip,pins =
261				/* dsmc_slv_d3 */
262				<1 RK_PC5 8 &pcfg_pull_none>;
263		};
264		dsmc_slv_d4_pins: dsmc-slv-d4-pins {
265			rockchip,pins =
266				/* dsmc_slv_d4 */
267				<1 RK_PC6 8 &pcfg_pull_none>;
268		};
269		dsmc_slv_d5_pins: dsmc-slv-d5-pins {
270			rockchip,pins =
271				/* dsmc_slv_d5 */
272				<1 RK_PC7 8 &pcfg_pull_none>;
273		};
274		dsmc_slv_d6_pins: dsmc-slv-d6-pins {
275			rockchip,pins =
276				/* dsmc_slv_d6 */
277				<1 RK_PD0 8 &pcfg_pull_none>;
278		};
279		dsmc_slv_d7_pins: dsmc-slv-d7-pins {
280			rockchip,pins =
281				/* dsmc_slv_d7 */
282				<1 RK_PD1 8 &pcfg_pull_none>;
283		};
284		dsmc_slv_dqs0_pins: dsmc-slv-dqs0-pins {
285			rockchip,pins =
286				/* dsmc_slv_dqs0 */
287				<1 RK_PC1 8 &pcfg_pull_none>;
288		};
289		dsmc_slv_int_pins: dsmc-slv-int-pins {
290			rockchip,pins =
291				/* dsmc_slv_int */
292				<1 RK_PA1 8 &pcfg_pull_none>;
293		};
294		dsmc_slv_rdyn_pins: dsmc-slv-rdyn-pins {
295			rockchip,pins =
296				/* dsmc_slv_rdyn */
297				<1 RK_PD3 8 &pcfg_pull_none>;
298		};
299	};
300
301	eth_clk0_25m {
302		eth_clk0_25m_out_pins: eth-clk0-25m-out-pins {
303			rockchip,pins =
304				/* eth_clk0_25m_out */
305				<0 RK_PC4 1 &pcfg_pull_none>;
306		};
307	};
308
309	eth_clk1_25m {
310		eth_clk1_25m_out_pins: eth-clk1-25m-out-pins {
311			rockchip,pins =
312				/* eth_clk1_25m_out */
313				<0 RK_PC3 1 &pcfg_pull_none>;
314		};
315	};
316
317	eth_rmii0 {
318		eth_rmii0_rmii0_rx_bus2_pins: eth-rmii0-rmii0-rx-bus2-pins {
319			rockchip,pins =
320				/* eth_rmii0_rxd0 */
321				<2 RK_PB0 1 &pcfg_pull_none>,
322				/* eth_rmii0_rxd1 */
323				<2 RK_PB1 1 &pcfg_pull_none>,
324				/* eth_rmii0_rxdvcrs */
325				<2 RK_PC0 1 &pcfg_pull_none>;
326		};
327
328		eth_rmii0_rmii0_tx_bus2_pins: eth-rmii0-rmii0-tx-bus2-pins {
329			rockchip,pins =
330				/* eth_rmii0_txd0 */
331				<2 RK_PB3 1 &pcfg_pull_none>,
332				/* eth_rmii0_txd1 */
333				<2 RK_PB4 1 &pcfg_pull_none>,
334				/* eth_rmii0_txen */
335				<2 RK_PB5 1 &pcfg_pull_none>;
336		};
337
338		eth_rmii0_clk_pins: eth-rmii0-clk-pins {
339			rockchip,pins =
340				/* eth_rmii0_clk */
341				<2 RK_PB2 1 &pcfg_pull_none>;
342		};
343		eth_rmii0_mdc_pins: eth-rmii0-mdc-pins {
344			rockchip,pins =
345				/* eth_rmii0_mdc */
346				<2 RK_PB6 1 &pcfg_pull_none>;
347		};
348		eth_rmii0_mdio_pins: eth-rmii0-mdio-pins {
349			rockchip,pins =
350				/* eth_rmii0_mdio */
351				<2 RK_PB7 1 &pcfg_pull_none>;
352		};
353	};
354
355	eth_rmii1 {
356		eth_rmii1_rmii1_rx_bus2_pins: eth-rmii1-rmii1-rx-bus2-pins {
357			rockchip,pins =
358				/* eth_rmii1_rxd0 */
359				<3 RK_PA6 2 &pcfg_pull_none>,
360				/* eth_rmii1_rxd1 */
361				<3 RK_PA7 2 &pcfg_pull_none>,
362				/* eth_rmii1_rxdvcrs */
363				<3 RK_PB6 2 &pcfg_pull_none>;
364		};
365
366		eth_rmii1_rmii1_tx_bus2_pins: eth-rmii1-rmii1-tx-bus2-pins {
367			rockchip,pins =
368				/* eth_rmii1_txd0 */
369				<3 RK_PB1 2 &pcfg_pull_none>,
370				/* eth_rmii1_txd1 */
371				<3 RK_PB2 2 &pcfg_pull_none>,
372				/* eth_rmii1_txen */
373				<3 RK_PB3 2 &pcfg_pull_none>;
374		};
375
376		eth_rmii1_clk_pins: eth-rmii1-clk-pins {
377			rockchip,pins =
378				/* eth_rmii1_clk */
379				<3 RK_PB0 2 &pcfg_pull_none>;
380		};
381		eth_rmii1_mdc_pins: eth-rmii1-mdc-pins {
382			rockchip,pins =
383				/* eth_rmii1_mdc */
384				<3 RK_PB4 2 &pcfg_pull_none>;
385		};
386		eth_rmii1_mdio_pins: eth-rmii1-mdio-pins {
387			rockchip,pins =
388				/* eth_rmii1_mdio */
389				<3 RK_PB5 2 &pcfg_pull_none>;
390		};
391	};
392
393	flexbus0 {
394		flexbus0m0_pins: flexbus0m0-pins {
395			rockchip,pins =
396				/* flexbus0_csn_m0 */
397				<1 RK_PB0 5 &pcfg_pull_none>;
398		};
399
400		flexbus0m1_pins: flexbus0m1-pins {
401			rockchip,pins =
402				/* flexbus0_csn_m1 */
403				<1 RK_PB2 5 &pcfg_pull_none>;
404		};
405
406		flexbus0m2_pins: flexbus0m2-pins {
407			rockchip,pins =
408				/* flexbus0_csn_m2 */
409				<1 RK_PB4 5 &pcfg_pull_none>;
410		};
411
412		flexbus0m3_pins: flexbus0m3-pins {
413			rockchip,pins =
414				/* flexbus0_csn_m3 */
415				<1 RK_PB6 5 &pcfg_pull_none>;
416		};
417
418		flexbus0m4_pins: flexbus0m4-pins {
419			rockchip,pins =
420				/* flexbus0_csn_m4 */
421				<1 RK_PC0 5 &pcfg_pull_none>;
422		};
423
424		flexbus0m5_pins: flexbus0m5-pins {
425			rockchip,pins =
426				/* flexbus0_csn_m5 */
427				<1 RK_PC2 5 &pcfg_pull_none>;
428		};
429
430		flexbus0_clk_pins: flexbus0-clk-pins {
431			rockchip,pins =
432				/* flexbus0_clk */
433				<1 RK_PC1 3 &pcfg_pull_none>;
434		};
435		flexbus0_d0_pins: flexbus0-d0-pins {
436			rockchip,pins =
437				/* flexbus0_d0 */
438				<1 RK_PD3 3 &pcfg_pull_none>;
439		};
440		flexbus0_d1_pins: flexbus0-d1-pins {
441			rockchip,pins =
442				/* flexbus0_d1 */
443				<1 RK_PD2 3 &pcfg_pull_none>;
444		};
445		flexbus0_d2_pins: flexbus0-d2-pins {
446			rockchip,pins =
447				/* flexbus0_d2 */
448				<1 RK_PD1 3 &pcfg_pull_none>;
449		};
450		flexbus0_d3_pins: flexbus0-d3-pins {
451			rockchip,pins =
452				/* flexbus0_d3 */
453				<1 RK_PD0 3 &pcfg_pull_none>;
454		};
455		flexbus0_d4_pins: flexbus0-d4-pins {
456			rockchip,pins =
457				/* flexbus0_d4 */
458				<1 RK_PC7 3 &pcfg_pull_none>;
459		};
460		flexbus0_d5_pins: flexbus0-d5-pins {
461			rockchip,pins =
462				/* flexbus0_d5 */
463				<1 RK_PC6 3 &pcfg_pull_none>;
464		};
465		flexbus0_d6_pins: flexbus0-d6-pins {
466			rockchip,pins =
467				/* flexbus0_d6 */
468				<1 RK_PC5 3 &pcfg_pull_none>;
469		};
470		flexbus0_d7_pins: flexbus0-d7-pins {
471			rockchip,pins =
472				/* flexbus0_d7 */
473				<1 RK_PC4 3 &pcfg_pull_none>;
474		};
475		flexbus0_d8_pins: flexbus0-d8-pins {
476			rockchip,pins =
477				/* flexbus0_d8 */
478				<1 RK_PC3 3 &pcfg_pull_none>;
479		};
480		flexbus0_d9_pins: flexbus0-d9-pins {
481			rockchip,pins =
482				/* flexbus0_d9 */
483				<1 RK_PC2 3 &pcfg_pull_none>;
484		};
485		flexbus0_d10_pins: flexbus0-d10-pins {
486			rockchip,pins =
487				/* flexbus0_d10 */
488				<1 RK_PB7 4 &pcfg_pull_none>;
489		};
490		flexbus0_d11_pins: flexbus0-d11-pins {
491			rockchip,pins =
492				/* flexbus0_d11 */
493				<1 RK_PB6 4 &pcfg_pull_none>;
494		};
495		flexbus0_d12_pins: flexbus0-d12-pins {
496			rockchip,pins =
497				/* flexbus0_d12 */
498				<1 RK_PB5 4 &pcfg_pull_none>;
499		};
500		flexbus0_d13_pins: flexbus0-d13-pins {
501			rockchip,pins =
502				/* flexbus0_d13 */
503				<1 RK_PB4 4 &pcfg_pull_none>;
504		};
505		flexbus0_d14_pins: flexbus0-d14-pins {
506			rockchip,pins =
507				/* flexbus0_d14 */
508				<1 RK_PB3 4 &pcfg_pull_none>;
509		};
510		flexbus0_d15_pins: flexbus0-d15-pins {
511			rockchip,pins =
512				/* flexbus0_d15 */
513				<1 RK_PB2 4 &pcfg_pull_none>;
514		};
515	};
516
517	flexbus1 {
518		flexbus1m0_pins: flexbus1m0-pins {
519			rockchip,pins =
520				/* flexbus1_csn_m0 */
521				<1 RK_PB1 5 &pcfg_pull_none>;
522		};
523
524		flexbus1m1_pins: flexbus1m1-pins {
525			rockchip,pins =
526				/* flexbus1_csn_m1 */
527				<1 RK_PB3 5 &pcfg_pull_none>;
528		};
529
530		flexbus1m2_pins: flexbus1m2-pins {
531			rockchip,pins =
532				/* flexbus1_csn_m2 */
533				<1 RK_PB5 5 &pcfg_pull_none>;
534		};
535
536		flexbus1m3_pins: flexbus1m3-pins {
537			rockchip,pins =
538				/* flexbus1_csn_m3 */
539				<1 RK_PB7 5 &pcfg_pull_none>;
540		};
541
542		flexbus1m4_pins: flexbus1m4-pins {
543			rockchip,pins =
544				/* flexbus1_csn_m4 */
545				<1 RK_PC1 5 &pcfg_pull_none>;
546		};
547
548		flexbus1m5_pins: flexbus1m5-pins {
549			rockchip,pins =
550				/* flexbus1_csn_m5 */
551				<1 RK_PC3 5 &pcfg_pull_none>;
552		};
553
554		flexbus1_clk_pins: flexbus1-clk-pins {
555			rockchip,pins =
556				/* flexbus1_clk */
557				<1 RK_PC0 3 &pcfg_pull_none>;
558		};
559		flexbus1_d0_pins: flexbus1-d0-pins {
560			rockchip,pins =
561				/* flexbus1_d0 */
562				<1 RK_PA0 3 &pcfg_pull_none>;
563		};
564		flexbus1_d1_pins: flexbus1-d1-pins {
565			rockchip,pins =
566				/* flexbus1_d1 */
567				<1 RK_PA1 3 &pcfg_pull_none>;
568		};
569		flexbus1_d2_pins: flexbus1-d2-pins {
570			rockchip,pins =
571				/* flexbus1_d2 */
572				<1 RK_PA2 3 &pcfg_pull_none>;
573		};
574		flexbus1_d3_pins: flexbus1-d3-pins {
575			rockchip,pins =
576				/* flexbus1_d3 */
577				<1 RK_PA3 3 &pcfg_pull_none>;
578		};
579		flexbus1_d4_pins: flexbus1-d4-pins {
580			rockchip,pins =
581				/* flexbus1_d4 */
582				<1 RK_PA4 3 &pcfg_pull_none>;
583		};
584		flexbus1_d5_pins: flexbus1-d5-pins {
585			rockchip,pins =
586				/* flexbus1_d5 */
587				<1 RK_PA5 3 &pcfg_pull_none>;
588		};
589		flexbus1_d6_pins: flexbus1-d6-pins {
590			rockchip,pins =
591				/* flexbus1_d6 */
592				<1 RK_PA6 3 &pcfg_pull_none>;
593		};
594		flexbus1_d7_pins: flexbus1-d7-pins {
595			rockchip,pins =
596				/* flexbus1_d7 */
597				<1 RK_PA7 3 &pcfg_pull_none>;
598		};
599		flexbus1_d8_pins: flexbus1-d8-pins {
600			rockchip,pins =
601				/* flexbus1_d8 */
602				<1 RK_PB0 3 &pcfg_pull_none>;
603		};
604		flexbus1_d9_pins: flexbus1-d9-pins {
605			rockchip,pins =
606				/* flexbus1_d9 */
607				<1 RK_PB1 3 &pcfg_pull_none>;
608		};
609		flexbus1_d10_pins: flexbus1-d10-pins {
610			rockchip,pins =
611				/* flexbus1_d10 */
612				<1 RK_PB2 3 &pcfg_pull_none>;
613		};
614		flexbus1_d11_pins: flexbus1-d11-pins {
615			rockchip,pins =
616				/* flexbus1_d11 */
617				<1 RK_PB3 3 &pcfg_pull_none>;
618		};
619		flexbus1_d12_pins: flexbus1-d12-pins {
620			rockchip,pins =
621				/* flexbus1_d12 */
622				<1 RK_PB4 3 &pcfg_pull_none>;
623		};
624		flexbus1_d13_pins: flexbus1-d13-pins {
625			rockchip,pins =
626				/* flexbus1_d13 */
627				<1 RK_PB5 3 &pcfg_pull_none>;
628		};
629		flexbus1_d14_pins: flexbus1-d14-pins {
630			rockchip,pins =
631				/* flexbus1_d14 */
632				<1 RK_PB6 3 &pcfg_pull_none>;
633		};
634		flexbus1_d15_pins: flexbus1-d15-pins {
635			rockchip,pins =
636				/* flexbus1_d15 */
637				<1 RK_PB7 3 &pcfg_pull_none>;
638		};
639	};
640
641	fspi {
642		fspi_bus4_pins: fspi-bus4-pins {
643			rockchip,pins =
644				/* fspi_d0 */
645				<2 RK_PA2 1 &pcfg_pull_none>,
646				/* fspi_d1 */
647				<2 RK_PA3 1 &pcfg_pull_none>,
648				/* fspi_d2 */
649				<2 RK_PA4 1 &pcfg_pull_none>,
650				/* fspi_d3 */
651				<2 RK_PA5 1 &pcfg_pull_none>;
652		};
653
654		fspi_clk_pins: fspi-clk-pins {
655			rockchip,pins =
656				/* fspi_clk */
657				<2 RK_PA1 1 &pcfg_pull_none>;
658		};
659		fspi_csn_pins: fspi-csn-pins {
660			rockchip,pins =
661				/* fspi_csn */
662				<2 RK_PA0 1 &pcfg_pull_none>;
663		};
664	};
665
666	jtag {
667		jtagm0_pins: jtagm0-pins {
668			rockchip,pins =
669				/* jtag_tck_m0 */
670				<3 RK_PA4 2 &pcfg_pull_none>,
671				/* jtag_tms_m0 */
672				<3 RK_PA5 2 &pcfg_pull_none>;
673		};
674
675		jtagm1_pins: jtagm1-pins {
676			rockchip,pins =
677				/* jtag_tck_m1 */
678				<0 RK_PC6 2 &pcfg_pull_none>,
679				/* jtag_tms_m1 */
680				<0 RK_PC7 2 &pcfg_pull_none>;
681		};
682	};
683
684	ref_clk1 {
685		ref_clk1_pins: ref-clk1-pins {
686			rockchip,pins =
687				/* ref_clk1_out */
688				<0 RK_PC2 1 &pcfg_pull_none>;
689		};
690	};
691
692	rm {
693		rm_io0_pins: rm-io0-pins {
694			rockchip,pins =
695				/* rm_io0 */
696				<0 RK_PA0 7 &pcfg_pull_none>;
697		};
698		rm_io1_pins: rm-io1-pins {
699			rockchip,pins =
700				/* rm_io1 */
701				<0 RK_PA1 7 &pcfg_pull_none>;
702		};
703		rm_io2_pins: rm-io2-pins {
704			rockchip,pins =
705				/* rm_io2 */
706				<0 RK_PA2 7 &pcfg_pull_none>;
707		};
708		rm_io3_pins: rm-io3-pins {
709			rockchip,pins =
710				/* rm_io3 */
711				<0 RK_PA3 7 &pcfg_pull_none>;
712		};
713		rm_io4_pins: rm-io4-pins {
714			rockchip,pins =
715				/* rm_io4 */
716				<0 RK_PA4 7 &pcfg_pull_none>;
717		};
718		rm_io5_pins: rm-io5-pins {
719			rockchip,pins =
720				/* rm_io5 */
721				<0 RK_PA5 7 &pcfg_pull_none>;
722		};
723		rm_io6_pins: rm-io6-pins {
724			rockchip,pins =
725				/* rm_io6 */
726				<0 RK_PA6 7 &pcfg_pull_none>;
727		};
728		rm_io7_pins: rm-io7-pins {
729			rockchip,pins =
730				/* rm_io7 */
731				<0 RK_PA7 7 &pcfg_pull_none>;
732		};
733		rm_io8_pins: rm-io8-pins {
734			rockchip,pins =
735				/* rm_io8 */
736				<0 RK_PB0 7 &pcfg_pull_none>;
737		};
738		rm_io9_pins: rm-io9-pins {
739			rockchip,pins =
740				/* rm_io9 */
741				<0 RK_PB1 7 &pcfg_pull_none>;
742		};
743		rm_io10_pins: rm-io10-pins {
744			rockchip,pins =
745				/* rm_io10 */
746				<0 RK_PB2 7 &pcfg_pull_none>;
747		};
748		rm_io11_pins: rm-io11-pins {
749			rockchip,pins =
750				/* rm_io11 */
751				<0 RK_PB3 7 &pcfg_pull_none>;
752		};
753		rm_io12_pins: rm-io12-pins {
754			rockchip,pins =
755				/* rm_io12 */
756				<0 RK_PB4 7 &pcfg_pull_none>;
757		};
758		rm_io13_pins: rm-io13-pins {
759			rockchip,pins =
760				/* rm_io13 */
761				<0 RK_PB5 7 &pcfg_pull_none>;
762		};
763		rm_io14_pins: rm-io14-pins {
764			rockchip,pins =
765				/* rm_io14 */
766				<0 RK_PB6 7 &pcfg_pull_none>;
767		};
768		rm_io15_pins: rm-io15-pins {
769			rockchip,pins =
770				/* rm_io15 */
771				<0 RK_PB7 7 &pcfg_pull_none>;
772		};
773		rm_io16_pins: rm-io16-pins {
774			rockchip,pins =
775				/* rm_io16 */
776				<0 RK_PC0 7 &pcfg_pull_none>;
777		};
778		rm_io17_pins: rm-io17-pins {
779			rockchip,pins =
780				/* rm_io17 */
781				<0 RK_PC1 7 &pcfg_pull_none>;
782		};
783		rm_io18_pins: rm-io18-pins {
784			rockchip,pins =
785				/* rm_io18 */
786				<0 RK_PC2 7 &pcfg_pull_none>;
787		};
788		rm_io19_pins: rm-io19-pins {
789			rockchip,pins =
790				/* rm_io19 */
791				<0 RK_PC3 7 &pcfg_pull_none>;
792		};
793		rm_io20_pins: rm-io20-pins {
794			rockchip,pins =
795				/* rm_io20 */
796				<0 RK_PC4 7 &pcfg_pull_none>;
797		};
798		rm_io21_pins: rm-io21-pins {
799			rockchip,pins =
800				/* rm_io21 */
801				<0 RK_PC5 7 &pcfg_pull_none>;
802		};
803		rm_io22_pins: rm-io22-pins {
804			rockchip,pins =
805				/* rm_io22 */
806				<0 RK_PC6 7 &pcfg_pull_none>;
807		};
808		rm_io23_pins: rm-io23-pins {
809			rockchip,pins =
810				/* rm_io23 */
811				<0 RK_PC7 7 &pcfg_pull_none>;
812		};
813		rm_io24_pins: rm-io24-pins {
814			rockchip,pins =
815				/* rm_io24 */
816				<1 RK_PB1 7 &pcfg_pull_none>;
817		};
818		rm_io25_pins: rm-io25-pins {
819			rockchip,pins =
820				/* rm_io25 */
821				<1 RK_PB2 7 &pcfg_pull_none>;
822		};
823		rm_io26_pins: rm-io26-pins {
824			rockchip,pins =
825				/* rm_io26 */
826				<1 RK_PB3 7 &pcfg_pull_none>;
827		};
828		rm_io27_pins: rm-io27-pins {
829			rockchip,pins =
830				/* rm_io27 */
831				<1 RK_PC2 7 &pcfg_pull_none>;
832		};
833		rm_io28_pins: rm-io28-pins {
834			rockchip,pins =
835				/* rm_io28 */
836				<1 RK_PC3 7 &pcfg_pull_none>;
837		};
838		rm_io29_pins: rm-io29-pins {
839			rockchip,pins =
840				/* rm_io29 */
841				<1 RK_PD1 7 &pcfg_pull_none>;
842		};
843		rm_io30_pins: rm-io30-pins {
844			rockchip,pins =
845				/* rm_io30 */
846				<1 RK_PD2 7 &pcfg_pull_none>;
847		};
848		rm_io31_pins: rm-io31-pins {
849			rockchip,pins =
850				/* rm_io31 */
851				<1 RK_PD3 7 &pcfg_pull_none>;
852		};
853	};
854
855	sai0 {
856		sai0_lrck_pins: sai0-lrck-pins {
857			rockchip,pins =
858				/* sai0_lrck */
859				<0 RK_PA0 1 &pcfg_pull_none>;
860		};
861
862		sai0_mclk_pins: sai0-mclk-pins {
863			rockchip,pins =
864				/* sai0_mclk */
865				<0 RK_PA2 1 &pcfg_pull_none>;
866		};
867
868		sai0_sclk_pins: sai0-sclk-pins {
869			rockchip,pins =
870				/* sai0_sclk */
871				<0 RK_PA1 1 &pcfg_pull_none>;
872		};
873
874		sai0_sdi0_pins: sai0-sdi0-pins {
875			rockchip,pins =
876				/* sai0_sdi0 */
877				<0 RK_PA4 1 &pcfg_pull_none>;
878		};
879
880		sai0_sdi1_pins: sai0-sdi1-pins {
881			rockchip,pins =
882				/* sai0_sdi1 */
883				<0 RK_PA5 1 &pcfg_pull_none>;
884		};
885
886		sai0_sdi2_pins: sai0-sdi2-pins {
887			rockchip,pins =
888				/* sai0_sdi2 */
889				<0 RK_PA6 1 &pcfg_pull_none>;
890		};
891
892		sai0_sdi3_pins: sai0-sdi3-pins {
893			rockchip,pins =
894				/* sai0_sdi3 */
895				<0 RK_PA7 1 &pcfg_pull_none>;
896		};
897
898		sai0_sdo_pins: sai0-sdo-pins {
899			rockchip,pins =
900				/* sai0_sdo */
901				<0 RK_PA3 1 &pcfg_pull_none>;
902		};
903	};
904
905	sai1 {
906		sai1_lrck_pins: sai1-lrck-pins {
907			rockchip,pins =
908				/* sai1_lrck */
909				<0 RK_PB2 1 &pcfg_pull_none>;
910		};
911
912		sai1_mclk_pins: sai1-mclk-pins {
913			rockchip,pins =
914				/* sai1_mclk */
915				<0 RK_PB0 1 &pcfg_pull_none>;
916		};
917
918		sai1_sclk_pins: sai1-sclk-pins {
919			rockchip,pins =
920				/* sai1_sclk */
921				<0 RK_PB1 1 &pcfg_pull_none>;
922		};
923
924		sai1_sdo0_pins: sai1-sdo0-pins {
925			rockchip,pins =
926				/* sai1_sdo0 */
927				<0 RK_PB4 1 &pcfg_pull_none>;
928		};
929
930		sai1_sdo1_pins: sai1-sdo1-pins {
931			rockchip,pins =
932				/* sai1_sdo1 */
933				<0 RK_PB5 1 &pcfg_pull_none>;
934		};
935
936		sai1_sdo2_pins: sai1-sdo2-pins {
937			rockchip,pins =
938				/* sai1_sdo2 */
939				<0 RK_PB6 1 &pcfg_pull_none>;
940		};
941
942		sai1_sdo3_pins: sai1-sdo3-pins {
943			rockchip,pins =
944				/* sai1_sdo3 */
945				<0 RK_PB7 1 &pcfg_pull_none>;
946		};
947
948		sai1_sdi_pins: sai1-sdi-pins {
949			rockchip,pins =
950				/* sai1_sdi */
951				<0 RK_PB3 1 &pcfg_pull_none>;
952		};
953	};
954
955	sai2 {
956		sai2m0_lrck_pins: sai2m0-lrck-pins {
957			rockchip,pins =
958				/* sai2_lrck_m0 */
959				<3 RK_PB1 1 &pcfg_pull_none>;
960		};
961
962		sai2m0_mclk_pins: sai2m0-mclk-pins {
963			rockchip,pins =
964				/* sai2_mclk_m0 */
965				<3 RK_PB6 1 &pcfg_pull_none>;
966		};
967
968		sai2m0_sclk_pins: sai2m0-sclk-pins {
969			rockchip,pins =
970				/* sai2_sclk_m0 */
971				<3 RK_PA7 1 &pcfg_pull_none>;
972		};
973
974		sai2m0_sdi_pins: sai2m0-sdi-pins {
975			rockchip,pins =
976				/* sai2m0_sdi */
977				<3 RK_PA6 1 &pcfg_pull_none>;
978		};
979		sai2m0_sdo_pins: sai2m0-sdo-pins {
980			rockchip,pins =
981				/* sai2m0_sdo */
982				<3 RK_PB0 1 &pcfg_pull_none>;
983		};
984
985		sai2m1_lrck_pins: sai2m1-lrck-pins {
986			rockchip,pins =
987				/* sai2_lrck_m1 */
988				<1 RK_PB3 6 &pcfg_pull_none>;
989		};
990
991		sai2m1_mclk_pins: sai2m1-mclk-pins {
992			rockchip,pins =
993				/* sai2_mclk_m1 */
994				<1 RK_PC1 6 &pcfg_pull_none>;
995		};
996
997		sai2m1_sclk_pins: sai2m1-sclk-pins {
998			rockchip,pins =
999				/* sai2_sclk_m1 */
1000				<1 RK_PB2 6 &pcfg_pull_none>;
1001		};
1002
1003		sai2m1_sdi_pins: sai2m1-sdi-pins {
1004			rockchip,pins =
1005				/* sai2m1_sdi */
1006				<1 RK_PC2 6 &pcfg_pull_none>;
1007		};
1008		sai2m1_sdo_pins: sai2m1-sdo-pins {
1009			rockchip,pins =
1010				/* sai2m1_sdo */
1011				<1 RK_PC3 6 &pcfg_pull_none>;
1012		};
1013	};
1014
1015	sai3 {
1016		sai3_lrck_pins: sai3-lrck-pins {
1017			rockchip,pins =
1018				/* sai3_lrck */
1019				<2 RK_PB5 3 &pcfg_pull_none>;
1020		};
1021
1022		sai3_mclk_pins: sai3-mclk-pins {
1023			rockchip,pins =
1024				/* sai3_mclk */
1025				<2 RK_PC0 3 &pcfg_pull_none>;
1026		};
1027
1028		sai3_sclk_pins: sai3-sclk-pins {
1029			rockchip,pins =
1030				/* sai3_sclk */
1031				<2 RK_PB4 3 &pcfg_pull_none>;
1032		};
1033
1034		sai3_sdi_pins: sai3-sdi-pins {
1035			rockchip,pins =
1036				/* sai3_sdi */
1037				<2 RK_PB6 3 &pcfg_pull_none>;
1038		};
1039		sai3_sdo_pins: sai3-sdo-pins {
1040			rockchip,pins =
1041				/* sai3_sdo */
1042				<2 RK_PB7 3 &pcfg_pull_none>;
1043		};
1044	};
1045
1046	sdmmc {
1047		sdmmc_bus4_pins: sdmmc-bus4-pins {
1048			rockchip,pins =
1049				/* sdmmc_d0 */
1050				<3 RK_PA2 1 &pcfg_pull_none>,
1051				/* sdmmc_d1 */
1052				<3 RK_PA3 1 &pcfg_pull_none>,
1053				/* sdmmc_d2 */
1054				<3 RK_PA4 1 &pcfg_pull_none>,
1055				/* sdmmc_d3 */
1056				<3 RK_PA5 1 &pcfg_pull_none>;
1057		};
1058
1059		sdmmc_clk_pins: sdmmc-clk-pins {
1060			rockchip,pins =
1061				/* sdmmc_clk */
1062				<3 RK_PA0 1 &pcfg_pull_none>;
1063		};
1064		sdmmc_cmd_pins: sdmmc-cmd-pins {
1065			rockchip,pins =
1066				/* sdmmc_cmd */
1067				<3 RK_PA1 1 &pcfg_pull_none>;
1068		};
1069	};
1070
1071	spi0 {
1072		spi0_clk_pins: spi0-clk-pins {
1073			rockchip,pins =
1074				/* spi0_clk */
1075				<0 RK_PC0 2 &pcfg_pull_none>,
1076				/* spi0_miso */
1077				<0 RK_PC2 2 &pcfg_pull_none>,
1078				/* spi0_mosi */
1079				<0 RK_PC1 2 &pcfg_pull_none>;
1080		};
1081
1082		spi0_csn0_pins: spi0-csn0-pins {
1083			rockchip,pins =
1084				/* spi0_csn0 */
1085				<0 RK_PC3 2 &pcfg_pull_none>;
1086		};
1087		spi0_csn1_pins: spi0-csn1-pins {
1088			rockchip,pins =
1089				/* spi0_csn1 */
1090				<0 RK_PB7 2 &pcfg_pull_none>;
1091		};
1092	};
1093
1094	spi1 {
1095		spi1_clk_pins: spi1-clk-pins {
1096			rockchip,pins =
1097				/* spi1_clk */
1098				<0 RK_PB0 2 &pcfg_pull_none>,
1099				/* spi1_miso */
1100				<0 RK_PB2 2 &pcfg_pull_none>,
1101				/* spi1_mosi */
1102				<0 RK_PB1 2 &pcfg_pull_none>;
1103		};
1104
1105		spi1_csn0_pins: spi1-csn0-pins {
1106			rockchip,pins =
1107				/* spi1_csn0 */
1108				<0 RK_PB6 2 &pcfg_pull_none>;
1109		};
1110		spi1_csn1_pins: spi1-csn1-pins {
1111			rockchip,pins =
1112				/* spi1_csn1 */
1113				<0 RK_PA7 2 &pcfg_pull_none>;
1114		};
1115	};
1116
1117	spi2 {
1118		spi2_clk_pins: spi2-clk-pins {
1119			rockchip,pins =
1120				/* spi2_clk */
1121				<2 RK_PB0 2 &pcfg_pull_none>,
1122				/* spi2_miso */
1123				<2 RK_PB3 2 &pcfg_pull_none>,
1124				/* spi2_mosi */
1125				<2 RK_PB2 2 &pcfg_pull_none>;
1126		};
1127
1128		spi2_csn_pins: spi2-csn-pins {
1129			rockchip,pins =
1130				/* spi2_csn */
1131				<2 RK_PB1 2 &pcfg_pull_none>;
1132		};
1133	};
1134
1135	test_clk {
1136		test_clk_pins: test-clk-pins {
1137			rockchip,pins =
1138				/* test_clk_out */
1139				<3 RK_PA3 2 &pcfg_pull_none>;
1140		};
1141	};
1142
1143	uart0 {
1144		uart0_xfer_pins: uart0-xfer-pins {
1145			rockchip,pins =
1146				/* uart0_rx */
1147				<0 RK_PC7 1 &pcfg_pull_up>,
1148				/* uart0_tx */
1149				<0 RK_PC6 1 &pcfg_pull_up>;
1150		};
1151	};
1152
1153	uart5 {
1154		uart5m0_xfer_pins: uart5m0-xfer-pins {
1155			rockchip,pins =
1156				/* uart5_rx_m0 */
1157				<3 RK_PB3 1 &pcfg_pull_up>,
1158				/* uart5_tx_m0 */
1159				<3 RK_PB4 1 &pcfg_pull_up>;
1160		};
1161
1162		uart5m0_ctsn_pins: uart5m0-ctsn-pins {
1163			rockchip,pins =
1164				/* uart5m0_ctsn */
1165				<3 RK_PB2 1 &pcfg_pull_none>;
1166		};
1167		uart5m0_rtsn_pins: uart5m0-rtsn-pins {
1168			rockchip,pins =
1169				/* uart5m0_rtsn */
1170				<3 RK_PB5 1 &pcfg_pull_none>;
1171		};
1172
1173		uart5m1_xfer_pins: uart5m1-xfer-pins {
1174			rockchip,pins =
1175				/* uart5_rx_m1 */
1176				<1 RK_PD3 6 &pcfg_pull_up>,
1177				/* uart5_tx_m1 */
1178				<1 RK_PD2 6 &pcfg_pull_up>;
1179		};
1180
1181		uart5m1_ctsn_pins: uart5m1-ctsn-pins {
1182			rockchip,pins =
1183				/* uart5m1_ctsn */
1184				<1 RK_PB1 6 &pcfg_pull_none>;
1185		};
1186		uart5m1_rtsn_pins: uart5m1-rtsn-pins {
1187			rockchip,pins =
1188				/* uart5m1_rtsn */
1189				<1 RK_PD1 6 &pcfg_pull_none>;
1190		};
1191	};
1192
1193	vo_lcdc {
1194		vo_lcdc_pins: vo-lcdc-pins {
1195			rockchip,pins =
1196				/* vo_lcdc_clk */
1197				<1 RK_PA3 1 &pcfg_pull_none>,
1198				/* vo_lcdc_d0 */
1199				<1 RK_PD3 1 &pcfg_pull_none>,
1200				/* vo_lcdc_d1 */
1201				<1 RK_PD2 1 &pcfg_pull_none>,
1202				/* vo_lcdc_d2 */
1203				<1 RK_PD1 1 &pcfg_pull_none>,
1204				/* vo_lcdc_d3 */
1205				<1 RK_PD0 1 &pcfg_pull_none>,
1206				/* vo_lcdc_d4 */
1207				<1 RK_PC7 1 &pcfg_pull_none>,
1208				/* vo_lcdc_d5 */
1209				<1 RK_PC6 1 &pcfg_pull_none>,
1210				/* vo_lcdc_d6 */
1211				<1 RK_PC5 1 &pcfg_pull_none>,
1212				/* vo_lcdc_d7 */
1213				<1 RK_PC4 1 &pcfg_pull_none>,
1214				/* vo_lcdc_d8 */
1215				<1 RK_PC3 1 &pcfg_pull_none>,
1216				/* vo_lcdc_d9 */
1217				<1 RK_PC2 1 &pcfg_pull_none>,
1218				/* vo_lcdc_d10 */
1219				<1 RK_PC1 1 &pcfg_pull_none>,
1220				/* vo_lcdc_d11 */
1221				<1 RK_PC0 1 &pcfg_pull_none>,
1222				/* vo_lcdc_d12 */
1223				<1 RK_PB7 1 &pcfg_pull_none>,
1224				/* vo_lcdc_d13 */
1225				<1 RK_PB6 1 &pcfg_pull_none>,
1226				/* vo_lcdc_d14 */
1227				<1 RK_PB5 1 &pcfg_pull_none>,
1228				/* vo_lcdc_d15 */
1229				<1 RK_PB4 1 &pcfg_pull_none>,
1230				/* vo_lcdc_d16 */
1231				<1 RK_PB3 1 &pcfg_pull_none>,
1232				/* vo_lcdc_d17 */
1233				<1 RK_PB2 1 &pcfg_pull_none>,
1234				/* vo_lcdc_d18 */
1235				<1 RK_PB1 1 &pcfg_pull_none>,
1236				/* vo_lcdc_d19 */
1237				<1 RK_PB0 1 &pcfg_pull_none>,
1238				/* vo_lcdc_d20 */
1239				<1 RK_PA7 1 &pcfg_pull_none>,
1240				/* vo_lcdc_d21 */
1241				<1 RK_PA6 1 &pcfg_pull_none>,
1242				/* vo_lcdc_d22 */
1243				<1 RK_PA5 1 &pcfg_pull_none>,
1244				/* vo_lcdc_d23 */
1245				<1 RK_PA4 1 &pcfg_pull_none>,
1246				/* vo_lcdc_den */
1247				<1 RK_PA0 1 &pcfg_pull_none>,
1248				/* vo_lcdc_hsync */
1249				<1 RK_PA2 1 &pcfg_pull_none>,
1250				/* vo_lcdc_vsync */
1251				<1 RK_PA1 1 &pcfg_pull_none>;
1252		};
1253	};
1254};
1255
1256/*
1257 * This part is edited handly.
1258 */
1259&pinctrl {
1260	vo_lcdc {
1261		bt1120_pins: bt1120-pins {
1262			rockchip,pins =
1263				/* vo_lcdc_clk */
1264				<1 RK_PA3 1 &pcfg_pull_none>,
1265				/* vo_lcdc_d3 */
1266				<1 RK_PD0 1 &pcfg_pull_none>,
1267				/* vo_lcdc_d4 */
1268				<1 RK_PC7 1 &pcfg_pull_none>,
1269				/* vo_lcdc_d5 */
1270				<1 RK_PC6 1 &pcfg_pull_none>,
1271				/* vo_lcdc_d6 */
1272				<1 RK_PC5 1 &pcfg_pull_none>,
1273				/* vo_lcdc_d7 */
1274				<1 RK_PC4 1 &pcfg_pull_none>,
1275				/* vo_lcdc_d10 */
1276				<1 RK_PC1 1 &pcfg_pull_none>,
1277				/* vo_lcdc_d11 */
1278				<1 RK_PC0 1 &pcfg_pull_none>,
1279				/* vo_lcdc_d12 */
1280				<1 RK_PB7 1 &pcfg_pull_none>,
1281				/* vo_lcdc_d13 */
1282				<1 RK_PB6 1 &pcfg_pull_none>,
1283				/* vo_lcdc_d14 */
1284				<1 RK_PB5 1 &pcfg_pull_none>,
1285				/* vo_lcdc_d15 */
1286				<1 RK_PB4 1 &pcfg_pull_none>,
1287				/* vo_lcdc_d19 */
1288				<1 RK_PB0 1 &pcfg_pull_none>,
1289				/* vo_lcdc_d20 */
1290				<1 RK_PA7 1 &pcfg_pull_none>,
1291				/* vo_lcdc_d21 */
1292				<1 RK_PA6 1 &pcfg_pull_none>,
1293				/* vo_lcdc_d22 */
1294				<1 RK_PA5 1 &pcfg_pull_none>,
1295				/* vo_lcdc_d23 */
1296				<1 RK_PA4 1 &pcfg_pull_none>;
1297		};
1298
1299		bt656_m0_pins: bt656-m0-pins {
1300			rockchip,pins =
1301				/* vo_lcdc_clk */
1302				<1 RK_PA3 1 &pcfg_pull_none>,
1303				/* vo_lcdc_d3 */
1304				<1 RK_PD0 1 &pcfg_pull_none>,
1305				/* vo_lcdc_d4 */
1306				<1 RK_PC7 1 &pcfg_pull_none>,
1307				/* vo_lcdc_d5 */
1308				<1 RK_PC6 1 &pcfg_pull_none>,
1309				/* vo_lcdc_d6 */
1310				<1 RK_PC5 1 &pcfg_pull_none>,
1311				/* vo_lcdc_d7 */
1312				<1 RK_PC4 1 &pcfg_pull_none>,
1313				/* vo_lcdc_d10 */
1314				<1 RK_PC1 1 &pcfg_pull_none>,
1315				/* vo_lcdc_d11 */
1316				<1 RK_PC0 1 &pcfg_pull_none>,
1317				/* vo_lcdc_d12 */
1318				<1 RK_PB7 1 &pcfg_pull_none>;
1319		};
1320
1321		bt656_m1_pins: bt656-m1-pins {
1322			rockchip,pins =
1323				/* vo_lcdc_clk */
1324				<1 RK_PA3 1 &pcfg_pull_none>,
1325				/* vo_lcdc_d13 */
1326				<1 RK_PB6 1 &pcfg_pull_none>,
1327				/* vo_lcdc_d14 */
1328				<1 RK_PB5 1 &pcfg_pull_none>,
1329				/* vo_lcdc_d15 */
1330				<1 RK_PB4 1 &pcfg_pull_none>,
1331				/* vo_lcdc_d19 */
1332				<1 RK_PB0 1 &pcfg_pull_none>,
1333				/* vo_lcdc_d20 */
1334				<1 RK_PA7 1 &pcfg_pull_none>,
1335				/* vo_lcdc_d21 */
1336				<1 RK_PA6 1 &pcfg_pull_none>,
1337				/* vo_lcdc_d22 */
1338				<1 RK_PA5 1 &pcfg_pull_none>,
1339				/* vo_lcdc_d23 */
1340				<1 RK_PA4 1 &pcfg_pull_none>;
1341		};
1342
1343		rgb3x8_rgb2x8_m0_pins: rgb3x8-rgb2x8-m0-pins {
1344			rockchip,pins =
1345				/* vo_lcdc_clk */
1346				<1 RK_PA3 1 &pcfg_pull_none>,
1347				/* vo_lcdc_d3 */
1348				<1 RK_PD0 1 &pcfg_pull_none>,
1349				/* vo_lcdc_d4 */
1350				<1 RK_PC7 1 &pcfg_pull_none>,
1351				/* vo_lcdc_d5 */
1352				<1 RK_PC6 1 &pcfg_pull_none>,
1353				/* vo_lcdc_d6 */
1354				<1 RK_PC5 1 &pcfg_pull_none>,
1355				/* vo_lcdc_d7 */
1356				<1 RK_PC4 1 &pcfg_pull_none>,
1357				/* vo_lcdc_d10 */
1358				<1 RK_PC1 1 &pcfg_pull_none>,
1359				/* vo_lcdc_d11 */
1360				<1 RK_PC0 1 &pcfg_pull_none>,
1361				/* vo_lcdc_d12 */
1362				<1 RK_PB7 1 &pcfg_pull_none>,
1363				/* vo_lcdc_den */
1364				<1 RK_PA0 1 &pcfg_pull_none>,
1365				/* vo_lcdc_hsync */
1366				<1 RK_PA2 1 &pcfg_pull_none>,
1367				/* vo_lcdc_vsync */
1368				<1 RK_PA1 1 &pcfg_pull_none>;
1369		};
1370
1371		rgb3x8_rgb2x8_m1_pins: rgb3x8-rgb2x8-m1-pins {
1372			rockchip,pins =
1373				/* vo_lcdc_clk */
1374				<1 RK_PA3 1 &pcfg_pull_none>,
1375				/* vo_lcdc_d13 */
1376				<1 RK_PB6 1 &pcfg_pull_none>,
1377				/* vo_lcdc_d14 */
1378				<1 RK_PB5 1 &pcfg_pull_none>,
1379				/* vo_lcdc_d15 */
1380				<1 RK_PB4 1 &pcfg_pull_none>,
1381				/* vo_lcdc_d19 */
1382				<1 RK_PB0 1 &pcfg_pull_none>,
1383				/* vo_lcdc_d20 */
1384				<1 RK_PA7 1 &pcfg_pull_none>,
1385				/* vo_lcdc_d21 */
1386				<1 RK_PA6 1 &pcfg_pull_none>,
1387				/* vo_lcdc_d22 */
1388				<1 RK_PA5 1 &pcfg_pull_none>,
1389				/* vo_lcdc_d23 */
1390				<1 RK_PA4 1 &pcfg_pull_none>,
1391				/* vo_lcdc_den */
1392				<1 RK_PA0 1 &pcfg_pull_none>,
1393				/* vo_lcdc_hsync */
1394				<1 RK_PA2 1 &pcfg_pull_none>,
1395				/* vo_lcdc_vsync */
1396				<1 RK_PA1 1 &pcfg_pull_none>;
1397		};
1398
1399		rgb565_pins: rgb565-pins {
1400			rockchip,pins =
1401				/* vo_lcdc_clk */
1402				<1 RK_PA3 1 &pcfg_pull_none>,
1403				/* vo_lcdc_d3 */
1404				<1 RK_PD0 1 &pcfg_pull_none>,
1405				/* vo_lcdc_d4 */
1406				<1 RK_PC7 1 &pcfg_pull_none>,
1407				/* vo_lcdc_d5 */
1408				<1 RK_PC6 1 &pcfg_pull_none>,
1409				/* vo_lcdc_d6 */
1410				<1 RK_PC5 1 &pcfg_pull_none>,
1411				/* vo_lcdc_d7 */
1412				<1 RK_PC4 1 &pcfg_pull_none>,
1413				/* vo_lcdc_d10 */
1414				<1 RK_PC1 1 &pcfg_pull_none>,
1415				/* vo_lcdc_d11 */
1416				<1 RK_PC0 1 &pcfg_pull_none>,
1417				/* vo_lcdc_d12 */
1418				<1 RK_PB7 1 &pcfg_pull_none>,
1419				/* vo_lcdc_d13 */
1420				<1 RK_PB6 1 &pcfg_pull_none>,
1421				/* vo_lcdc_d14 */
1422				<1 RK_PB5 1 &pcfg_pull_none>,
1423				/* vo_lcdc_d15 */
1424				<1 RK_PB4 1 &pcfg_pull_none>,
1425				/* vo_lcdc_d19 */
1426				<1 RK_PB0 1 &pcfg_pull_none>,
1427				/* vo_lcdc_d20 */
1428				<1 RK_PA7 1 &pcfg_pull_none>,
1429				/* vo_lcdc_d21 */
1430				<1 RK_PA6 1 &pcfg_pull_none>,
1431				/* vo_lcdc_d22 */
1432				<1 RK_PA5 1 &pcfg_pull_none>,
1433				/* vo_lcdc_d23 */
1434				<1 RK_PA4 1 &pcfg_pull_none>,
1435				/* vo_lcdc_den */
1436				<1 RK_PA0 1 &pcfg_pull_none>,
1437				/* vo_lcdc_hsync */
1438				<1 RK_PA2 1 &pcfg_pull_none>,
1439				/* vo_lcdc_vsync */
1440				<1 RK_PA1 1 &pcfg_pull_none>;
1441		};
1442
1443		rgb666_pins: rgb666-pins {
1444			rockchip,pins =
1445				/* vo_lcdc_clk */
1446				<1 RK_PA3 1 &pcfg_pull_none>,
1447				/* vo_lcdc_d2 */
1448				<1 RK_PD1 1 &pcfg_pull_none>,
1449				/* vo_lcdc_d3 */
1450				<1 RK_PD0 1 &pcfg_pull_none>,
1451				/* vo_lcdc_d4 */
1452				<1 RK_PC7 1 &pcfg_pull_none>,
1453				/* vo_lcdc_d5 */
1454				<1 RK_PC6 1 &pcfg_pull_none>,
1455				/* vo_lcdc_d6 */
1456				<1 RK_PC5 1 &pcfg_pull_none>,
1457				/* vo_lcdc_d7 */
1458				<1 RK_PC4 1 &pcfg_pull_none>,
1459				/* vo_lcdc_d10 */
1460				<1 RK_PC1 1 &pcfg_pull_none>,
1461				/* vo_lcdc_d11 */
1462				<1 RK_PC0 1 &pcfg_pull_none>,
1463				/* vo_lcdc_d12 */
1464				<1 RK_PB7 1 &pcfg_pull_none>,
1465				/* vo_lcdc_d13 */
1466				<1 RK_PB6 1 &pcfg_pull_none>,
1467				/* vo_lcdc_d14 */
1468				<1 RK_PB5 1 &pcfg_pull_none>,
1469				/* vo_lcdc_d15 */
1470				<1 RK_PB4 1 &pcfg_pull_none>,
1471				/* vo_lcdc_d18 */
1472				<1 RK_PB1 1 &pcfg_pull_none>,
1473				/* vo_lcdc_d19 */
1474				<1 RK_PB0 1 &pcfg_pull_none>,
1475				/* vo_lcdc_d20 */
1476				<1 RK_PA7 1 &pcfg_pull_none>,
1477				/* vo_lcdc_d21 */
1478				<1 RK_PA6 1 &pcfg_pull_none>,
1479				/* vo_lcdc_d22 */
1480				<1 RK_PA5 1 &pcfg_pull_none>,
1481				/* vo_lcdc_d23 */
1482				<1 RK_PA4 1 &pcfg_pull_none>,
1483				/* vo_lcdc_den */
1484				<1 RK_PA0 1 &pcfg_pull_none>,
1485				/* vo_lcdc_hsync */
1486				<1 RK_PA2 1 &pcfg_pull_none>,
1487				/* vo_lcdc_vsync */
1488				<1 RK_PA1 1 &pcfg_pull_none>;
1489		};
1490
1491		rgb888_pins: rgb888-pins {
1492			rockchip,pins =
1493				/* vo_lcdc_clk */
1494				<1 RK_PA3 1 &pcfg_pull_none>,
1495				/* vo_lcdc_d0 */
1496				<1 RK_PD3 1 &pcfg_pull_none>,
1497				/* vo_lcdc_d1 */
1498				<1 RK_PD2 1 &pcfg_pull_none>,
1499				/* vo_lcdc_d2 */
1500				<1 RK_PD1 1 &pcfg_pull_none>,
1501				/* vo_lcdc_d3 */
1502				<1 RK_PD0 1 &pcfg_pull_none>,
1503				/* vo_lcdc_d4 */
1504				<1 RK_PC7 1 &pcfg_pull_none>,
1505				/* vo_lcdc_d5 */
1506				<1 RK_PC6 1 &pcfg_pull_none>,
1507				/* vo_lcdc_d6 */
1508				<1 RK_PC5 1 &pcfg_pull_none>,
1509				/* vo_lcdc_d7 */
1510				<1 RK_PC4 1 &pcfg_pull_none>,
1511				/* vo_lcdc_d8 */
1512				<1 RK_PC3 1 &pcfg_pull_none>,
1513				/* vo_lcdc_d9 */
1514				<1 RK_PC2 1 &pcfg_pull_none>,
1515				/* vo_lcdc_d10 */
1516				<1 RK_PC1 1 &pcfg_pull_none>,
1517				/* vo_lcdc_d11 */
1518				<1 RK_PC0 1 &pcfg_pull_none>,
1519				/* vo_lcdc_d12 */
1520				<1 RK_PB7 1 &pcfg_pull_none>,
1521				/* vo_lcdc_d13 */
1522				<1 RK_PB6 1 &pcfg_pull_none>,
1523				/* vo_lcdc_d14 */
1524				<1 RK_PB5 1 &pcfg_pull_none>,
1525				/* vo_lcdc_d15 */
1526				<1 RK_PB4 1 &pcfg_pull_none>,
1527				/* vo_lcdc_d16 */
1528				<1 RK_PB3 1 &pcfg_pull_none>,
1529				/* vo_lcdc_d17 */
1530				<1 RK_PB2 1 &pcfg_pull_none>,
1531				/* vo_lcdc_d18 */
1532				<1 RK_PB1 1 &pcfg_pull_none>,
1533				/* vo_lcdc_d19 */
1534				<1 RK_PB0 1 &pcfg_pull_none>,
1535				/* vo_lcdc_d20 */
1536				<1 RK_PA7 1 &pcfg_pull_none>,
1537				/* vo_lcdc_d21 */
1538				<1 RK_PA6 1 &pcfg_pull_none>,
1539				/* vo_lcdc_d22 */
1540				<1 RK_PA5 1 &pcfg_pull_none>,
1541				/* vo_lcdc_d23 */
1542				<1 RK_PA4 1 &pcfg_pull_none>,
1543				/* vo_lcdc_den */
1544				<1 RK_PA0 1 &pcfg_pull_none>,
1545				/* vo_lcdc_hsync */
1546				<1 RK_PA2 1 &pcfg_pull_none>,
1547				/* vo_lcdc_vsync */
1548				<1 RK_PA1 1 &pcfg_pull_none>;
1549		};
1550	};
1551};
1552