1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7/* 8 * This define is for support double show any dclk frequency. 9 * dclk_vop will have a exclusive pll as parent. 10 * set dclk_vop will change the pll rate as well. 11 */ 12 13#ifdef RK3399_TWO_PLL_FOR_VOP 14 15&sdhci { 16 assigned-clocks = <&cru SCLK_EMMC>; 17 assigned-clock-parents = <&cru PLL_GPLL>; 18 assigned-clock-rates = <200000000>; 19}; 20 21&uart0 { 22 assigned-clocks = <&cru SCLK_UART0_SRC>; 23 assigned-clock-parents = <&cru PLL_GPLL>; 24}; 25 26&uart1 { 27 assigned-clocks = <&cru SCLK_UART_SRC>; 28 assigned-clock-parents = <&cru PLL_GPLL>; 29}; 30 31&uart2 { 32 assigned-clocks = <&cru SCLK_UART_SRC>; 33 assigned-clock-parents = <&cru PLL_GPLL>; 34}; 35 36&uart3 { 37 assigned-clocks = <&cru SCLK_UART_SRC>; 38 assigned-clock-parents = <&cru PLL_GPLL>; 39}; 40 41&uart4 { 42 assigned-clocks = <&pmucru SCLK_UART4_SRC>; 43 assigned-clock-parents = <&pmucru PLL_PPLL>; 44}; 45 46&spdif { 47 assigned-clocks = <&cru SCLK_SPDIF_DIV>; 48 assigned-clock-parents = <&cru PLL_GPLL>; 49}; 50 51&i2s0{ 52 assigned-clocks = <&cru SCLK_I2S0_DIV>; 53 assigned-clock-parents = <&cru PLL_GPLL>; 54}; 55 56&i2s1 { 57 assigned-clocks = <&cru SCLK_I2S1_DIV>; 58 assigned-clock-parents = <&cru PLL_GPLL>; 59}; 60 61&i2s2 { 62 assigned-clocks = <&cru SCLK_I2S2_DIV>; 63 assigned-clock-parents = <&cru PLL_GPLL>; 64}; 65 66&cru { 67 assigned-clocks = 68 <&cru ACLK_PERIHP>, <&cru ACLK_PERILP0>, 69 <&cru HCLK_PERILP1>, <&cru SCLK_SDMMC>, 70 <&cru ACLK_EMMC>, <&cru ACLK_CENTER>, 71 <&cru HCLK_SD>, <&cru SCLK_VDU_CA>, 72 <&cru SCLK_VDU_CORE>, <&cru ACLK_USB3>, 73 <&cru FCLK_CM0S>, <&cru ACLK_CCI>, 74 <&cru PCLK_ALIVE>, <&cru ACLK_GMAC>, 75 <&cru SCLK_CS>, <&cru SCLK_CCI_TRACE>, 76 <&cru ARMCLKL>, <&cru ARMCLKB>, 77 <&cru PLL_NPLL>, <&cru ACLK_GPU>, 78 <&cru PLL_GPLL>, <&cru ACLK_PERIHP>, 79 <&cru HCLK_PERIHP>, <&cru PCLK_PERIHP>, 80 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 81 <&cru PCLK_PERILP0>, <&cru HCLK_PERILP1>, 82 <&cru PCLK_PERILP1>, <&cru SCLK_I2C1>, 83 <&cru SCLK_I2C2>, <&cru SCLK_I2C3>, 84 <&cru SCLK_I2C5>, <&cru SCLK_I2C6>, 85 <&cru SCLK_I2C7>, <&cru SCLK_SPI0>, 86 <&cru SCLK_SPI1>, <&cru SCLK_SPI2>, 87 <&cru SCLK_SPI4>, <&cru SCLK_SPI5>, 88 <&cru ACLK_GIC>, <&cru ACLK_ISP0>, 89 <&cru ACLK_ISP1>, <&cru SCLK_VOP0_PWM>, 90 <&cru SCLK_VOP1_PWM>, <&cru PCLK_EDP>, 91 <&cru ACLK_HDCP>, <&cru ACLK_VIO>, 92 <&cru HCLK_SD>, <&cru SCLK_CRYPTO0>, 93 <&cru SCLK_CRYPTO1>, <&cru SCLK_EMMC>, 94 <&cru ACLK_EMMC>, <&cru ACLK_CENTER>, 95 <&cru ACLK_IEP>, <&cru ACLK_RGA>, 96 <&cru SCLK_RGA_CORE>, <&cru ACLK_VDU>, 97 <&cru ACLK_VCODEC>, <&cru PCLK_DDR>, 98 <&cru ACLK_GMAC>, <&cru SCLK_VDU_CA>, 99 <&cru SCLK_VDU_CORE>, <&cru ACLK_USB3>, 100 <&cru FCLK_CM0S>, <&cru ACLK_CCI>, 101 <&cru PCLK_ALIVE>, <&cru SCLK_CS>, 102 <&cru SCLK_CCI_TRACE>, <&cru ACLK_VOP0>, 103 <&cru HCLK_VOP0>, <&cru ACLK_VOP1>, 104 <&cru HCLK_VOP1>; 105 assigned-clock-rates = 106 <75000000>, <50000000>, 107 <50000000>, <50000000>, 108 <50000000>, <100000000>, 109 <50000000>, <150000000>, 110 <150000000>, <150000000>, 111 <50000000>, <150000000>, 112 <50000000>, <100000000>, 113 <75000000>, <75000000>, 114 <816000000>, <816000000>, 115 <600000000>, <200000000>, 116 <800000000>, <150000000>, 117 <75000000>, <37500000>, 118 <300000000>, <100000000>, 119 <50000000>, <100000000>, 120 <50000000>, <100000000>, 121 <100000000>, <100000000>, 122 <100000000>, <100000000>, 123 <100000000>, <50000000>, 124 <50000000>, <50000000>, 125 <50000000>, <50000000>, 126 <200000000>, <400000000>, 127 <400000000>, <100000000>, 128 <100000000>, <100000000>, 129 <400000000>, <400000000>, 130 <200000000>, <100000000>, 131 <200000000>, <200000000>, 132 <100000000>, <400000000>, 133 <400000000>, <400000000>, 134 <400000000>, <300000000>, 135 <400000000>, <200000000>, 136 <400000000>, <300000000>, 137 <300000000>, <300000000>, 138 <300000000>, <600000000>,/* aclk_cci */ 139 <100000000>, <150000000>, 140 <150000000>, <400000000>, 141 <100000000>, <400000000>, 142 <100000000>; 143}; 144#endif 145 146