1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include "rk3399-sched-energy.dtsi" 7 8/ { 9 cluster0_opp: opp-table0 { 10 compatible = "operating-points-v2"; 11 opp-shared; 12 13 rockchip,temp-hysteresis = <5000>; 14 rockchip,low-temp = <10000>; 15 rockchip,low-temp-min-volt = <900000>; 16 17 nvmem-cells = <&cpul_leakage>, <&specification_serial_number>, 18 <&customer_demand>; 19 nvmem-cell-names = "cpu_leakage", 20 "specification_serial_number", 21 "customer_demand"; 22 clocks = <&cru PLL_APLLL>; 23 rockchip,avs-scale = <20>; 24 rockchip,bin-scaling-sel = < 25 0 30 26 1 34 27 >; 28 29 rockchip,pvtm-voltage-sel = < 30 0 143500 0 31 143501 148500 1 32 148501 152000 2 33 152001 999999 3 34 >; 35 rockchip,pvtm-freq = <408000>; 36 rockchip,pvtm-volt = <1000000>; 37 rockchip,pvtm-ch = <0 0>; 38 rockchip,pvtm-sample-time = <1000>; 39 rockchip,pvtm-number = <10>; 40 rockchip,pvtm-error = <1000>; 41 rockchip,pvtm-ref-temp = <41>; 42 rockchip,pvtm-temp-prop = <115 66>; 43 rockchip,pvtm-thermal-zone = "soc-thermal"; 44 45 opp-408000000 { 46 opp-hz = /bits/ 64 <408000000>; 47 opp-microvolt = <825000 825000 1250000>; 48 opp-microvolt-L0 = <825000 825000 1250000>; 49 opp-microvolt-L1 = <825000 825000 1250000>; 50 opp-microvolt-L2 = <825000 825000 1250000>; 51 opp-microvolt-L3 = <825000 825000 1250000>; 52 clock-latency-ns = <40000>; 53 }; 54 opp-600000000 { 55 opp-hz = /bits/ 64 <600000000>; 56 opp-microvolt = <825000 825000 1250000>; 57 opp-microvolt-L0 = <825000 825000 1250000>; 58 opp-microvolt-L1 = <825000 825000 1250000>; 59 opp-microvolt-L2 = <825000 825000 1250000>; 60 opp-microvolt-L3 = <825000 825000 1250000>; 61 clock-latency-ns = <40000>; 62 }; 63 opp-816000000 { 64 opp-hz = /bits/ 64 <816000000>; 65 opp-microvolt = <850000 850000 1250000>; 66 opp-microvolt-L0 = <850000 850000 1250000>; 67 opp-microvolt-L1 = <825000 825000 1250000>; 68 opp-microvolt-L2 = <825000 825000 1250000>; 69 opp-microvolt-L3 = <825000 825000 1250000>; 70 clock-latency-ns = <40000>; 71 opp-suspend; 72 }; 73 opp-1008000000 { 74 opp-hz = /bits/ 64 <1008000000>; 75 opp-microvolt = <925000 925000 1250000>; 76 opp-microvolt-L0 = <925000 925000 1250000>; 77 opp-microvolt-L1 = <900000 900000 1250000>; 78 opp-microvolt-L2 = <875000 875000 1250000>; 79 opp-microvolt-L3 = <850000 850000 1250000>; 80 clock-latency-ns = <40000>; 81 }; 82 opp-1200000000 { 83 opp-hz = /bits/ 64 <1200000000>; 84 opp-microvolt = <1000000 1000000 1250000>; 85 opp-microvolt-L0 = <1000000 1000000 1250000>; 86 opp-microvolt-L1 = <975000 975000 1250000>; 87 opp-microvolt-L2 = <950000 950000 1250000>; 88 opp-microvolt-L3 = <925000 925000 1250000>; 89 clock-latency-ns = <40000>; 90 }; 91 opp-1416000000 { 92 opp-hz = /bits/ 64 <1416000000>; 93 opp-microvolt = <1125000 1125000 1250000>; 94 opp-microvolt-L0 = <1125000 1125000 1250000>; 95 opp-microvolt-L1 = <1100000 1100000 1250000>; 96 opp-microvolt-L2 = <1075000 1075000 1200000>; 97 opp-microvolt-L3 = <1050000 1050000 1250000>; 98 clock-latency-ns = <40000>; 99 }; 100 }; 101 102 cluster1_opp: opp-table1 { 103 compatible = "operating-points-v2"; 104 opp-shared; 105 106 rockchip,temp-hysteresis = <5000>; 107 rockchip,low-temp = <10000>; 108 rockchip,low-temp-min-volt = <900000>; 109 110 nvmem-cells = <&cpub_leakage>, <&specification_serial_number>, 111 <&customer_demand>; 112 nvmem-cell-names = "cpu_leakage", 113 "specification_serial_number", 114 "customer_demand"; 115 clocks = <&cru PLL_APLLB>; 116 rockchip,avs-scale = <8>; 117 rockchip,bin-scaling-sel = < 118 0 8 119 1 17 120 >; 121 122 rockchip,pvtm-voltage-sel = < 123 0 149000 0 124 149001 155000 1 125 155001 159000 2 126 159001 161000 3 127 161001 999999 4 128 >; 129 rockchip,pvtm-freq = <408000>; 130 rockchip,pvtm-volt = <1000000>; 131 rockchip,pvtm-ch = <1 0>; 132 rockchip,pvtm-sample-time = <1000>; 133 rockchip,pvtm-number = <10>; 134 rockchip,pvtm-error = <1000>; 135 rockchip,pvtm-ref-temp = <41>; 136 rockchip,pvtm-temp-prop = <71 35>; 137 rockchip,pvtm-thermal-zone = "soc-thermal"; 138 139 opp-408000000 { 140 opp-hz = /bits/ 64 <408000000>; 141 opp-microvolt = <825000 825000 1250000>; 142 opp-microvolt-L0 = <825000 825000 1250000>; 143 opp-microvolt-L1 = <825000 825000 1250000>; 144 opp-microvolt-L2 = <825000 825000 1250000>; 145 opp-microvolt-L3 = <825000 825000 1250000>; 146 opp-microvolt-L4 = <825000 825000 1250000>; 147 clock-latency-ns = <40000>; 148 }; 149 opp-600000000 { 150 opp-hz = /bits/ 64 <600000000>; 151 opp-microvolt = <825000 825000 1250000>; 152 opp-microvolt-L0 = <825000 825000 1250000>; 153 opp-microvolt-L1 = <825000 825000 1250000>; 154 opp-microvolt-L2 = <825000 825000 1250000>; 155 opp-microvolt-L3 = <825000 825000 1250000>; 156 opp-microvolt-L4 = <825000 825000 1250000>; 157 clock-latency-ns = <40000>; 158 }; 159 opp-816000000 { 160 opp-hz = /bits/ 64 <816000000>; 161 opp-microvolt = <825000 825000 1250000>; 162 opp-microvolt-L0 = <825000 825000 1250000>; 163 opp-microvolt-L1 = <825000 825000 1250000>; 164 opp-microvolt-L2 = <825000 825000 1250000>; 165 opp-microvolt-L3 = <825000 825000 1250000>; 166 opp-microvolt-L4 = <825000 825000 1250000>; 167 clock-latency-ns = <40000>; 168 opp-suspend; 169 }; 170 opp-1008000000 { 171 opp-hz = /bits/ 64 <1008000000>; 172 opp-microvolt = <875000 875000 1250000>; 173 opp-microvolt-L0 = <875000 875000 1250000>; 174 opp-microvolt-L1 = <850000 850000 1250000>; 175 opp-microvolt-L2 = <850000 850000 1250000>; 176 opp-microvolt-L3 = <850000 850000 1250000>; 177 opp-microvolt-L4 = <850000 850000 1250000>; 178 clock-latency-ns = <40000>; 179 }; 180 opp-1200000000 { 181 opp-hz = /bits/ 64 <1200000000>; 182 opp-microvolt = <950000 950000 1250000>; 183 opp-microvolt-L0 = <950000 950000 1250000>; 184 opp-microvolt-L1 = <925000 925000 1250000>; 185 opp-microvolt-L2 = <900000 900000 1250000>; 186 opp-microvolt-L3 = <875000 875000 1250000>; 187 opp-microvolt-L4 = <875000 875000 1250000>; 188 clock-latency-ns = <40000>; 189 }; 190 opp-1416000000 { 191 opp-hz = /bits/ 64 <1416000000>; 192 opp-microvolt = <1025000 1025000 1250000>; 193 opp-microvolt-L0 = <1025000 1025000 1250000>; 194 opp-microvolt-L1 = <1000000 1000000 1250000>; 195 opp-microvolt-L2 = <1000000 1000000 1250000>; 196 opp-microvolt-L3 = <975000 975000 1250000>; 197 opp-microvolt-L4 = <975000 975000 1250000>; 198 clock-latency-ns = <40000>; 199 }; 200 opp-1608000000 { 201 opp-hz = /bits/ 64 <1608000000>; 202 opp-microvolt = <1100000 1100000 1250000>; 203 opp-microvolt-L0 = <1100000 1100000 1250000>; 204 opp-microvolt-L1 = <1075000 1075000 1250000>; 205 opp-microvolt-L2 = <1050000 1050000 1250000>; 206 opp-microvolt-L3 = <1025000 1025000 1250000>; 207 opp-microvolt-L4 = <1025000 1025000 1250000>; 208 clock-latency-ns = <40000>; 209 }; 210 opp-1800000000 { 211 opp-hz = /bits/ 64 <1800000000>; 212 opp-microvolt = <1200000 1200000 1250000>; 213 opp-microvolt-L0 = <1200000 1200000 1250000>; 214 opp-microvolt-L1 = <1175000 1175000 1250000>; 215 opp-microvolt-L2 = <1150000 1150000 1250000>; 216 opp-microvolt-L3 = <1125000 1125000 1250000>; 217 opp-microvolt-L4 = <1100000 1100000 1250000>; 218 clock-latency-ns = <40000>; 219 }; 220 }; 221 222 gpu_opp_table: opp-table2 { 223 compatible = "operating-points-v2"; 224 225 rockchip,thermal-zone = "soc-thermal"; 226 rockchip,temp-hysteresis = <5000>; 227 rockchip,low-temp = <10000>; 228 rockchip,low-temp-min-volt = <900000>; 229 230 nvmem-cells = <&gpu_leakage>; 231 nvmem-cell-names = "gpu_leakage"; 232 233 rockchip,pvtm-voltage-sel = < 234 0 121000 0 235 121001 125500 1 236 125501 128500 2 237 128501 999999 3 238 >; 239 rockchip,pvtm-freq = <200000>; 240 rockchip,pvtm-volt = <900000>; 241 rockchip,pvtm-ch = <3 0>; 242 rockchip,pvtm-sample-time = <1000>; 243 rockchip,pvtm-number = <10>; 244 rockchip,pvtm-error = <1000>; 245 rockchip,pvtm-ref-temp = <41>; 246 rockchip,pvtm-temp-prop = <46 12>; 247 rockchip,pvtm-thermal-zone = "gpu-thermal"; 248 249 opp-200000000 { 250 opp-hz = /bits/ 64 <200000000>; 251 opp-microvolt = <825000>; 252 opp-microvolt-L0 = <825000>; 253 opp-microvolt-L1 = <825000>; 254 opp-microvolt-L2 = <825000>; 255 opp-microvolt-L3 = <825000>; 256 }; 257 opp-300000000 { 258 opp-hz = /bits/ 64 <300000000>; 259 opp-microvolt = <825000>; 260 opp-microvolt-L0 = <825000>; 261 opp-microvolt-L1 = <825000>; 262 opp-microvolt-L2 = <825000>; 263 opp-microvolt-L3 = <825000>; 264 }; 265 opp-400000000 { 266 opp-hz = /bits/ 64 <400000000>; 267 opp-microvolt = <825000>; 268 opp-microvolt-L0 = <825000>; 269 opp-microvolt-L1 = <825000>; 270 opp-microvolt-L2 = <825000>; 271 opp-microvolt-L3 = <825000>; 272 }; 273 opp-600000000 { 274 opp-hz = /bits/ 64 <600000000>; 275 opp-microvolt = <925000>; 276 opp-microvolt-L0 = <925000>; 277 opp-microvolt-L1 = <925000>; 278 opp-microvolt-L2 = <900000>; 279 opp-microvolt-L3 = <900000>; 280 }; 281 opp-800000000 { 282 opp-hz = /bits/ 64 <800000000>; 283 opp-microvolt = <1100000>; 284 opp-microvolt-L0 = <1100000>; 285 opp-microvolt-L1 = <1075000>; 286 opp-microvolt-L2 = <1050000>; 287 opp-microvolt-L3 = <1025000>; 288 }; 289 }; 290 291 dmc_opp_table: opp-table3 { 292 compatible = "operating-points-v2"; 293 294 opp-200000000 { 295 opp-hz = /bits/ 64 <200000000>; 296 opp-microvolt = <900000>; 297 }; 298 opp-300000000 { 299 opp-hz = /bits/ 64 <300000000>; 300 opp-microvolt = <900000>; 301 }; 302 opp-400000000 { 303 opp-hz = /bits/ 64 <400000000>; 304 opp-microvolt = <900000>; 305 }; 306 opp-528000000 { 307 opp-hz = /bits/ 64 <528000000>; 308 opp-microvolt = <900000>; 309 }; 310 opp-600000000 { 311 opp-hz = /bits/ 64 <600000000>; 312 opp-microvolt = <900000>; 313 }; 314 opp-800000000 { 315 opp-hz = /bits/ 64 <800000000>; 316 opp-microvolt = <900000>; 317 }; 318 }; 319}; 320 321&cpu_l0 { 322 operating-points-v2 = <&cluster0_opp>; 323 sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>; 324}; 325 326&cpu_l1 { 327 operating-points-v2 = <&cluster0_opp>; 328 sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>; 329}; 330 331&cpu_l2 { 332 operating-points-v2 = <&cluster0_opp>; 333 sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>; 334}; 335 336&cpu_l3 { 337 operating-points-v2 = <&cluster0_opp>; 338 sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>; 339}; 340 341&cpu_b0 { 342 operating-points-v2 = <&cluster1_opp>; 343 sched-energy-costs = <&RK3399_CPU_COST_1 &RK3399_CLUSTER_COST_1>; 344}; 345 346&cpu_b1 { 347 operating-points-v2 = <&cluster1_opp>; 348 sched-energy-costs = <&RK3399_CPU_COST_1 &RK3399_CLUSTER_COST_1>; 349}; 350 351&dmc { 352 operating-points-v2 = <&dmc_opp_table>; 353}; 354 355&gpu { 356 operating-points-v2 = <&gpu_opp_table>; 357}; 358