xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3399-linux.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4 *
5 */
6
7#include <dt-bindings/display/drm_mipi_dsi.h>
8#include "rk3399-vop-clk-set.dtsi"
9
10/ {
11	compatible = "rockchip,linux", "rockchip,rk3399";
12
13	aliases {
14		mmc0 = &sdhci;
15		mmc1 = &sdmmc;
16		mmc2 = &sdio0;
17	};
18
19	chosen {
20		bootargs = "earlycon=uart8250,mmio32,0xff1a0000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait coherent_pool=1m";
21	};
22
23	reserved-memory {
24		#address-cells = <2>;
25		#size-cells = <2>;
26		ranges;
27
28		drm_logo: drm-logo@00000000 {
29			compatible = "rockchip,drm-logo";
30			reg = <0x0 0x0 0x0 0x0>;
31		};
32
33		ramoops_mem: region@110000 {
34			reg = <0x0 0x110000 0x0 0xf0000>;
35			reg-names = "ramoops_mem";
36		};
37	};
38
39	ramoops: ramoops {
40		compatible = "ramoops";
41		record-size = <0x0 0x40000>;
42		console-size = <0x0 0x80000>;
43		ftrace-size = <0x0 0x00000>;
44		pmsg-size = <0x0 0x00000>;
45		memory-region = <&ramoops_mem>;
46	};
47
48	fiq_debugger: fiq-debugger {
49		compatible = "rockchip,fiq-debugger";
50		rockchip,serial-id = <2>;
51		rockchip,wake-irq = <0>;
52		rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
53		rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
54		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
55		pinctrl-names = "default";
56		pinctrl-0 = <&uart2c_xfer>;
57	};
58
59	cif_isp0: cif_isp@ff910000 {
60		compatible = "rockchip,rk3399-cif-isp";
61		rockchip,grf = <&grf>;
62		reg = <0x0 0xff910000 0x0 0x4000>, <0x0 0xff968000 0x0 0x8000>;
63		reg-names = "register", "dsihost-register";
64		clocks =
65			<&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
66			<&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
67			<&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>,
68			<&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
69			<&cru SCLK_MIPIDPHY_REF>;
70		clock-names =
71			"aclk_isp0_noc", "aclk_isp0_wrapper",
72			"hclk_isp0_noc", "hclk_isp0_wrapper",
73			"clk_isp0", "pclk_dphyrx",
74			"clk_cif_out", "clk_cif_pll",
75			"pclk_dphy_ref";
76		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
77		interrupt-names = "cif_isp10_irq";
78		power-domains = <&power RK3399_PD_ISP0>;
79		rockchip,isp,iommu-enable = <1>;
80		iommus = <&isp0_mmu>;
81		status = "disabled";
82	};
83
84	cif_isp1: cif_isp@ff920000 {
85		compatible = "rockchip,rk3399-cif-isp";
86		rockchip,grf = <&grf>;
87		reg = <0x0 0xff920000 0x0 0x4000>, <0x0 0xff968000 0x0 0x8000>;
88		reg-names = "register", "dsihost-register";
89		clocks =
90			<&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>,
91			<&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>,
92			<&cru SCLK_ISP1>, <&cru PCLK_ISP1_WRAPPER>,
93			<&cru SCLK_DPHY_TX1RX1_CFG>,
94			<&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>,
95			<&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
96			<&cru SCLK_MIPIDPHY_REF>;
97		clock-names =
98			"aclk_isp1_noc", "aclk_isp1_wrapper",
99			"hclk_isp1_noc", "hclk_isp1_wrapper",
100			"clk_isp1", "pclkin_isp1",
101			"pclk_dphytxrx",
102			"pclk_mipi_dsi","mipi_dphy_cfg",
103			"clk_cif_out", "clk_cif_pll",
104			"pclk_dphy_ref";
105		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
106		interrupt-names = "cif_isp10_irq";
107		power-domains = <&power RK3399_PD_ISP1>;
108		rockchip,isp,iommu-enable = <1>;
109		iommus = <&isp1_mmu>;
110		status = "disabled";
111	};
112
113	rga: rga@ff680000 {
114		compatible = "rockchip,rga2";
115		dev_mode = <1>;
116		reg = <0x0 0xff680000 0x0 0x1000>;
117		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
118		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
119		clock-names = "aclk_rga", "hclk_rga", "clk_rga";
120		power-domains = <&power RK3399_PD_RGA>;
121		status = "okay";
122	};
123};
124
125&display_subsystem {
126	status = "disabled";
127
128	ports = <&vopb_out>, <&vopl_out>;
129	logo-memory-region = <&drm_logo>;
130
131	route {
132		route_hdmi: route-hdmi {
133			status = "disabled";
134			logo,uboot = "logo.bmp";
135			logo,kernel = "logo_kernel.bmp";
136			logo,mode = "center";
137			charge_logo,mode = "center";
138			connect = <&vopb_out_hdmi>;
139		};
140
141		route_dsi: route-dsi {
142			status = "disabled";
143			logo,uboot = "logo.bmp";
144			logo,kernel = "logo_kernel.bmp";
145			logo,mode = "center";
146			charge_logo,mode = "center";
147			connect = <&vopl_out_dsi>;
148		};
149
150		route_edp: route-edp {
151			status = "disabled";
152			logo,uboot = "logo.bmp";
153			logo,kernel = "logo_kernel.bmp";
154			logo,mode = "center";
155			charge_logo,mode = "center";
156			connect = <&vopl_out_edp>;
157		};
158	};
159};
160
161&edp {
162	/delete-property/pinctrl-names;
163	/delete-property/pinctrl-0;
164};
165
166&iep {
167	status = "okay";
168};
169
170&iep_mmu {
171	status = "okay";
172};
173
174&mpp_srv {
175	status = "okay";
176};
177
178&pvtm {
179	status = "okay";
180};
181
182&rkvdec {
183	status = "okay";
184	/* 0 means ion, 1 means drm */
185	//allocator = <0>;
186};
187
188&vdec_mmu {
189	status = "okay";
190};
191
192&vdpu {
193	status = "okay";
194};
195
196&vepu {
197	status = "okay";
198};
199
200&vpu_mmu {
201	status = "okay";
202};
203
204&uart2 {
205	status = "disabled";
206};
207
208&pinctrl {
209	isp {
210		cif_clkout: cif-clkout {
211			rockchip,pins =
212				/* cif_clkout */
213				<2 RK_PB3 3 &pcfg_pull_none>;
214		};
215
216		isp_dvp_d0d7: isp-dvp-d0d7 {
217			rockchip,pins =
218				<4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>,
219				/* cif_clkout */
220				<2 RK_PB3 3 &pcfg_pull_none>,
221				/* cif_data0 */
222				<2 RK_PA0 3 &pcfg_pull_none>,
223				/* cif_data1 */
224				<2 RK_PA1 3 &pcfg_pull_none>,
225				/* cif_data2 */
226				<2 RK_PA2 3 &pcfg_pull_none>,
227				/* cif_data3 */
228				<2 RK_PA3 3 &pcfg_pull_none>,
229				/* cif_data4 */
230				<2 RK_PA4 3 &pcfg_pull_none>,
231				/* cif_data5 */
232				<2 RK_PA5 3 &pcfg_pull_none>,
233				/* cif_data6 */
234				<2 RK_PA6 3 &pcfg_pull_none>,
235				/* cif_data7 */
236				<2 RK_PA7 3 &pcfg_pull_none>,
237				/* cif_sync */
238				<2 RK_PB0 3 &pcfg_pull_none>,
239				/* cif_href */
240				<2 RK_PB1 3 &pcfg_pull_none>,
241				/* cif_clkin */
242				<2 RK_PB2 3 &pcfg_pull_none>;
243		};
244
245		isp_shutter: isp-shutter {
246			rockchip,pins =
247				/* SHUTTEREN */
248				<1 RK_PA1 1 &pcfg_pull_none>,
249				/* SHUTTERTRIG */
250				<1 RK_PA0 1 &pcfg_pull_none>;
251		};
252
253		isp_flash_trigger: isp-flash-trigger {
254			/* ISP_FLASHTRIGOU */
255			rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>;
256		};
257
258		isp_flash_trigger_as_gpio: isp-flash-trigger-as-gpio {
259			/* ISP_FLASHTRIGOU */
260			rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
261		};
262	};
263
264	cam_pins {
265		cam0_default_pins: cam0-default-pins {
266			rockchip,pins =
267				<4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>,
268				<2 RK_PB3 3 &pcfg_pull_none>;
269		};
270		cam0_sleep_pins: cam0-sleep-pins {
271			rockchip,pins =
272				<4 RK_PD3 3 &pcfg_pull_none>,
273				<2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
274		};
275	};
276};
277