1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7#include <dt-bindings/memory/rk3399-dram.h> 8 9/ { 10 ddr_timing: ddr_timing { 11 compatible = "rockchip,ddr-timing"; 12 ddr3_speed_bin = <21>; 13 pd_idle = <0>; 14 sr_idle = <0>; 15 sr_mc_gate_idle = <0>; 16 srpd_lite_idle = <0>; 17 standby_idle = <0>; 18 auto_lp_dis_freq = <666>; 19 ddr3_dll_dis_freq = <300>; 20 phy_dll_dis_freq = <260>; 21 22 ddr3_odt_dis_freq = <666>; 23 ddr3_drv = <DDR3_DS_40ohm>; 24 ddr3_odt = <DDR3_ODT_120ohm>; 25 phy_ddr3_ca_drv = <PHY_DRV_ODT_40>; 26 phy_ddr3_dq_drv = <PHY_DRV_ODT_40>; 27 phy_ddr3_odt = <PHY_DRV_ODT_240>; 28 29 lpddr3_odt_dis_freq = <666>; 30 lpddr3_drv = <LP3_DS_34ohm>; 31 lpddr3_odt = <LP3_ODT_240ohm>; 32 phy_lpddr3_ca_drv = <PHY_DRV_ODT_34_3>; 33 phy_lpddr3_dq_drv = <PHY_DRV_ODT_34_3>; 34 phy_lpddr3_odt = <PHY_DRV_ODT_240>; 35 36 lpddr4_odt_dis_freq = <800>; 37 lpddr4_drv = <LP4_PDDS_240ohm>; 38 lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>; 39 lpddr4_ca_odt = <LP4_CA_ODT_DIS>; 40 phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>; 41 phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_40>; 42 phy_lpddr4_dq_drv = <PHY_DRV_ODT_60>; 43 phy_lpddr4_odt = <PHY_DRV_ODT_40>; 44 }; 45}; 46