xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3368-android.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4 *
5 */
6
7/ {
8	chosen: chosen {
9		bootargs = "earlycon=uart8250,mmio32,0xff690000 firmware_class.path=/system/vendor/firmware";
10	};
11
12	fiq_debugger: fiq-debugger {
13		compatible = "rockchip,fiq-debugger";
14		rockchip,serial-id = <2>;
15		rockchip,wake-irq = <0>;
16		rockchip,irq-mode-enable = <0>;  /* If enable uart uses irq instead of fiq */
17		rockchip,baudrate = <115200>;  /* Only 115200 and 1500000 */
18		pinctrl-names = "default";
19		pinctrl-0 = <&uart2_xfer>;
20		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;   /* signal irq */
21	};
22
23	reserved-memory {
24		#address-cells = <2>;
25		#size-cells = <2>;
26		ranges;
27
28		drm_logo: drm-logo@00000000 {
29			compatible = "rockchip,drm-logo";
30			reg = <0x0 0x0 0x0 0x0>;
31		};
32
33		ramoops: ramoops@110000 {
34			compatible = "ramoops";
35			reg = <0x0 0x110000 0x0 0xf0000>;
36			record-size = <0x20000>;
37			console-size = <0x80000>;
38			ftrace-size = <0x00000>;
39			pmsg-size = <0x50000>;
40		};
41
42		/* global autoconfigured region for contiguous allocations */
43		linux,cma {
44			compatible = "shared-dma-pool";
45			reusable;
46			size = <0x0 0x2000000>;
47			linux,cma-default;
48		};
49	};
50
51	ion {
52		compatible = "rockchip,ion";
53		#address-cells = <1>;
54		#size-cells = <0>;
55
56		cma-heap {
57			reg = <0x00000000 0x2800000>;
58		};
59
60		system-heap {
61		};
62	};
63
64	firmware {
65		firmware_android: android {};
66
67		optee: optee {
68			compatible = "linaro,optee-tz";
69			method = "smc";
70		};
71	};
72
73	rga@ff920000 {
74		compatible = "rockchip,rga2";
75		dev_mode = <1>;
76		reg = <0x0 0xff920000 0x0 0x1000>;
77		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
78		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
79		clock-names = "aclk_rga", "hclk_rga", "clk_rga";
80		status = "okay";
81	};
82};
83
84&cluster1_opp {
85	rockchip,avs = <1>;
86};
87
88&display_subsystem {
89	status = "okay";
90
91	logo-memory-region = <&drm_logo>;
92	route {
93		route_dsi: route-dsi {
94			status = "disabled";
95			logo,uboot = "logo.bmp";
96			logo,kernel = "logo_kernel.bmp";
97			logo,mode = "center";
98			charge_logo,mode = "center";
99			connect = <&vop_out_dsi>;
100		};
101
102		route_edp: route-edp {
103			status = "disabled";
104			logo,uboot = "logo.bmp";
105			logo,kernel = "logo_kernel.bmp";
106			logo,mode = "center";
107			charge_logo,mode = "center";
108			connect = <&vop_out_edp>;
109		};
110
111		route_hdmi: route-hdmi {
112			status = "disabled";
113			logo,uboot = "logo.bmp";
114			logo,kernel = "logo_kernel.bmp";
115			logo,mode = "center";
116			charge_logo,mode = "center";
117			connect = <&vop_out_hdmi>;
118		};
119
120		route_lvds: route-lvds {
121			status = "disabled";
122			logo,uboot = "logo.bmp";
123			logo,kernel = "logo_kernel.bmp";
124			logo,mode = "center";
125			charge_logo,mode = "center";
126			connect = <&vop_out_lvds>;
127		};
128
129		route_rgb: route-rgb {
130			status = "disabled";
131			logo,uboot = "logo.bmp";
132			logo,kernel = "logo_kernel.bmp";
133			logo,mode = "center";
134			charge_logo,mode = "center";
135			connect = <&vop_out_rgb>;
136		};
137
138	};
139};
140
141&dsi {
142	panel@0 {
143		reg = <0>;
144
145		ports {
146			#address-cells = <1>;
147			#size-cells = <0>;
148
149			port@0 {
150				reg = <0>;
151
152				panel_in_dsi: endpoint {
153					remote-endpoint = <&dsi_out_panel>;
154				};
155			};
156		};
157	};
158
159	ports {
160		#address-cells = <1>;
161		#size-cells = <0>;
162
163		port@1 {
164			reg = <1>;
165
166			dsi_out_panel: endpoint {
167				remote-endpoint = <&panel_in_dsi>;
168			};
169		};
170	};
171};
172
173&hevc {
174	status = "okay";
175};
176
177&hevc_mmu {
178	status = "okay";
179};
180
181&iep {
182	status = "okay";
183};
184
185&iep_mmu {
186	status = "okay";
187};
188
189&mailbox {
190	status = "okay";
191};
192
193&mailbox_scpi {
194	status = "okay";
195};
196
197&mpp_srv {
198	status = "okay";
199};
200
201&vdpu {
202	status = "okay";
203};
204
205&vepu {
206	status = "okay";
207};
208
209&vpu_mmu {
210	status = "okay";
211};
212
213&vop {
214	support-multi-area;
215	status = "okay";
216};
217
218&vop_mmu {
219	status = "okay";
220};
221
222&isp {
223	status = "okay";
224};
225
226&isp_mmu {
227	status = "okay";
228};
229
230&cif {
231	status = "okay";
232};
233
234&rng {
235	status = "okay";
236};
237
238&vip_mmu {
239	status = "okay";
240};
241
242&video_phy {
243	status = "okay";
244};
245
246&usb_otg {
247	status = "okay";
248};
249
250&pinctrl {
251	isp {
252		cif_clkout: cif-clkout {
253			rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;//cif_clkout
254		};
255
256		isp_dvp_d2d9: isp-dvp-d2d9 {
257			rockchip,pins =
258					<1 RK_PA0 1 &pcfg_pull_none>,//cif_data2
259					<1 RK_PA1 1 &pcfg_pull_none>,//cif_data3
260					<1 RK_PA2 1 &pcfg_pull_none>,//cif_data4
261					<1 RK_PA3 1 &pcfg_pull_none>,//cif_data5
262					<1 RK_PA4 1 &pcfg_pull_none>,//cif_data6
263					<1 RK_PA5 1 &pcfg_pull_none>,//cif_data7
264					<1 RK_PA6 1 &pcfg_pull_none>,//cif_data8
265					<1 RK_PA7 1 &pcfg_pull_none>,//cif_data9
266					<1 RK_PB0 1 &pcfg_pull_none>,//cif_sync
267					<1 RK_PB1 1 &pcfg_pull_none>,//cif_href
268					<1 RK_PB2 1 &pcfg_pull_none>,//cif_clkin
269					<1 RK_PB3 1 &pcfg_pull_none>;//cif_clkout
270		};
271
272		isp_dvp_d0d1: isp-dvp-d0d1 {
273			rockchip,pins =
274					<1 RK_PB4 1 &pcfg_pull_none>,//cif_data0
275					<1 RK_PB5 1 &pcfg_pull_none>;//cif_data1
276		};
277
278		isp_dvp_d10d11:isp_d10d11 {
279			rockchip,pins =
280					<1 RK_PB6 1 &pcfg_pull_none>,//cif_data10
281					<1 RK_PB7 1 &pcfg_pull_none>;//cif_data11
282		};
283
284		isp_dvp_d0d7: isp-dvp-d0d7 {
285			rockchip,pins =
286					<1 RK_PB4 1 &pcfg_pull_none>,//cif_data0
287					<1 RK_PB5 1 &pcfg_pull_none>,//cif_data1
288					<1 RK_PA0 1 &pcfg_pull_none>,//cif_data2
289					<1 RK_PA1 1 &pcfg_pull_none>,//cif_data3
290					<1 RK_PA2 1 &pcfg_pull_none>,//cif_data4
291					<1 RK_PA3 1 &pcfg_pull_none>,//cif_data5
292					<1 RK_PA4 1 &pcfg_pull_none>,//cif_data6
293					<1 RK_PA5 1 &pcfg_pull_none>;//cif_data7
294		};
295
296		isp_dvp_d4d11: isp-dvp-d4d11 {
297			rockchip,pins =
298					<1 RK_PA2 1 &pcfg_pull_none>,//cif_data4
299					<1 RK_PA3 1 &pcfg_pull_none>,//cif_data5
300					<1 RK_PA4 1 &pcfg_pull_none>,//cif_data6
301					<1 RK_PA5 1 &pcfg_pull_none>,//cif_data7
302					<1 RK_PA6 1 &pcfg_pull_none>,//cif_data8
303					<1 RK_PA7 1 &pcfg_pull_none>,//cif_data9
304					<1 RK_PB6 1 &pcfg_pull_none>,//cif_data10
305					<1 RK_PC1 1 &pcfg_pull_none>;//cif_data11
306		};
307
308		isp_shutter: isp-shutter {
309			rockchip,pins =
310					<3 RK_PC3 2 &pcfg_pull_none>, //SHUTTEREN
311					<3 RK_PC6 2 &pcfg_pull_none>;//SHUTTERTRIG
312		};
313
314		isp_flash_trigger: isp-flash-trigger {
315			rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
316		};
317
318		isp_prelight: isp-prelight {
319			rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
320		};
321
322		isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
323			rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
324		};
325	};
326};
327