1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd 4 * 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/display/drm_mipi_dsi.h> 11#include "rk3358.dtsi" 12 13/ { 14 adc-keys { 15 compatible = "adc-keys"; 16 io-channels = <&saradc 2>; 17 io-channel-names = "buttons"; 18 poll-interval = <100>; 19 keyup-threshold-microvolt = <1800000>; 20 21 vol-down-key { 22 linux,code = <KEY_VOLUMEDOWN>; 23 label = "volume down"; 24 press-threshold-microvolt = <300000>; 25 }; 26 27 vol-up-key { 28 linux,code = <KEY_VOLUMEUP>; 29 label = "volume up"; 30 press-threshold-microvolt = <17000>; 31 }; 32 }; 33 34 backlight: backlight { 35 compatible = "pwm-backlight"; 36 pwms = <&pwm1 0 25000 0>; 37 brightness-levels = < 38 0 1 2 3 4 5 6 7 39 8 9 10 11 12 13 14 15 40 16 17 18 19 20 21 22 23 41 24 25 26 27 28 29 30 31 42 32 33 34 35 36 37 38 39 43 40 41 42 43 44 45 46 47 44 48 49 50 51 52 53 54 55 45 56 57 58 59 60 61 62 63 46 64 65 66 67 68 69 70 71 47 72 73 74 75 76 77 78 79 48 80 81 82 83 84 85 86 87 49 88 89 90 91 92 93 94 95 50 96 97 98 99 100 101 102 103 51 104 105 106 107 108 109 110 111 52 112 113 114 115 116 117 118 119 53 120 121 122 123 124 125 126 127 54 128 129 130 131 132 133 134 135 55 136 137 138 139 140 141 142 143 56 144 145 146 147 148 149 150 151 57 152 153 154 155 156 157 158 159 58 160 161 162 163 164 165 166 167 59 168 169 170 171 172 173 174 175 60 176 177 178 179 180 181 182 183 61 184 185 186 187 188 189 190 191 62 192 193 194 195 196 197 198 199 63 200 201 202 203 204 205 206 207 64 208 209 210 211 212 213 214 215 65 216 217 218 219 220 221 222 223 66 224 225 226 227 228 229 230 231 67 232 233 234 235 236 237 238 239 68 240 241 242 243 244 245 246 247 69 248 249 250 251 252 253 254 255>; 70 default-brightness-level = <200>; 71 }; 72 73 backlight_2: backlight-2 { 74 compatible = "pwm-backlight"; 75 pwms = <&pwm3 0 10000000 0>; 76 pinctrl-names = "default"; 77 pinctrl-0 = <&lcd0_pwren &lcd0_rst>; 78 enable-gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_HIGH>; 79 brightness-levels = < 80 0 1 2 3 4 5 6 7 81 8 9 10 11 12 13 14 15 82 16 17 18 19 20 21 22 23 83 24 25 26 27 28 29 30 31 84 32 33 34 35 36 37 38 39 85 40 41 42 43 44 45 46 47 86 48 49 50 51 52 53 54 55 87 56 57 58 59 60 61 62 63 88 64 65 66 67 68 69 70 71 89 72 73 74 75 76 77 78 79 90 80 81 82 83 84 85 86 87 91 88 89 90 91 92 93 94 95 92 96 97 98 99 100 101 102 103 93 104 105 106 107 108 109 110 111 94 112 113 114 115 116 117 118 119 95 120 121 122 123 124 125 126 127 96 128 129 130 131 132 133 134 135 97 136 137 138 139 140 141 142 143 98 144 145 146 147 148 149 150 151 99 152 153 154 155 156 157 158 159 100 160 161 162 163 164 165 166 167 101 168 169 170 171 172 173 174 175 102 176 177 178 179 180 181 182 183 103 184 185 186 187 188 189 190 191 104 192 193 194 195 196 197 198 199 105 200 201 202 203 204 205 206 207 106 208 209 210 211 212 213 214 215 107 216 217 218 219 220 221 222 223 108 224 225 226 227 228 229 230 231 109 232 233 234 235 236 237 238 239 110 240 241 242 243 244 245 246 247 111 248 249 250 251 252 253 254 255>; 112 default-brightness-level = <60>; 113 }; 114 115 /* The THine 827-Q (rgb to dual lvds) don't need driver */ 116 panel-rgb { 117 compatible = "simple-panel"; 118 #address-cells = <1>; 119 #size-cells = <0>; 120 121 pinctrl-names = "default"; 122 pinctrl-0 = <&pwdn_rgb>; /* This the pwdn of THine-827-Q */ 123 power-supply = <&vcc3v3_lcd>; 124 backlight = <&backlight_2>; 125 enable-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; 126 reset-gpios = <&gpio1 RK_PD7 GPIO_ACTIVE_LOW>; 127 prepare-delay-ms = <0>; 128 reset-delay-ms = <0>; 129 init-delay-ms = <0>; 130 enable-delay-ms = <5>; 131 disable-delay-ms = <10>; 132 unprepare-delay-ms = <0>; 133 134 width-mm = <292>; 135 height-mm = <109>; 136 137 bus-format = <MEDIA_BUS_FMT_RGB888_1X24>; 138 139 display-timings { 140 native-mode = <&timing1>; 141 142 timing1: timing1 { 143 clock-frequency = <88200000>; 144 hactive = <1920>; 145 vactive = <720>; 146 hfront-porch = <40>; 147 hsync-len = <20>; 148 hback-porch = <24>; 149 vfront-porch = <5>; 150 vsync-len = <4>; 151 vback-porch = <4>; 152 hsync-active = <0>; 153 vsync-active = <0>; 154 de-active = <0>; 155 pixelclk-active = <0>; 156 }; 157 }; 158 159 ports { 160 #address-cells = <1>; 161 #size-cells = <0>; 162 163 port@0 { 164 reg = <0>; 165 panel_in_rgb: endpoint { 166 remote-endpoint = <&rgb_out_panel>; 167 }; 168 }; 169 }; 170 }; 171 172 173 rk809-sound { 174 compatible = "simple-audio-card"; 175 simple-audio-card,format = "i2s"; 176 simple-audio-card,name = "rockchip,rk809-codec"; 177 simple-audio-card,mclk-fs = <256>; 178 simple-audio-card,widgets = 179 "Microphone", "Mic Jack", 180 "Headphone", "Headphone Jack"; 181 simple-audio-card,routing = 182 "Mic Jack", "MICBIAS1", 183 "IN1P", "Mic Jack", 184 "Headphone Jack", "HPOL", 185 "Headphone Jack", "HPOR"; 186 simple-audio-card,cpu { 187 sound-dai = <&i2s1_2ch>; 188 }; 189 simple-audio-card,codec { 190 sound-dai = <&rk809_codec>; 191 }; 192 }; 193 194 sdio_pwrseq: sdio-pwrseq { 195 compatible = "mmc-pwrseq-simple"; 196 pinctrl-names = "default"; 197 pinctrl-0 = <&wifi_enable_h>; 198 199 /* 200 * On the module itself this is one of these (depending 201 * on the actual card populated): 202 * - SDIO_RESET_L_WL_REG_ON 203 * - PDN (power down when low) 204 */ 205 reset-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; 206 }; 207 208 vcc5v0_sys: vccsys { 209 compatible = "regulator-fixed"; 210 regulator-name = "vcc5v0_sys"; 211 regulator-always-on; 212 regulator-boot-on; 213 regulator-min-microvolt = <5000000>; 214 regulator-max-microvolt = <5000000>; 215 }; 216 217 wireless-wlan { 218 compatible = "wlan-platdata"; 219 wifi_chip_type = "AP6212"; 220 WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; 221 status = "okay"; 222 }; 223 224 wireless-bluetooth { 225 compatible = "bluetooth-platdata"; 226 clocks = <&rk809 1>; 227 clock-names = "ext_clock"; 228 uart_rts_gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; 229 pinctrl-names = "default","rts_gpio"; 230 pinctrl-0 = <&uart1_rts>; 231 pinctrl-1 = <&uart1_rts_gpio>; 232 BT,reset_gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; 233 BT,wake_gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; 234 BT,wake_host_irq = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; 235 status = "okay"; 236 }; 237}; 238 239&display_subsystem { 240 status = "okay"; 241}; 242 243&dsi { 244 status = "disabled"; 245 246 panel@0 { 247 compatible = "sitronix,st7703", "simple-panel-dsi"; 248 reg = <0>; 249 250 pinctrl-names = "default"; 251 pinctrl-0 = <&mipi_en>; 252 enable-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; 253 254 backlight = <&backlight>; 255 prepare-delay-ms = <0>; 256 reset-delay-ms = <0>; 257 init-delay-ms = <80>; 258 enable-delay-ms = <0>; 259 disable-delay-ms = <10>; 260 unprepare-delay-ms = <60>; 261 262 width-mm = <68>; 263 height-mm = <121>; 264 265 dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 266 MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 267 dsi,format = <MIPI_DSI_FMT_RGB888>; 268 dsi,lanes = <4>; 269 270 panel-init-sequence = [ 271 39 00 04 ff 98 81 03 272 15 00 02 01 00 273 15 00 02 02 00 274 15 00 02 03 53 275 15 00 02 04 53 276 15 00 02 05 13 277 15 00 02 06 04 278 15 00 02 07 02 279 15 00 02 08 02 280 15 00 02 09 00 281 15 00 02 0a 00 282 15 00 02 0b 00 283 15 00 02 0c 00 284 15 00 02 0d 00 285 15 00 02 0e 00 286 15 00 02 0f 00 287 288 15 00 02 10 00 289 15 00 02 11 00 290 15 00 02 12 00 291 15 00 02 13 00 292 15 00 02 14 00 293 15 00 02 15 08 294 15 00 02 16 10 295 15 00 02 17 00 296 15 00 02 18 08 297 15 00 02 19 00 298 15 00 02 1a 00 299 15 00 02 1b 00 300 15 00 02 1c 00 301 15 00 02 1d 00 302 15 00 02 1e c0 303 15 00 02 1f 80 304 305 15 00 02 20 02 306 15 00 02 21 09 307 15 00 02 22 00 308 15 00 02 23 00 309 15 00 02 24 00 310 15 00 02 25 00 311 15 00 02 26 00 312 15 00 02 27 00 313 15 00 02 28 55 314 15 00 02 29 03 315 15 00 02 2a 00 316 15 00 02 2b 00 317 15 00 02 2c 00 318 15 00 02 2d 00 319 15 00 02 2e 00 320 15 00 02 2f 00 321 322 15 00 02 30 00 323 15 00 02 31 00 324 15 00 02 32 00 325 15 00 02 33 00 326 15 00 02 34 04 327 15 00 02 35 05 328 15 00 02 36 05 329 15 00 02 37 00 330 15 00 02 38 3c 331 15 00 02 39 35 332 15 00 02 3a 00 333 15 00 02 3b 40 334 15 00 02 3c 00 335 15 00 02 3d 00 336 15 00 02 3e 00 337 15 00 02 3f 00 338 339 15 00 02 40 00 340 15 00 02 41 88 341 15 00 02 42 00 342 15 00 02 43 00 343 15 00 02 44 1f 344 345 15 00 02 50 01 346 15 00 02 51 23 347 15 00 02 52 45 348 15 00 02 53 67 349 15 00 02 54 89 350 15 00 02 55 ab 351 15 00 02 56 01 352 15 00 02 57 23 353 15 00 02 58 45 354 15 00 02 59 67 355 15 00 02 5a 89 356 15 00 02 5b ab 357 15 00 02 5c cd 358 15 00 02 5d ef 359 15 00 02 5e 03 360 15 00 02 5f 14 361 362 15 00 02 60 15 363 15 00 02 61 0c 364 15 00 02 62 0d 365 15 00 02 63 0e 366 15 00 02 64 0f 367 15 00 02 65 10 368 15 00 02 66 11 369 15 00 02 67 08 370 15 00 02 68 02 371 15 00 02 69 0a 372 15 00 02 6a 02 373 15 00 02 6b 02 374 15 00 02 6c 02 375 15 00 02 6d 02 376 15 00 02 6e 02 377 15 00 02 6f 02 378 379 15 00 02 70 02 380 15 00 02 71 02 381 15 00 02 72 06 382 15 00 02 73 02 383 15 00 02 74 02 384 15 00 02 75 14 385 15 00 02 76 15 386 15 00 02 77 0f 387 15 00 02 78 0e 388 15 00 02 79 0d 389 15 00 02 7a 0c 390 15 00 02 7b 11 391 15 00 02 7c 10 392 15 00 02 7d 06 393 15 00 02 7e 02 394 15 00 02 7f 0a 395 396 15 00 02 80 02 397 15 00 02 81 02 398 15 00 02 82 02 399 15 00 02 83 02 400 15 00 02 84 02 401 15 00 02 85 02 402 15 00 02 86 02 403 15 00 02 87 02 404 15 00 02 88 08 405 15 00 02 89 02 406 15 00 02 8a 02 407 408 39 00 04 ff 98 81 04 409 15 00 02 00 80 410 15 00 02 70 00 411 15 00 02 71 00 412 15 00 02 66 fe 413 15 00 02 82 15 414 15 00 02 84 15 415 15 00 02 85 15 416 15 00 02 3a 24 417 15 00 02 32 ac 418 15 00 02 8c 80 419 15 00 02 3c f5 420 15 00 02 88 33 421 422 39 00 04 ff 98 81 01 423 15 00 02 22 0a 424 15 00 02 31 00 425 15 00 02 53 78 426 15 00 02 50 5b 427 15 00 02 51 5b 428 15 00 02 60 20 429 15 00 02 61 00 430 15 00 02 62 0d 431 15 00 02 63 00 432 433 15 00 02 a0 00 434 15 00 02 a1 10 435 15 00 02 a2 1c 436 15 00 02 a3 13 437 15 00 02 a4 15 438 15 00 02 a5 26 439 15 00 02 a6 1a 440 15 00 02 a7 1d 441 15 00 02 a8 67 442 15 00 02 a9 1c 443 15 00 02 aa 29 444 15 00 02 ab 5b 445 15 00 02 ac 26 446 15 00 02 ad 28 447 15 00 02 ae 5c 448 15 00 02 af 30 449 15 00 02 b0 31 450 15 00 02 b1 2e 451 15 00 02 b2 32 452 15 00 02 b3 00 453 454 15 00 02 c0 00 455 15 00 02 c1 10 456 15 00 02 c2 1c 457 15 00 02 c3 13 458 15 00 02 c4 15 459 15 00 02 c5 26 460 15 00 02 c6 1a 461 15 00 02 c7 1d 462 15 00 02 c8 67 463 15 00 02 c9 1c 464 15 00 02 ca 29 465 15 00 02 cb 5b 466 15 00 02 cc 26 467 15 00 02 cd 28 468 15 00 02 ce 5c 469 15 00 02 cf 30 470 15 00 02 d0 31 471 15 00 02 d1 2e 472 15 00 02 d2 32 473 15 00 02 d3 00 474 39 00 04 ff 98 81 00 475 05 00 01 11 476 05 01 01 29 477 ]; 478 479 panel-exit-sequence = [ 480 05 00 01 28 481 05 00 01 10 482 ]; 483 484 display-timings { 485 native-mode = <&timing0>; 486 487 timing0: timing0 { 488 clock-frequency = <64000000>; 489 hactive = <720>; 490 vactive = <1280>; 491 hfront-porch = <40>; 492 hsync-len = <10>; 493 hback-porch = <40>; 494 vfront-porch = <22>; 495 vsync-len = <4>; 496 vback-porch = <11>; 497 hsync-active = <0>; 498 vsync-active = <0>; 499 de-active = <0>; 500 pixelclk-active = <0>; 501 }; 502 }; 503 504 ports { 505 #address-cells = <1>; 506 #size-cells = <0>; 507 508 port@0 { 509 reg = <0>; 510 panel_in_dsi: endpoint { 511 remote-endpoint = <&dsi_out_panel>; 512 }; 513 }; 514 }; 515 }; 516 517 ports { 518 #address-cells = <1>; 519 #size-cells = <0>; 520 521 port@1 { 522 reg = <1>; 523 dsi_out_panel: endpoint { 524 remote-endpoint = <&panel_in_dsi>; 525 }; 526 }; 527 }; 528}; 529 530&dsi_in_vopb { 531 status = "disabled"; 532}; 533 534&dsi_in_vopl { 535 status = "disabled"; 536}; 537 538&route_dsi { 539 connect = <&vopb_out_dsi>; 540 status = "disabled"; 541}; 542 543&rgb { 544 status = "okay"; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 548 /delete-property/ phys; 549 /delete-property/ phy-names; 550 551 pinctrl-0 = <&lcdc_m0_rgb_pins>; 552 pinctrl-1 = <&lcdc_m0_sleep_pins>; 553 554 ports { 555 port@1 { 556 reg = <1>; 557 558 rgb_out_panel: endpoint { 559 remote-endpoint = <&panel_in_rgb>; 560 }; 561 }; 562 }; 563}; 564 565&rgb_in_vopb { 566 status = "okay"; 567}; 568 569&rgb_in_vopl { 570 status = "disabled"; 571}; 572 573&route_rgb { 574 connect = <&vopb_out_rgb>; 575 status = "okay"; 576}; 577 578&cpu0 { 579 cpu-supply = <&vdd_arm>; 580}; 581 582&dfi { 583 status = "okay"; 584}; 585 586&dmc { 587 center-supply = <&vdd_logic>; 588 status = "okay"; 589}; 590 591&emmc { 592 bus-width = <8>; 593 cap-mmc-highspeed; 594 mmc-hs200-1_8v; 595 supports-emmc; 596 disable-wp; 597 non-removable; 598 num-slots = <1>; 599 status = "okay"; 600}; 601 602&gpu { 603 mali-supply = <&vdd_logic>; 604 status = "okay"; 605}; 606 607&i2c0 { 608 status = "okay"; 609 clock-frequency = <400000>; 610 611 rk809: pmic@20 { 612 compatible = "rockchip,rk809"; 613 reg = <0x20>; 614 interrupt-parent = <&gpio0>; 615 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 616 pinctrl-names = "default", "pmic-sleep", 617 "pmic-power-off", "pmic-reset"; 618 pinctrl-0 = <&pmic_int>; 619 pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; 620 pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; 621 pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; 622 rockchip,system-power-controller; 623 wakeup-source; 624 #clock-cells = <1>; 625 clock-output-names = "rk808-clkout1", "rk808-clkout2"; 626 //fb-inner-reg-idxs = <2>; 627 /* 1: rst regs (default in codes), 0: rst the pmic */ 628 pmic-reset-func = <1>; 629 630 vcc1-supply = <&vcc5v0_sys>; 631 vcc2-supply = <&vcc5v0_sys>; 632 vcc3-supply = <&vcc5v0_sys>; 633 vcc4-supply = <&vcc5v0_sys>; 634 vcc5-supply = <&vcc3v3_sys>; 635 vcc6-supply = <&vcc3v3_sys>; 636 vcc7-supply = <&vcc3v3_sys>; 637 vcc8-supply = <&vcc3v3_sys>; 638 vcc9-supply = <&vcc5v0_sys>; 639 640 pwrkey { 641 status = "okay"; 642 }; 643 644 pinctrl_rk8xx: pinctrl_rk8xx { 645 gpio-controller; 646 #gpio-cells = <2>; 647 648 rk817_slppin_null: rk817_slppin_null { 649 pins = "gpio_slp"; 650 function = "pin_fun0"; 651 }; 652 653 rk817_slppin_slp: rk817_slppin_slp { 654 pins = "gpio_slp"; 655 function = "pin_fun1"; 656 }; 657 658 rk817_slppin_pwrdn: rk817_slppin_pwrdn { 659 pins = "gpio_slp"; 660 function = "pin_fun2"; 661 }; 662 663 rk817_slppin_rst: rk817_slppin_rst { 664 pins = "gpio_slp"; 665 function = "pin_fun3"; 666 }; 667 }; 668 669 regulators { 670 vdd_logic: DCDC_REG1 { 671 regulator-always-on; 672 regulator-boot-on; 673 regulator-min-microvolt = <950000>; 674 regulator-max-microvolt = <1350000>; 675 regulator-ramp-delay = <6001>; 676 regulator-initial-mode = <0x2>; 677 regulator-name = "vdd_logic"; 678 regulator-state-mem { 679 regulator-on-in-suspend; 680 regulator-suspend-microvolt = <950000>; 681 }; 682 }; 683 684 vdd_arm: DCDC_REG2 { 685 regulator-always-on; 686 regulator-boot-on; 687 regulator-min-microvolt = <950000>; 688 regulator-max-microvolt = <1350000>; 689 regulator-ramp-delay = <6001>; 690 regulator-initial-mode = <0x2>; 691 regulator-name = "vdd_arm"; 692 regulator-state-mem { 693 regulator-off-in-suspend; 694 regulator-suspend-microvolt = <950000>; 695 }; 696 }; 697 698 vcc_ddr: DCDC_REG3 { 699 regulator-always-on; 700 regulator-boot-on; 701 regulator-name = "vcc_ddr"; 702 regulator-initial-mode = <0x2>; 703 regulator-state-mem { 704 regulator-on-in-suspend; 705 }; 706 }; 707 708 vcc_3v3: DCDC_REG4 { 709 regulator-always-on; 710 regulator-boot-on; 711 regulator-min-microvolt = <3300000>; 712 regulator-max-microvolt = <3300000>; 713 regulator-initial-mode = <0x2>; 714 regulator-name = "vcc_3v3"; 715 regulator-state-mem { 716 regulator-on-in-suspend; 717 regulator-suspend-microvolt = <3300000>; 718 }; 719 }; 720 721 vcc_1v0: LDO_REG1 { 722 regulator-always-on; 723 regulator-boot-on; 724 regulator-min-microvolt = <1000000>; 725 regulator-max-microvolt = <1000000>; 726 regulator-name = "vcc_1v0"; 727 regulator-state-mem { 728 regulator-on-in-suspend; 729 regulator-suspend-microvolt = <1000000>; 730 }; 731 }; 732 733 vcc_1v8: LDO_REG2 { 734 regulator-always-on; 735 regulator-boot-on; 736 regulator-min-microvolt = <1800000>; 737 regulator-max-microvolt = <1800000>; 738 739 regulator-name = "vcc_1v8"; 740 regulator-state-mem { 741 regulator-on-in-suspend; 742 regulator-suspend-microvolt = <1800000>; 743 }; 744 }; 745 746 vdd_1v0: LDO_REG3 { 747 regulator-always-on; 748 regulator-boot-on; 749 regulator-min-microvolt = <1000000>; 750 regulator-max-microvolt = <1000000>; 751 752 regulator-name = "vdd_1v0"; 753 regulator-state-mem { 754 regulator-on-in-suspend; 755 regulator-suspend-microvolt = <1000000>; 756 }; 757 }; 758 759 vcc3v3_pmu: LDO_REG4 { 760 regulator-always-on; 761 regulator-boot-on; 762 regulator-min-microvolt = <3300000>; 763 regulator-max-microvolt = <3300000>; 764 765 regulator-name = "vcc3v3_pmu"; 766 regulator-state-mem { 767 regulator-on-in-suspend; 768 regulator-suspend-microvolt = <3000000>; 769 770 }; 771 }; 772 773 vccio_sd: LDO_REG5 { 774 regulator-always-on; 775 regulator-boot-on; 776 regulator-min-microvolt = <1800000>; 777 regulator-max-microvolt = <3300000>; 778 779 regulator-name = "vccio_sd"; 780 regulator-state-mem { 781 regulator-on-in-suspend; 782 regulator-suspend-microvolt = <3300000>; 783 }; 784 }; 785 786 vcc_sd: LDO_REG6 { 787 regulator-min-microvolt = <3300000>; 788 regulator-max-microvolt = <3300000>; 789 regulator-boot-off; 790 791 regulator-name = "vcc_sd"; 792 regulator-state-mem { 793 regulator-off-in-suspend; 794 regulator-suspend-microvolt = <3300000>; 795 796 }; 797 }; 798 799 vcc2v8_dvp: LDO_REG7 { 800 regulator-boot-on; 801 regulator-min-microvolt = <2800000>; 802 regulator-max-microvolt = <2800000>; 803 804 regulator-name = "vcc2v8_dvp"; 805 regulator-state-mem { 806 regulator-off-in-suspend; 807 regulator-suspend-microvolt = <2800000>; 808 }; 809 }; 810 811 vcc1v8_dvp: LDO_REG8 { 812 regulator-boot-on; 813 regulator-min-microvolt = <1800000>; 814 regulator-max-microvolt = <1800000>; 815 816 regulator-name = "vcc1v8_dvp"; 817 regulator-state-mem { 818 regulator-on-in-suspend; 819 regulator-suspend-microvolt = <1800000>; 820 }; 821 }; 822 823 vdd1v5_dvp: LDO_REG9 { 824 regulator-boot-on; 825 regulator-min-microvolt = <1500000>; 826 regulator-max-microvolt = <1500000>; 827 828 regulator-name = "vdd1v5_dvp"; 829 regulator-state-mem { 830 regulator-off-in-suspend; 831 regulator-suspend-microvolt = <1500000>; 832 }; 833 }; 834 835 vcc3v3_sys: DCDC_REG5 { 836 regulator-always-on; 837 regulator-boot-on; 838 regulator-min-microvolt = <3300000>; 839 regulator-max-microvolt = <3300000>; 840 regulator-name = "vcc3v3_sys"; 841 regulator-state-mem { 842 regulator-on-in-suspend; 843 regulator-suspend-microvolt = <3300000>; 844 }; 845 }; 846 847 vcc5v0_host: SWITCH_REG1 { 848 regulator-always-on; 849 regulator-boot-on; 850 regulator-name = "vcc5v0_host"; 851 }; 852 853 vcc3v3_lcd: SWITCH_REG2 { 854 regulator-boot-on; 855 regulator-name = "vcc3v3_lcd"; 856 }; 857 }; 858 859 rk809_codec: codec { 860 #sound-dai-cells = <0>; 861 compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; 862 clocks = <&cru SCLK_I2S1_OUT>; 863 clock-names = "mclk"; 864 pinctrl-names = "default"; 865 pinctrl-0 = <&i2s1_2ch_mclk>; 866 hp-volume = <20>; 867 spk-volume = <3>; 868 status = "okay"; 869 }; 870 }; 871}; 872 873&i2c1 { 874 status = "okay"; 875 876 clock-frequency = <400000>; 877 878 /* These are relatively safe rise/fall times; TODO: measure */ 879 i2c-scl-falling-time-ns = <50>; 880 i2c-scl-rising-time-ns = <300>; 881}; 882 883&i2s1_2ch { 884 status = "okay"; 885 #sound-dai-cells = <0>; 886}; 887 888&io_domains { 889 status = "okay"; 890 891 vccio1-supply = <&vcc_3v3>; 892 vccio2-supply = <&vcc_3v3>; 893 vccio3-supply = <&vcc_3v3>; 894 vccio4-supply = <&vcc3v3_pmu>; 895 vccio5-supply = <&vcc_1v8>; 896}; 897 898&isp_mmu { 899 status = "okay"; 900}; 901 902&mipi_dphy_rx0 { 903 status = "okay"; 904 905 ports { 906 #address-cells = <1>; 907 #size-cells = <0>; 908 909 port@0 { 910 reg = <0>; 911 #address-cells = <1>; 912 #size-cells = <0>; 913 914 mipi_in_ucam: endpoint@1 { 915 reg = <1>; 916 // remote-endpoint = <&ucam_out>; 917 data-lanes = <1 2>; 918 }; 919 }; 920 921 port@1 { 922 reg = <1>; 923 #address-cells = <1>; 924 #size-cells = <0>; 925 926 dphy_rx0_out: endpoint@0 { 927 reg = <0>; 928 remote-endpoint = <&isp0_mipi_in>; 929 }; 930 }; 931 }; 932}; 933 934&pmu_io_domains { 935 status = "okay"; 936 937 pmuio1-supply = <&vcc3v3_pmu>; 938 pmuio2-supply = <&vcc3v3_pmu>; 939}; 940 941&pwm1 { 942 status = "okay"; 943}; 944 945&pwm3 { 946 status = "okay"; 947}; 948 949&rk_rga { 950 status = "okay"; 951}; 952 953&rkisp1 { 954 status = "okay"; 955 956 port { 957 #address-cells = <1>; 958 #size-cells = <0>; 959 960 isp0_mipi_in: endpoint@0 { 961 reg = <0>; 962 remote-endpoint = <&dphy_rx0_out>; 963 }; 964 }; 965}; 966 967&saradc { 968 status = "okay"; 969 vref-supply = <&vcc_1v8>; 970}; 971 972&sdio { 973 bus-width = <4>; 974 cap-sd-highspeed; 975 supports-sdio; 976 ignore-pm-notify; 977 keep-power-in-suspend; 978 non-removable; 979 mmc-pwrseq = <&sdio_pwrseq>; 980 sd-uhs-sdr104; 981 status = "okay"; 982}; 983 984&tsadc { 985 pinctrl-names = "gpio", "otpout"; 986 pinctrl-0 = <&tsadc_otp_gpio>; 987 pinctrl-1 = <&tsadc_otp_out>; 988 status = "okay"; 989}; 990 991&uart1 { 992 pinctrl-names = "default"; 993 pinctrl-0 = <&uart1_xfer &uart1_cts>; 994 status = "okay"; 995}; 996 997&u2phy { 998 status = "okay"; 999 1000 u2phy_host: host-port { 1001 status = "okay"; 1002 phy-supply = <&vcc5v0_host>; 1003 }; 1004 1005 u2phy_otg: otg-port { 1006 status = "okay"; 1007 }; 1008}; 1009 1010&usb20_otg { 1011 status = "okay"; 1012}; 1013 1014&usb_host0_ehci { 1015 status = "okay"; 1016}; 1017 1018&usb_host0_ohci { 1019 status = "okay"; 1020}; 1021 1022&vopb { 1023 status = "okay"; 1024}; 1025 1026&vopb_mmu { 1027 status = "okay"; 1028}; 1029 1030&vopl { 1031 status = "okay"; 1032}; 1033 1034&vopl_mmu { 1035 status = "okay"; 1036}; 1037 1038&mpp_srv { 1039 status = "okay"; 1040}; 1041 1042&vdpu { 1043 status = "okay"; 1044}; 1045 1046&vepu { 1047 status = "okay"; 1048}; 1049 1050&vpu_mmu { 1051 status = "okay"; 1052}; 1053 1054&hevc { 1055 status = "okay"; 1056}; 1057 1058&hevc_mmu { 1059 status = "okay"; 1060}; 1061 1062&pinctrl { 1063 lcd { 1064 lcd0_pwren: lcd0-pwren { 1065 rockchip,pins = <1 RK_PD6 RK_FUNC_GPIO &pcfg_output_high>; 1066 }; 1067 lcd0_rst: lcd0-rst { 1068 rockchip,pins = <1 RK_PD7 RK_FUNC_GPIO &pcfg_output_high>; 1069 }; 1070 mipi_en: mipi-en { 1071 rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>; 1072 }; 1073 pwdn_rgb: pwdn-rgb { 1074 rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_output_high>; 1075 }; 1076 }; 1077 1078 pmic { 1079 pmic_int: pmic_int { 1080 rockchip,pins = 1081 <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; 1082 }; 1083 1084 soc_slppin_gpio: soc_slppin_gpio { 1085 rockchip,pins = 1086 <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; 1087 }; 1088 1089 soc_slppin_slp: soc_slppin_slp { 1090 rockchip,pins = 1091 <0 RK_PA4 1 &pcfg_pull_none>; 1092 }; 1093 1094 soc_slppin_rst: soc_slppin_rst { 1095 rockchip,pins = 1096 <0 RK_PA4 2 &pcfg_pull_none>; 1097 }; 1098 }; 1099 1100 sdio-pwrseq { 1101 wifi_enable_h: wifi-enable-h { 1102 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 1103 }; 1104 }; 1105}; 1106