1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7#include "px30.dtsi" 8 9&cpu0_opp_table { 10 /delete-node/ opp-408000000; 11 /delete-node/ opp-600000000; 12 /delete-node/ opp-816000000; 13 /delete-node/ opp-1008000000; 14 /delete-node/ opp-1200000000; 15 /delete-node/ opp-1248000000; 16 /delete-node/ opp-1296000000; 17 /delete-node/ opp-1416000000; 18 /delete-node/ opp-1512000000; 19 20 opp-1008000000 { 21 opp-hz = /bits/ 64 <1008000000>; 22 opp-microvolt = <1125000 1125000 1125000>; 23 clock-latency-ns = <40000>; 24 }; 25}; 26 27&cru { 28 assigned-clocks = <&cru PLL_NPLL>; 29 assigned-clock-rates = <1040000000>; 30}; 31 32&display_subsystem { 33 status = "disabled"; 34 ports = <&vopb_out>, <&vopl_out>; 35 logo-memory-region = <&drm_logo>; 36 37 route { 38 route_lvds: route-lvds { 39 status = "disabled"; 40 logo,uboot = "logo.bmp"; 41 logo,kernel = "logo_kernel.bmp"; 42 logo,mode = "center"; 43 charge_logo,mode = "center"; 44 connect = <&vopb_out_lvds>; 45 }; 46 47 route_dsi: route-dsi { 48 status = "disabled"; 49 logo,uboot = "logo.bmp"; 50 logo,kernel = "logo_kernel.bmp"; 51 logo,mode = "center"; 52 charge_logo,mode = "center"; 53 connect = <&vopb_out_dsi>; 54 }; 55 56 route_rgb: route-rgb { 57 status = "disabled"; 58 logo,uboot = "logo.bmp"; 59 logo,kernel = "logo_kernel.bmp"; 60 logo,mode = "center"; 61 charge_logo,mode = "center"; 62 connect = <&vopb_out_rgb>; 63 }; 64 }; 65}; 66 67&dmc_opp_table { 68 /delete-node/ opp-194000000; 69 /delete-node/ opp-328000000; 70 /delete-node/ opp-450000000; 71 /delete-node/ opp-528000000; 72 /delete-node/ opp-666000000; 73 74 opp-666000000 { 75 opp-hz = /bits/ 64 <666000000>; 76 opp-microvolt = <1050000>; 77 }; 78}; 79 80&gpu_opp_table { 81 /delete-node/ opp-200000000; 82 /delete-node/ opp-300000000; 83 /delete-node/ opp-400000000; 84 /delete-node/ opp-480000000; 85 86 opp-520000000 { 87 opp-hz = /bits/ 64 <520000000>; 88 opp-microvolt = <1125000>; 89 }; 90}; 91 92&rgb { 93 phys = <&video_phy>; 94 phy-names = "phy"; 95 pinctrl-names = "default", "sleep"; 96 pinctrl-0 = <&lcdc_m1_rgb_pins>; 97 pinctrl-1 = <&lcdc_m1_sleep_pins>; 98}; 99 100&pinctrl { 101 lcdc { 102 lcdc_m1_rgb_pins: lcdc-m1-rgb-pins { 103 rockchip,pins = 104 <3 RK_PA0 1 &pcfg_pull_none_8ma>, /* LCDC_DCLK */ 105 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* LCDC_D0 */ 106 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* LCDC_D2 */ 107 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* LCDC_D6 */ 108 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* LCDC_D7 */ 109 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* LCDC_D9 */ 110 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* LCDC_D12 */ 111 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* LCDC_D13 */ 112 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* LCDC_D14 */ 113 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* LCDC_D15 */ 114 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* LCDC_D16 */ 115 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* LCDC_D17 */ 116 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* LCDC_D18 */ 117 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* LCDC_D19 */ 118 <3 RK_PD0 1 &pcfg_pull_none_8ma>, /* LCDC_D20 */ 119 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* LCDC_D21 */ 120 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* LCDC_D22 */ 121 <3 RK_PD3 1 &pcfg_pull_none_8ma>; /* LCDC_D23 */ 122 }; 123 124 lcdc_m1_sleep_pins: lcdc-m1-sleep-pins { 125 rockchip,pins = 126 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */ 127 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D0 */ 128 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D2 */ 129 <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D6 */ 130 <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D7 */ 131 <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D9 */ 132 <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */ 133 <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */ 134 <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */ 135 <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */ 136 <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */ 137 <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */ 138 <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */ 139 <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */ 140 <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */ 141 <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */ 142 <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */ 143 <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_D23 */ 144 }; 145 }; 146}; 147
