1 /* 2 * rk3308_codec.h -- RK3308 ALSA Soc Audio Driver 3 * 4 * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 */ 19 20 #ifndef __RK3308_CODEC_H__ 21 #define __RK3308_CODEC_H__ 22 23 #define ACODEC_RESET_CTL 0x00 /* REG 0x00 */ 24 25 /* ADC DIGITAL REGISTERS */ 26 #define ACODEC_ADC_I2S_CTL0 0x04 /* REG 0x01 */ 27 #define ACODEC_ADC_I2S_CTL1 0x08 /* REG 0x02 */ 28 #define ACODEC_ADC_BIST_MODE_SEL 0x0c /* REG 0x03 */ 29 #define ACODEC_ADC_HPF_PATH 0x10 /* REG 0x04 */ 30 #define ACODEC_S_ADC_DIG_VOL_CON_L 0x14 /* REG 0x05 */ 31 #define ACODEC_S_ADC_DIG_VOL_CON_R 0x18 /* REG 0x06 */ 32 #define ACODEC_ADC_DATA_PATH 0x1c /* REG 0x07 */ 33 /* Resevred REG 0x08 ~ 0x0f */ 34 35 /* REG 0x10 ~ 0x1c are used to configure AGC of Left channel (ALC1) */ 36 #define ACODEC_ADC_PGA_AGC_L_CTL0 0x40 /* REG 0x10 */ 37 #define ACODEC_ADC_PGA_AGC_L_CTL1 0x44 /* REG 0x11 */ 38 #define ACODEC_ADC_PGA_AGC_L_CTL2 0x48 /* REG 0x12 */ 39 #define ACODEC_ADC_PGA_AGC_L_CTL3 0x4c /* REG 0x13 */ 40 #define ACODEC_ADC_PGA_AGC_L_CTL4 0x50 /* REG 0x14 */ 41 #define ACODEC_ADC_PGA_AGC_L_LO_MAX 0x54 /* REG 0x15 */ 42 #define ACODEC_ADC_PGA_AGC_L_HI_MAX 0x58 /* REG 0x16 */ 43 #define ACODEC_ADC_PGA_AGC_L_LO_MIN 0x5c /* REG 0x17 */ 44 #define ACODEC_ADC_PGA_AGC_L_HI_MIN 0x60 /* REG 0x18 */ 45 #define ACODEC_ADC_PGA_AGC_L_CTL5 0x64 /* REG 0x19 */ 46 /* Resevred REG 0x1a */ 47 #define ACODEC_S_ADC_PEAK_DET_VALUE_DEC_RATE_L 0x6c /* REG 0x1b */ 48 #define ACODEC_ADC_AGC_L_RO_GAIN 0x70 /* REG 0x1c */ 49 50 /* REG 0x20 ~ 0x2c are used to configure AGC of Right channel (ALC2) */ 51 #define ACODEC_ADC_PGA_AGC_R_CTL0 0x80 /* REG 0x20 */ 52 #define ACODEC_ADC_PGA_AGC_R_CTL1 0x84 /* REG 0x21 */ 53 #define ACODEC_ADC_PGA_AGC_R_CTL2 0x88 /* REG 0x22 */ 54 #define ACODEC_ADC_PGA_AGC_R_CTL3 0x8c /* REG 0x23 */ 55 #define ACODEC_ADC_PGA_AGC_R_CTL4 0x90 /* REG 0x24 */ 56 #define ACODEC_ADC_PGA_AGC_R_LO_MAX 0x94 /* REG 0x25 */ 57 #define ACODEC_ADC_PGA_AGC_R_HI_MAX 0x98 /* REG 0x26 */ 58 #define ACODEC_ADC_PGA_AGC_R_LO_MIN 0x9c /* REG 0x27 */ 59 #define ACODEC_ADC_PGA_AGC_R_HI_MIN 0xa0 /* REG 0x28 */ 60 #define ACODEC_ADC_PGA_AGC_R_CTL5 0xa4 /* REG 0x29 */ 61 /* Resevred REG 0x2a */ 62 #define ACODEC_S_ADC_PEAK_DET_VALUE_DEC_RATE_R 0xac /* REG 0x2b */ 63 #define ACODEC_ADC_AGC_R_RO_GAIN 0xb0 /* REG 0x2c */ 64 65 /* DAC DIGITAL REGISTERS */ 66 #define ACODEC_DAC_I2S_CTL0 0x04 /* REG 0x01 */ 67 #define ACODEC_DAC_I2S_CTL1 0x08 /* REG 0x02 */ 68 #define ACODEC_DAC_BIST_MODE_SEL 0x0c /* REG 0x03 */ 69 #define ACODEC_DAC_DIGITAL_GAIN 0x10 /* REG 0x04 */ 70 #define ACODEC_DAC_DATA_SEL 0x14 /* REG 0x05 */ 71 /* Resevred REG 0x06 ~ 0x08 */ 72 #define ACODEC_DAC_DATA_HI 0x28 /* REG 0x0a */ 73 #define ACODEC_DAC_DATA_LO 0x2c /* REG 0x0b */ 74 75 #define ACODEC_DAC_HPDET_DELAYTIME_HI 0x30 /* REG 0x0c */ 76 #define ACODEC_DAC_HPDET_DELAYTIME_LO 0x34 /* REG 0x0d */ 77 #define ACODEC_DAC_HPDET_STATUS 0x38 /* REG 0x0e, Read-only */ 78 79 #define ACODEC_S_DAC_DATA_HI 0x24 /* REG 0x09 */ 80 #define ACODEC_S_DAC_DATA_LO 0x28 /* REG 0x0a */ 81 #define ACODEC_S_DAC_HPDET_DELAYTIME_HI 0x2c /* REG 0x0b */ 82 #define ACODEC_S_DAC_HPDET_DELAYTIME_LO 0x30 /* REG 0x0c */ 83 #define ACODEC_S_DAC_HPDET_STATUS 0x34 /* REG 0x0d, Read-only */ 84 85 /* Resevred REG 0x0f */ 86 87 /* ADC ANALOG REGISTERS */ 88 #define ACODEC_ADC_ANA_MIC_CTL 0x00 /* REG 0x00 */ 89 #define ACODEC_ADC_ANA_MIC_GAIN 0x04 /* REG 0x01 */ 90 #define ACODEC_ADC_ANA_ALC_CTL 0x08 /* REG 0x02 */ 91 #define ACODEC_ADC_ANA_ALC_GAIN1 0x0c /* REG 0x03 */ 92 #define ACODEC_ADC_ANA_ALC_GAIN2 0x10 /* REG 0x04 */ 93 #define ACODEC_ADC_ANA_CTL0 0x14 /* REG 0x05 */ 94 #define ACODEC_ADC_ANA_CTL1 0x18 /* REG 0x06 */ 95 #define ACODEC_ADC_ANA_CTL2 0x1c /* REG 0x07 */ 96 #define ACODEC_ADC_ANA_CTL3 0x20 /* REG 0x08 */ 97 #define ACODEC_S_ADC_ANA_CTL4 0x24 /* REG 0x09 */ 98 #define ACODEC_ADC_ANA_CTL5 0x28 /* REG 0x0a */ 99 #define ACODEC_ADC_ANA_ALC_PGA 0x2c /* REG 0x0b */ 100 /* Resevred REG 0x0c ~ 0x0f */ 101 102 /* DAC ANALOG REGISTERS */ 103 #define ACODEC_DAC_ANA_CTL0 0x00 /* REG 0x00 */ 104 #define ACODEC_DAC_ANA_POP_VOLT 0x04 /* REG 0x01 */ 105 #define ACODEC_DAC_ANA_CTL1 0x08 /* REG 0x02 */ 106 #define ACODEC_DAC_ANA_HPOUT 0x0c /* REG 0x03 */ 107 #define ACODEC_DAC_ANA_LINEOUT 0x10 /* REG 0x04 */ 108 #define ACODEC_DAC_ANA_L_HPOUT_GAIN 0x14 /* REG 0x05 */ 109 #define ACODEC_DAC_ANA_R_HPOUT_GAIN 0x18 /* REG 0x06 */ 110 #define ACODEC_DAC_ANA_DRV_HPOUT 0x1c /* REG 0x07 */ 111 #define ACODEC_DAC_ANA_DRV_LINEOUT 0x20 /* REG 0x08 */ 112 /* Resevred REG 0x07 ~ 0x0b */ 113 #define ACODEC_DAC_ANA_HPMIX_CTL0 0x30 /* REG 0x0c */ 114 #define ACODEC_DAC_ANA_HPMIX_CTL1 0x34 /* REG 0x0d */ 115 #define ACODEC_DAC_ANA_LINEOUT_CTL0 0x38 /* REG 0x0e */ 116 #define ACODEC_DAC_ANA_LINEOUT_CTL1 0x3c /* REG 0x0f */ 117 118 /* 119 * These registers are referenced by codec driver 120 */ 121 122 #define RK3308_GLB_CON ACODEC_RESET_CTL 123 124 /* ADC DIGITAL REGISTERS */ 125 126 /* 127 * The ADC group are 0 ~ 3, that control: 128 * 129 * CH0: left_0(ADC1) and right_0(ADC2) 130 * CH1: left_1(ADC3) and right_1(ADC4) 131 * CH2: left_2(ADC5) and right_2(ADC6) 132 * CH3: left_3(ADC7) and right_3(ADC8) 133 */ 134 #define RK3308_ADC_DIG_OFFSET(ch) ((ch & 0x3) * 0xc0 + 0x0) 135 136 #define RK3308_ADC_DIG_CON01(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_I2S_CTL0) 137 #define RK3308_ADC_DIG_CON02(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_I2S_CTL1) 138 #define RK3308_ADC_DIG_CON03(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_BIST_MODE_SEL) 139 #define RK3308_ADC_DIG_CON04(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_HPF_PATH) 140 #define RK3308BS_ADC_DIG_CON05(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_S_ADC_DIG_VOL_CON_L) 141 #define RK3308BS_ADC_DIG_CON06(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_S_ADC_DIG_VOL_CON_R) 142 #define RK3308_ADC_DIG_CON07(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_DATA_PATH) /* Removed from S */ 143 144 #define RK3308_ALC_L_DIG_CON00(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL0) 145 #define RK3308_ALC_L_DIG_CON01(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL1) 146 #define RK3308_ALC_L_DIG_CON02(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL2) 147 #define RK3308_ALC_L_DIG_CON03(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL3) 148 #define RK3308_ALC_L_DIG_CON04(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL4) 149 #define RK3308_ALC_L_DIG_CON05(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_LO_MAX) 150 #define RK3308_ALC_L_DIG_CON06(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_HI_MAX) 151 #define RK3308_ALC_L_DIG_CON07(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_LO_MIN) 152 #define RK3308_ALC_L_DIG_CON08(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_HI_MIN) 153 #define RK3308_ALC_L_DIG_CON09(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL5) 154 #define RK3308BS_ALC_L_DIG_CON11(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_S_ADC_PEAK_DET_VALUE_DEC_RATE_L) 155 #define RK3308_ALC_L_DIG_CON12(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_AGC_L_RO_GAIN) 156 157 #define RK3308_ALC_R_DIG_CON00(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL0) 158 #define RK3308_ALC_R_DIG_CON01(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL1) 159 #define RK3308_ALC_R_DIG_CON02(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL2) 160 #define RK3308_ALC_R_DIG_CON03(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL3) 161 #define RK3308_ALC_R_DIG_CON04(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL4) 162 #define RK3308_ALC_R_DIG_CON05(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_LO_MAX) 163 #define RK3308_ALC_R_DIG_CON06(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_HI_MAX) 164 #define RK3308_ALC_R_DIG_CON07(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_LO_MIN) 165 #define RK3308_ALC_R_DIG_CON08(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_HI_MIN) 166 #define RK3308_ALC_R_DIG_CON09(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL5) 167 #define RK3308BS_ALC_R_DIG_CON11(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_S_ADC_PEAK_DET_VALUE_DEC_RATE_R) 168 #define RK3308_ALC_R_DIG_CON12(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_AGC_R_RO_GAIN) 169 170 /* DAC DIGITAL REGISTERS */ 171 #define RK3308_DAC_DIG_OFFSET 0x300 172 173 #define RK3308_DAC_DIG_CON01 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_I2S_CTL0) 174 #define RK3308_DAC_DIG_CON02 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_I2S_CTL1) 175 #define RK3308_DAC_DIG_CON03 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_BIST_MODE_SEL) 176 #define RK3308_DAC_DIG_CON04 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DIGITAL_GAIN) 177 #define RK3308BS_DAC_DIG_CON04 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DIGITAL_GAIN) 178 #define RK3308_DAC_DIG_CON05 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DATA_SEL) 179 #define RK3308BS_DAC_DIG_CON05 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DATA_SEL) 180 181 #define RK3308_DAC_DIG_CON10 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DATA_HI) 182 #define RK3308_DAC_DIG_CON11 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DATA_LO) 183 184 #define RK3308_DAC_DIG_CON12 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_HPDET_DELAYTIME_HI) 185 #define RK3308_DAC_DIG_CON13 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_HPDET_DELAYTIME_LO) 186 #define RK3308_DAC_DIG_CON14 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_HPDET_STATUS) 187 188 #define RK3308BS_DAC_DIG_CON09 (RK3308_DAC_DIG_OFFSET + ACODEC_S_DAC_DATA_HI) 189 #define RK3308BS_DAC_DIG_CON10 (RK3308_DAC_DIG_OFFSET + ACODEC_S_DAC_DATA_LO) 190 #define RK3308BS_DAC_DIG_CON11 (RK3308_DAC_DIG_OFFSET + ACODEC_S_DAC_DELAY_TIME_DET_HI) 191 #define RK3308BS_DAC_DIG_CON12 (RK3308_DAC_DIG_OFFSET + ACODEC_S_DAC_DELAY_TIME_DET_LO) 192 #define RK3308BS_DAC_DIG_CON13 (RK3308_DAC_DIG_OFFSET + ACODEC_S_DAC_HPDET_STATUS) 193 194 #define RK3308_CODEC_HEADPHONE_CON RK3308_DAC_DIG_CON14 195 #define RK3308BS_CODEC_HEADPHONE_CON RK3308BS_DAC_DIG_CON13 196 197 /* ADC ANALOG REGISTERS */ 198 /* 199 * The ADC group are 0 ~ 3, that control: 200 * 201 * CH0: left_0(ADC1) and right_0(ADC2) 202 * CH1: left_1(ADC3) and right_1(ADC4) 203 * CH2: left_2(ADC5) and right_2(ADC6) 204 * CH3: left_3(ADC7) and right_3(ADC8) 205 */ 206 #define RK3308_ADC_ANA_OFFSET(ch) (((ch) & 0x3) * 0x40 + 0x340) 207 208 #define RK3308_ADC_ANA_CON00(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_MIC_CTL) 209 #define RK3308_ADC_ANA_CON01(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_MIC_GAIN) 210 #define RK3308_ADC_ANA_CON02(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_ALC_CTL) 211 #define RK3308_ADC_ANA_CON03(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_ALC_GAIN1) 212 #define RK3308_ADC_ANA_CON04(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_ALC_GAIN2) 213 #define RK3308_ADC_ANA_CON05(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL0) 214 #define RK3308_ADC_ANA_CON06(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL1) 215 #define RK3308_ADC_ANA_CON07(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL2) 216 #define RK3308_ADC_ANA_CON08(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL3) 217 #define RK3308BS_ADC_ANA_CON09(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_S_ADC_ANA_CTL4) 218 #define RK3308_ADC_ANA_CON10(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL5) 219 #define RK3308_ADC_ANA_CON11(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_ALC_PGA) 220 221 /* DAC ANALOG REGISTERS */ 222 #define RK3308_DAC_ANA_OFFSET 0x440 223 #define RK3308_DAC_ANA_CON00 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_CTL0) 224 #define RK3308_DAC_ANA_CON01 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_POP_VOLT) 225 #define RK3308_DAC_ANA_CON02 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_CTL1) 226 #define RK3308_DAC_ANA_CON03 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_HPOUT) 227 #define RK3308_DAC_ANA_CON04 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_LINEOUT) 228 #define RK3308_DAC_ANA_CON05 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_L_HPOUT_GAIN) 229 #define RK3308_DAC_ANA_CON06 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_R_HPOUT_GAIN) 230 #define RK3308_DAC_ANA_CON07 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_DRV_HPOUT) 231 #define RK3308_DAC_ANA_CON08 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_DRV_LINEOUT) 232 #define RK3308_DAC_ANA_CON12 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_HPMIX_CTL0) 233 #define RK3308_DAC_ANA_CON13 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_HPMIX_CTL1) 234 #define RK3308_DAC_ANA_CON14 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_LINEOUT_CTL0) 235 #define RK3308_DAC_ANA_CON15 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_LINEOUT_CTL1) 236 237 /* 238 * These are the bits for registers 239 */ 240 241 /* RK3308_GLB_CON - REG: 0x0000 */ 242 #define RK3308_ADC_BIST_WORK (1 << 7) 243 #define RK3308_ADC_BIST_RESET (0 << 7) 244 #define RK3308_DAC_BIST_WORK (1 << 6) 245 #define RK3308_DAC_BIST_RESET (0 << 6) 246 #define RK3308_ADC_MCLK_MSK (1 << 5) 247 #define RK3308_ADC_MCLK_DIS (1 << 5) 248 #define RK3308_ADC_MCLK_EN (0 << 5) 249 #define RK3308_DAC_MCLK_MSK (1 << 4) 250 #define RK3308_DAC_MCLK_DIS (1 << 4) 251 #define RK3308_DAC_MCLK_EN (0 << 4) 252 #define RK3308_CODEC_RST_MSK (0x7 << 0) 253 #define RK3308_ADC_DIG_WORK (1 << 2) 254 #define RK3308_ADC_DIG_RESET (0 << 2) 255 #define RK3308_DAC_DIG_WORK (1 << 1) 256 #define RK3308_DAC_DIG_RESET (0 << 1) 257 #define RK3308_SYS_WORK (1 << 0) 258 #define RK3308_SYS_RESET (0 << 0) 259 260 /* RK3308_ADC_DIG_CON01 - REG: 0x0004 */ 261 #define RK3308_ADC_I2S_LRC_POL_MSK (1 << 0) 262 #define RK3308_ADC_I2S_LRC_POL_REVERSAL (1 << 0) 263 #define RK3308_ADC_I2S_LRC_POL_NORMAL (0 << 0) 264 #define RK3308_ADC_I2S_VALID_LEN_SFT 5 265 #define RK3308_ADC_I2S_VALID_LEN_MSK (0x3 << RK3308_ADC_I2S_VALID_LEN_SFT) 266 #define RK3308_ADC_I2S_VALID_LEN_32BITS (0x3 << RK3308_ADC_I2S_VALID_LEN_SFT) 267 #define RK3308_ADC_I2S_VALID_LEN_24BITS (0x2 << RK3308_ADC_I2S_VALID_LEN_SFT) 268 #define RK3308_ADC_I2S_VALID_LEN_20BITS (0x1 << RK3308_ADC_I2S_VALID_LEN_SFT) 269 #define RK3308_ADC_I2S_VALID_LEN_16BITS (0x0 << RK3308_ADC_I2S_VALID_LEN_SFT) 270 #define RK3308_ADC_I2S_MODE_SFT 3 271 #define RK3308_ADC_I2S_MODE_MSK (0x3 << RK3308_ADC_I2S_MODE_SFT) 272 #define RK3308_ADC_I2S_MODE_PCM (0x3 << RK3308_ADC_I2S_MODE_SFT) 273 #define RK3308_ADC_I2S_MODE_I2S (0x2 << RK3308_ADC_I2S_MODE_SFT) 274 #define RK3308_ADC_I2S_MODE_LJ (0x1 << RK3308_ADC_I2S_MODE_SFT) 275 #define RK3308_ADC_I2S_MODE_RJ (0x0 << RK3308_ADC_I2S_MODE_SFT) 276 #define RK3308_ADC_I2S_LR_MSK (1 << 1) 277 #define RK3308_ADC_I2S_LR_SWAP (1 << 1) 278 #define RK3308_ADC_I2S_LR_NORMAL (0 << 1) 279 #define RK3308_ADC_I2S_TYPE_MSK (1 << 0) 280 #define RK3308_ADC_I2S_MONO (1 << 0) 281 #define RK3308_ADC_I2S_STEREO (0 << 0) 282 #define RK3308BS_ADC_I2S_SWAP_SFT 0 283 #define RK3308BS_ADC_I2S_LR (0 << RK3308BS_ADC_I2S_SWAP_SFT) 284 #define RK3308BS_ADC_I2S_LL (1 << RK3308BS_ADC_I2S_SWAP_SFT) 285 #define RK3308BS_ADC_I2S_RR (2 << RK3308BS_ADC_I2S_SWAP_SFT) 286 #define RK3308BS_ADC_I2S_RL (3 << RK3308BS_ADC_I2S_SWAP_SFT) 287 288 /* RK3308_ADC_DIG_CON02 - REG: 0x0008 */ 289 #define RK3308_ADC_IO_MODE_MSK (1 << 5) 290 #define RK3308_ADC_IO_MODE_MASTER (1 << 5) 291 #define RK3308_ADC_IO_MODE_SLAVE (0 << 5) 292 #define RK3308_ADC_MODE_MSK (1 << 4) 293 #define RK3308_ADC_MODE_MASTER (1 << 4) 294 #define RK3308_ADC_MODE_SLAVE (0 << 4) 295 #define RK3308_ADC_I2S_FRAME_LEN_SFT 2 296 #define RK3308_ADC_I2S_FRAME_LEN_MSK (0x3 << RK3308_ADC_I2S_FRAME_LEN_SFT) 297 #define RK3308_ADC_I2S_FRAME_32BITS (0x3 << RK3308_ADC_I2S_FRAME_LEN_SFT) 298 #define RK3308_ADC_I2S_FRAME_24BITS (0x2 << RK3308_ADC_I2S_FRAME_LEN_SFT) 299 #define RK3308_ADC_I2S_FRAME_20BITS (0x1 << RK3308_ADC_I2S_FRAME_LEN_SFT) 300 #define RK3308_ADC_I2S_FRAME_16BITS (0x0 << RK3308_ADC_I2S_FRAME_LEN_SFT) 301 #define RK3308_ADC_I2S_MSK (0x1 << 1) 302 #define RK3308_ADC_I2S_WORK (0x1 << 1) 303 #define RK3308_ADC_I2S_RESET (0x0 << 1) 304 #define RK3308_ADC_I2S_BIT_CLK_POL_MSK (0x1 << 0) 305 #define RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL (0x1 << 0) 306 #define RK3308_ADC_I2S_BIT_CLK_POL_NORMAL (0x0 << 0) 307 308 /* RK3308_ADC_DIG_CON03 - REG: 0x000c */ 309 #define RK3308_ADC_L_CH_BIST_SFT 2 310 #define RK3308_ADC_L_CH_BIST_MSK (0x3 << RK3308_ADC_L_CH_BIST_SFT) 311 #define RK3308_ADC_L_CH_NORMAL_RIGHT (0x3 << RK3308_ADC_L_CH_BIST_SFT) /* normal mode */ 312 #define RK3308_ADC_L_CH_BIST_CUBE (0x2 << RK3308_ADC_L_CH_BIST_SFT) 313 #define RK3308_ADC_L_CH_BIST_SINE (0x1 << RK3308_ADC_L_CH_BIST_SFT) 314 #define RK3308_ADC_L_CH_NORMAL_LEFT (0x0 << RK3308_ADC_L_CH_BIST_SFT) /* normal mode */ 315 #define RK3308_ADC_R_CH_BIST_SFT 0 316 #define RK3308_ADC_R_CH_BIST_MSK (0x3 << RK3308_ADC_R_CH_BIST_SFT) 317 #define RK3308_ADC_R_CH_NORMAL_LEFT (0x3 << RK3308_ADC_R_CH_BIST_SFT) /* normal mode */ 318 #define RK3308_ADC_R_CH_BIST_CUBE (0x2 << RK3308_ADC_R_CH_BIST_SFT) 319 #define RK3308_ADC_R_CH_BIST_SINE (0x1 << RK3308_ADC_R_CH_BIST_SFT) 320 #define RK3308_ADC_R_CH_NORMAL_RIGHT (0x0 << RK3308_ADC_R_CH_BIST_SFT) /* normal mode */ 321 322 /* RK3308_ADC_DIG_CON04 - REG: 0x0010 */ 323 #define RK3308_ADC_HPF_PATH_SFT 2 324 #define RK3308_ADC_HPF_PATH_MSK (1 << RK3308_ADC_HPF_PATH_SFT) 325 #define RK3308_ADC_HPF_PATH_DIS (1 << RK3308_ADC_HPF_PATH_SFT) 326 #define RK3308_ADC_HPF_PATH_EN (0 << RK3308_ADC_HPF_PATH_SFT) 327 #define RK3308_ADC_HPF_CUTOFF_SFT 0 328 #define RK3308_ADC_HPF_CUTOFF_MSK (0x3 << RK3308_ADC_HPF_CUTOFF_SFT) 329 #define RK3308_ADC_HPF_CUTOFF_612HZ (0x2 << RK3308_ADC_HPF_CUTOFF_SFT) 330 #define RK3308_ADC_HPF_CUTOFF_245HZ (0x1 << RK3308_ADC_HPF_CUTOFF_SFT) 331 #define RK3308_ADC_HPF_CUTOFF_20HZ (0x0 << RK3308_ADC_HPF_CUTOFF_SFT) 332 333 /* RK3308BS_ADC_DIG_CON05 - REG: 0x0014 */ 334 #define RK3308_ADC_DIG_VOL_CON_L_MSK 0xff 335 #define RK3308_ADC_DIG_VOL_CON_L(x) ((x) & RK3308_ADC_DIG_VOL_CON_L_MSK) 336 /* RK3308BS_ADC_DIG_CON06 - REG: 0x0018 */ 337 #define RK3308_ADC_DIG_VOL_CON_R_MSK 0xff 338 #define RK3308_ADC_DIG_VOL_CON_R(x) ((x) & RK3308_ADC_DIG_VOL_CON_R_MSK) 339 #define RK3308_ADC_DIG_VOL_0DB 0xc2 340 341 /* RK3308_ADC_DIG_CON07 - REG: 0x001c */ 342 #define RK3308_ADCL_DATA_SFT 4 343 #define RK3308_ADCL_DATA(x) ((x) << RK3308_ADCL_DATA_SFT) 344 #define RK3308_ADCR_DATA_SFT 2 345 #define RK3308_ADCR_DATA(x) ((x) << RK3308_ADCR_DATA_SFT) 346 #define RK3308_ADCL_DATA_SEL_ADCL (0x1 << 1) 347 #define RK3308_ADCL_DATA_SEL_NORMAL (0x0 << 1) 348 #define RK3308_ADCR_DATA_SEL_ADCR (0x1 << 0) 349 #define RK3308_ADCR_DATA_SEL_NORMAL (0x0 << 0) 350 351 /* 352 * RK3308_ALC_L_DIG_CON00 - REG: 0x0040 + ch * 0xc0 353 * RK3308_ALC_R_DIG_CON00 - REG: 0x0080 + ch * 0xc0 354 */ 355 #define RK3308_GAIN_ATTACK_JACK (0x1 << 6) 356 #define RK3308_GAIN_ATTACK_NORMAL (0x0 << 6) 357 #define RK3308_CTRL_GEN_SFT 4 358 #define RK3308_CTRL_GEN_MSK (0x3 << RK3308_ALC_CTRL_GEN_SFT) 359 #define RK3308_CTRL_GEN_JACK3 (0x3 << RK3308_ALC_CTRL_GEN_SFT) 360 #define RK3308_CTRL_GEN_JACK2 (0x2 << RK3308_ALC_CTRL_GEN_SFT) 361 #define RK3308_CTRL_GEN_JACK1 (0x1 << RK3308_ALC_CTRL_GEN_SFT) 362 #define RK3308_CTRL_GEN_NORMAL (0x0 << RK3308_ALC_CTRL_GEN_SFT) 363 #define RK3308_AGC_HOLD_TIME_SFT 0 364 #define RK3308_AGC_HOLD_TIME_MSK (0xf << RK3308_AGC_HOLD_TIME_SFT) 365 #define RK3308_AGC_HOLD_TIME_1S (0xa << RK3308_AGC_HOLD_TIME_SFT) 366 #define RK3308_AGC_HOLD_TIME_512MS (0x9 << RK3308_AGC_HOLD_TIME_SFT) 367 #define RK3308_AGC_HOLD_TIME_256MS (0x8 << RK3308_AGC_HOLD_TIME_SFT) 368 #define RK3308_AGC_HOLD_TIME_128MS (0x7 << RK3308_AGC_HOLD_TIME_SFT) 369 #define RK3308_AGC_HOLD_TIME_64MS (0x6 << RK3308_AGC_HOLD_TIME_SFT) 370 #define RK3308_AGC_HOLD_TIME_32MS (0x5 << RK3308_AGC_HOLD_TIME_SFT) 371 #define RK3308_AGC_HOLD_TIME_16MS (0x4 << RK3308_AGC_HOLD_TIME_SFT) 372 #define RK3308_AGC_HOLD_TIME_8MS (0x3 << RK3308_AGC_HOLD_TIME_SFT) 373 #define RK3308_AGC_HOLD_TIME_4MS (0x2 << RK3308_AGC_HOLD_TIME_SFT) 374 #define RK3308_AGC_HOLD_TIME_2MS (0x1 << RK3308_AGC_HOLD_TIME_SFT) 375 #define RK3308_AGC_HOLD_TIME_0MS (0x0 << RK3308_AGC_HOLD_TIME_SFT) 376 377 /* 378 * RK3308_ALC_L_DIG_CON01 - REG: 0x0044 + ch * 0xc0 379 * RK3308_ALC_R_DIG_CON01 - REG: 0x0084 + ch * 0xc0 380 */ 381 #define RK3308_AGC_DECAY_TIME_SFT 4 382 /* Normal mode (reg_agc_mode = 0) */ 383 #define RK3308_AGC_DECAY_NORMAL_MSK (0xf << RK3308_AGC_DECAY_TIME_SFT) 384 #define RK3308_AGC_DECAY_NORMAL_512MS (0xa << RK3308_AGC_DECAY_TIME_SFT) 385 #define RK3308_AGC_DECAY_NORMAL_256MS (0x9 << RK3308_AGC_DECAY_TIME_SFT) 386 #define RK3308_AGC_DECAY_NORMAL_128MS (0x8 << RK3308_AGC_DECAY_TIME_SFT) 387 #define RK3308_AGC_DECAY_NORMAL_64MS (0x7 << RK3308_AGC_DECAY_TIME_SFT) 388 #define RK3308_AGC_DECAY_NORMAL_32MS (0x6 << RK3308_AGC_DECAY_TIME_SFT) 389 #define RK3308_AGC_DECAY_NORMAL_16MS (0x5 << RK3308_AGC_DECAY_TIME_SFT) 390 #define RK3308_AGC_DECAY_NORMAL_8MS (0x4 << RK3308_AGC_DECAY_TIME_SFT) 391 #define RK3308_AGC_DECAY_NORMAL_4MS (0x3 << RK3308_AGC_DECAY_TIME_SFT) 392 #define RK3308_AGC_DECAY_NORMAL_2MS (0x2 << RK3308_AGC_DECAY_TIME_SFT) 393 #define RK3308_AGC_DECAY_NORMAL_1MS (0x1 << RK3308_AGC_DECAY_TIME_SFT) 394 #define RK3308_AGC_DECAY_NORMAL_0MS (0x0 << RK3308_AGC_DECAY_TIME_SFT) 395 /* Limiter mode (reg_agc_mode = 1) */ 396 #define RK3308_AGC_DECAY_LIMITER_MSK (0xf << RK3308_AGC_DECAY_TIME_SFT) 397 #define RK3308_AGC_DECAY_LIMITER_128MS (0xa << RK3308_AGC_DECAY_TIME_SFT) 398 #define RK3308_AGC_DECAY_LIMITER_64MS (0x9 << RK3308_AGC_DECAY_TIME_SFT) 399 #define RK3308_AGC_DECAY_LIMITER_32MS (0x8 << RK3308_AGC_DECAY_TIME_SFT) 400 #define RK3308_AGC_DECAY_LIMITER_16MS (0x7 << RK3308_AGC_DECAY_TIME_SFT) 401 #define RK3308_AGC_DECAY_LIMITER_8MS (0x6 << RK3308_AGC_DECAY_TIME_SFT) 402 #define RK3308_AGC_DECAY_LIMITER_4MS (0x5 << RK3308_AGC_DECAY_TIME_SFT) 403 #define RK3308_AGC_DECAY_LIMITER_2MS (0x4 << RK3308_AGC_DECAY_TIME_SFT) 404 #define RK3308_AGC_DECAY_LIMITER_1MS (0x3 << RK3308_AGC_DECAY_TIME_SFT) 405 #define RK3308_AGC_DECAY_LIMITER_500US (0x2 << RK3308_AGC_DECAY_TIME_SFT) 406 #define RK3308_AGC_DECAY_LIMITER_250US (0x1 << RK3308_AGC_DECAY_TIME_SFT) 407 #define RK3308_AGC_DECAY_LIMITER_125US (0x0 << RK3308_AGC_DECAY_TIME_SFT) 408 409 #define RK3308_AGC_ATTACK_TIME_SFT 0 410 /* Normal mode (reg_agc_mode = 0) */ 411 #define RK3308_AGC_ATTACK_NORMAL_MSK (0xf << RK3308_AGC_ATTACK_TIME_SFT) 412 #define RK3308_AGC_ATTACK_NORMAL_128MS (0xa << RK3308_AGC_ATTACK_TIME_SFT) 413 #define RK3308_AGC_ATTACK_NORMAL_64MS (0x9 << RK3308_AGC_ATTACK_TIME_SFT) 414 #define RK3308_AGC_ATTACK_NORMAL_32MS (0x8 << RK3308_AGC_ATTACK_TIME_SFT) 415 #define RK3308_AGC_ATTACK_NORMAL_16MS (0x7 << RK3308_AGC_ATTACK_TIME_SFT) 416 #define RK3308_AGC_ATTACK_NORMAL_8MS (0x6 << RK3308_AGC_ATTACK_TIME_SFT) 417 #define RK3308_AGC_ATTACK_NORMAL_4MS (0x5 << RK3308_AGC_ATTACK_TIME_SFT) 418 #define RK3308_AGC_ATTACK_NORMAL_2MS (0x4 << RK3308_AGC_ATTACK_TIME_SFT) 419 #define RK3308_AGC_ATTACK_NORMAL_1MS (0x3 << RK3308_AGC_ATTACK_TIME_SFT) 420 #define RK3308_AGC_ATTACK_NORMAL_500US (0x2 << RK3308_AGC_ATTACK_TIME_SFT) 421 #define RK3308_AGC_ATTACK_NORMAL_250US (0x1 << RK3308_AGC_ATTACK_TIME_SFT) 422 #define RK3308_AGC_ATTACK_NORMAL_125US (0x0 << RK3308_AGC_ATTACK_TIME_SFT) 423 /* Limiter mode (reg_agc_mode = 1) */ 424 #define RK3308_AGC_ATTACK_LIMITER_MSK (0xf << RK3308_AGC_ATTACK_TIME_SFT) 425 #define RK3308_AGC_ATTACK_LIMITER_32MS (0xa << RK3308_AGC_ATTACK_TIME_SFT) 426 #define RK3308_AGC_ATTACK_LIMITER_16MS (0x9 << RK3308_AGC_ATTACK_TIME_SFT) 427 #define RK3308_AGC_ATTACK_LIMITER_8MS (0x8 << RK3308_AGC_ATTACK_TIME_SFT) 428 #define RK3308_AGC_ATTACK_LIMITER_4MS (0x7 << RK3308_AGC_ATTACK_TIME_SFT) 429 #define RK3308_AGC_ATTACK_LIMITER_2MS (0x6 << RK3308_AGC_ATTACK_TIME_SFT) 430 #define RK3308_AGC_ATTACK_LIMITER_1MS (0x5 << RK3308_AGC_ATTACK_TIME_SFT) 431 #define RK3308_AGC_ATTACK_LIMITER_500US (0x4 << RK3308_AGC_ATTACK_TIME_SFT) 432 #define RK3308_AGC_ATTACK_LIMITER_250US (0x3 << RK3308_AGC_ATTACK_TIME_SFT) 433 #define RK3308_AGC_ATTACK_LIMITER_125US (0x2 << RK3308_AGC_ATTACK_TIME_SFT) 434 #define RK3308_AGC_ATTACK_LIMITER_64US (0x1 << RK3308_AGC_ATTACK_TIME_SFT) 435 #define RK3308_AGC_ATTACK_LIMITER_32US (0x0 << RK3308_AGC_ATTACK_TIME_SFT) 436 437 /* 438 * RK3308_ALC_L_DIG_CON02 - REG: 0x0048 + ch * 0xc0 439 * RK3308_ALC_R_DIG_CON02 - REG: 0x0088 + ch * 0xc0 440 */ 441 #define RK3308_AGC_MODE_LIMITER (0x1 << 7) 442 #define RK3308_AGC_MODE_NORMAL (0x0 << 7) 443 #define RK3308_AGC_ZERO_CRO_EN (0x1 << 6) 444 #define RK3308_AGC_ZERO_CRO_DIS (0x0 << 6) 445 #define RK3308_AGC_AMP_RECOVER_GAIN (0x1 << 5) 446 #define RK3308_AGC_AMP_RECOVER_LVOL (0x0 << 5) 447 #define RK3308_AGC_FAST_DEC_EN (0x1 << 4) 448 #define RK3308_AGC_FAST_DEC_DIS (0x0 << 4) 449 #define RK3308_AGC_NOISE_GATE_EN (0x1 << 3) 450 #define RK3308_AGC_NOISE_GATE_DIS (0x0 << 3) 451 #define RK3308_AGC_NOISE_GATE_THRESH_SFT 0 452 #define RK3308_AGC_NOISE_GATE_THRESH_MSK (0x7 << RK3308_AGC_NOISE_GATE_THRESH_SFT) 453 #define RK3308_AGC_NOISE_GATE_THRESH_N81DB (0x7 << RK3308_AGC_NOISE_GATE_THRESH_SFT) 454 #define RK3308_AGC_NOISE_GATE_THRESH_N75DB (0x6 << RK3308_AGC_NOISE_GATE_THRESH_SFT) 455 #define RK3308_AGC_NOISE_GATE_THRESH_N69DB (0x5 << RK3308_AGC_NOISE_GATE_THRESH_SFT) 456 #define RK3308_AGC_NOISE_GATE_THRESH_N63DB (0x4 << RK3308_AGC_NOISE_GATE_THRESH_SFT) 457 #define RK3308_AGC_NOISE_GATE_THRESH_N57DB (0x3 << RK3308_AGC_NOISE_GATE_THRESH_SFT) 458 #define RK3308_AGC_NOISE_GATE_THRESH_N51DB (0x2 << RK3308_AGC_NOISE_GATE_THRESH_SFT) 459 #define RK3308_AGC_NOISE_GATE_THRESH_N45DB (0x1 << RK3308_AGC_NOISE_GATE_THRESH_SFT) 460 #define RK3308_AGC_NOISE_GATE_THRESH_N39DB (0x0 << RK3308_AGC_NOISE_GATE_THRESH_SFT) 461 462 /* 463 * RK3308_ALC_L_DIG_CON03 - REG: 0x004c + ch * 0xc0 464 * RK3308_ALC_R_DIG_CON03 - REG: 0x008c + ch * 0xc0 465 */ 466 #define RK3308_AGC_PGA_ZERO_CRO_EN (0x1 << 5) 467 #define RK3308_AGC_PGA_ZERO_CRO_DIS (0x0 << 5) 468 #define RK3308_AGC_PGA_GAIN_MAX 0x1f 469 #define RK3308_AGC_PGA_GAIN_MIN 0 470 #define RK3308_AGC_PGA_GAIN_SFT 0 471 #define RK3308_AGC_PGA_GAIN_MSK (0x1f << RK3308_AGC_PGA_GAIN_SFT) 472 #define RK3308_AGC_PGA_GAIN_PDB_28_5 (0x1f << RK3308_AGC_PGA_GAIN_SFT) 473 #define RK3308_AGC_PGA_GAIN_PDB_27 (0x1e << RK3308_AGC_PGA_GAIN_SFT) 474 #define RK3308_AGC_PGA_GAIN_PDB_25_5 (0x1d << RK3308_AGC_PGA_GAIN_SFT) 475 #define RK3308_AGC_PGA_GAIN_PDB_24 (0x1c << RK3308_AGC_PGA_GAIN_SFT) 476 #define RK3308_AGC_PGA_GAIN_PDB_22_5 (0x1b << RK3308_AGC_PGA_GAIN_SFT) 477 #define RK3308_AGC_PGA_GAIN_PDB_21 (0x1a << RK3308_AGC_PGA_GAIN_SFT) 478 #define RK3308_AGC_PGA_GAIN_PDB_19_5 (0x19 << RK3308_AGC_PGA_GAIN_SFT) 479 #define RK3308_AGC_PGA_GAIN_PDB_18 (0x18 << RK3308_AGC_PGA_GAIN_SFT) 480 #define RK3308_AGC_PGA_GAIN_PDB_16_5 (0x17 << RK3308_AGC_PGA_GAIN_SFT) 481 #define RK3308_AGC_PGA_GAIN_PDB_15 (0x16 << RK3308_AGC_PGA_GAIN_SFT) 482 #define RK3308_AGC_PGA_GAIN_PDB_13_5 (0x15 << RK3308_AGC_PGA_GAIN_SFT) 483 #define RK3308_AGC_PGA_GAIN_PDB_12 (0x14 << RK3308_AGC_PGA_GAIN_SFT) 484 #define RK3308_AGC_PGA_GAIN_PDB_10_5 (0x13 << RK3308_AGC_PGA_GAIN_SFT) 485 #define RK3308_AGC_PGA_GAIN_PDB_9 (0x12 << RK3308_AGC_PGA_GAIN_SFT) 486 #define RK3308_AGC_PGA_GAIN_PDB_7_5 (0x11 << RK3308_AGC_PGA_GAIN_SFT) 487 #define RK3308_AGC_PGA_GAIN_PDB_6 (0x10 << RK3308_AGC_PGA_GAIN_SFT) 488 #define RK3308_AGC_PGA_GAIN_PDB_4_5 (0x0f << RK3308_AGC_PGA_GAIN_SFT) 489 #define RK3308_AGC_PGA_GAIN_PDB_3 (0x0e << RK3308_AGC_PGA_GAIN_SFT) 490 #define RK3308_AGC_PGA_GAIN_PDB_1_5 (0x0d << RK3308_AGC_PGA_GAIN_SFT) 491 #define RK3308_AGC_PGA_GAIN_0DB (0x0c << RK3308_AGC_PGA_GAIN_SFT) 492 #define RK3308_AGC_PGA_GAIN_NDB_1_5 (0x0b << RK3308_AGC_PGA_GAIN_SFT) 493 #define RK3308_AGC_PGA_GAIN_NDB_3 (0x0a << RK3308_AGC_PGA_GAIN_SFT) 494 #define RK3308_AGC_PGA_GAIN_NDB_4_5 (0x09 << RK3308_AGC_PGA_GAIN_SFT) 495 #define RK3308_AGC_PGA_GAIN_NDB_6 (0x08 << RK3308_AGC_PGA_GAIN_SFT) 496 #define RK3308_AGC_PGA_GAIN_NDB_7_5 (0x07 << RK3308_AGC_PGA_GAIN_SFT) 497 #define RK3308_AGC_PGA_GAIN_NDB_9 (0x06 << RK3308_AGC_PGA_GAIN_SFT) 498 #define RK3308_AGC_PGA_GAIN_NDB_10_5 (0x05 << RK3308_AGC_PGA_GAIN_SFT) 499 #define RK3308_AGC_PGA_GAIN_NDB_12 (0x04 << RK3308_AGC_PGA_GAIN_SFT) 500 #define RK3308_AGC_PGA_GAIN_NDB_13_5 (0x03 << RK3308_AGC_PGA_GAIN_SFT) 501 #define RK3308_AGC_PGA_GAIN_NDB_15 (0x02 << RK3308_AGC_PGA_GAIN_SFT) 502 #define RK3308_AGC_PGA_GAIN_NDB_16_5 (0x01 << RK3308_AGC_PGA_GAIN_SFT) 503 #define RK3308_AGC_PGA_GAIN_NDB_18 (0x00 << RK3308_AGC_PGA_GAIN_SFT) 504 505 /* 506 * RK3308_ALC_L_DIG_CON04 - REG: 0x0050 + ch * 0xc0 507 * RK3308_ALC_R_DIG_CON04 - REG: 0x0090 + ch * 0xc0 508 */ 509 #define RK3308_AGC_SLOW_CLK_EN (0x1 << 3) 510 #define RK3308_AGC_SLOW_CLK_DIS (0x0 << 3) 511 #define RK3308_AGC_APPROX_RATE_SFT 0 512 #define RK3308_AGC_APPROX_RATE_MSK (0x7 << RK3308_AGC_APPROX_RATE_SFT) 513 #define RK3308_AGC_APPROX_RATE_8K (0x7 << RK3308_AGC_APPROX_RATE_SFT) 514 #define RK3308_AGC_APPROX_RATE_12K (0x6 << RK3308_AGC_APPROX_RATE_SFT) 515 #define RK3308_AGC_APPROX_RATE_16K (0x5 << RK3308_AGC_APPROX_RATE_SFT) 516 #define RK3308_AGC_APPROX_RATE_24K (0x4 << RK3308_AGC_APPROX_RATE_SFT) 517 #define RK3308_AGC_APPROX_RATE_32K (0x3 << RK3308_AGC_APPROX_RATE_SFT) 518 #define RK3308_AGC_APPROX_RATE_44_1K (0x2 << RK3308_AGC_APPROX_RATE_SFT) 519 #define RK3308_AGC_APPROX_RATE_48K (0x1 << RK3308_AGC_APPROX_RATE_SFT) 520 #define RK3308_AGC_APPROX_RATE_96K (0x0 << RK3308_AGC_APPROX_RATE_SFT) 521 522 /* 523 * RK3308_ALC_L_DIG_CON05 - REG: 0x0054 + ch * 0xc0 524 * RK3308_ALC_R_DIG_CON05 - REG: 0x0094 + ch * 0xc0 525 */ 526 #define RK3308_AGC_LO_8BITS_AGC_MAX_MSK 0xff 527 528 /* 529 * RK3308_ALC_L_DIG_CON06 - REG: 0x0058 + ch * 0xc0 530 * RK3308_ALC_R_DIG_CON06 - REG: 0x0098 + ch * 0xc0 531 */ 532 #define RK3308_AGC_HI_8BITS_AGC_MAX_MSK 0xff 533 534 /* 535 * RK3308_ALC_L_DIG_CON07 - REG: 0x005c + ch * 0xc0 536 * RK3308_ALC_R_DIG_CON07 - REG: 0x009c + ch * 0xc0 537 */ 538 #define RK3308_AGC_LO_8BITS_AGC_MIN_MSK 0xff 539 540 /* 541 * RK3308_ALC_L_DIG_CON08 - REG: 0x0060 + ch * 0xc0 542 * RK3308_ALC_R_DIG_CON08 - REG: 0x00a0 + ch * 0xc0 543 */ 544 #define RK3308_AGC_HI_8BITS_AGC_MIN_MSK 0xff 545 546 /* 547 * RK3308_ALC_L_DIG_CON09 - REG: 0x0064 + ch * 0xc0 548 * RK3308_ALC_R_DIG_CON09 - REG: 0x00a4 + ch * 0xc0 549 */ 550 #define RK3308_AGC_FUNC_SEL_MSK (0x1 << 6) 551 #define RK3308_AGC_FUNC_SEL_EN (0x1 << 6) 552 #define RK3308_AGC_FUNC_SEL_DIS (0x0 << 6) 553 #define RK3308_AGC_MAX_GAIN_PGA_MAX 0x7 554 #define RK3308_AGC_MAX_GAIN_PGA_MIN 0 555 #define RK3308_AGC_MAX_GAIN_PGA_SFT 3 556 #define RK3308_AGC_MAX_GAIN_PGA_MSK (0x7 << RK3308_AGC_MAX_GAIN_PGA_SFT) 557 #define RK3308_AGC_MAX_GAIN_PGA_PDB_28_5 (0x7 << RK3308_AGC_MAX_GAIN_PGA_SFT) 558 #define RK3308_AGC_MAX_GAIN_PGA_PDB_22_5 (0x6 << RK3308_AGC_MAX_GAIN_PGA_SFT) 559 #define RK3308_AGC_MAX_GAIN_PGA_PDB_16_5 (0x5 << RK3308_AGC_MAX_GAIN_PGA_SFT) 560 #define RK3308_AGC_MAX_GAIN_PGA_PDB_10_5 (0x4 << RK3308_AGC_MAX_GAIN_PGA_SFT) 561 #define RK3308_AGC_MAX_GAIN_PGA_PDB_4_5 (0x3 << RK3308_AGC_MAX_GAIN_PGA_SFT) 562 #define RK3308_AGC_MAX_GAIN_PGA_NDB_1_5 (0x2 << RK3308_AGC_MAX_GAIN_PGA_SFT) 563 #define RK3308_AGC_MAX_GAIN_PGA_NDB_7_5 (0x1 << RK3308_AGC_MAX_GAIN_PGA_SFT) 564 #define RK3308_AGC_MAX_GAIN_PGA_NDB_13_5 (0x0 << RK3308_AGC_MAX_GAIN_PGA_SFT) 565 #define RK3308_AGC_MIN_GAIN_PGA_MAX 0x7 566 #define RK3308_AGC_MIN_GAIN_PGA_MIN 0 567 #define RK3308_AGC_MIN_GAIN_PGA_SFT 0 568 #define RK3308_AGC_MIN_GAIN_PGA_MSK (0x7 << RK3308_AGC_MIN_GAIN_PGA_SFT) 569 #define RK3308_AGC_MIN_GAIN_PGA_PDB_24 (0x7 << RK3308_AGC_MIN_GAIN_PGA_SFT) 570 #define RK3308_AGC_MIN_GAIN_PGA_PDB_18 (0x6 << RK3308_AGC_MIN_GAIN_PGA_SFT) 571 #define RK3308_AGC_MIN_GAIN_PGA_PDB_12 (0x5 << RK3308_AGC_MIN_GAIN_PGA_SFT) 572 #define RK3308_AGC_MIN_GAIN_PGA_PDB_6 (0x4 << RK3308_AGC_MIN_GAIN_PGA_SFT) 573 #define RK3308_AGC_MIN_GAIN_PGA_0DB (0x3 << RK3308_AGC_MIN_GAIN_PGA_SFT) 574 #define RK3308_AGC_MIN_GAIN_PGA_NDB_6 (0x2 << RK3308_AGC_MIN_GAIN_PGA_SFT) 575 #define RK3308_AGC_MIN_GAIN_PGA_NDB_12 (0x1 << RK3308_AGC_MIN_GAIN_PGA_SFT) 576 #define RK3308_AGC_MIN_GAIN_PGA_NDB_18 (0x0 << RK3308_AGC_MIN_GAIN_PGA_SFT) 577 578 /* 579 * RK3308BS_ALC_L_DIG_CON11 - REG: 0x006c + ch * 0xc0 580 * RK3308BS_ALC_R_DIG_CON11 - REG: 0x00ac + ch * 0xc0 581 */ 582 #define ACODEC_S_ADC_PEAK_DET_VALUE_DEC_RATE(x) ((x) & 0x1f) 583 584 /* 585 * RK3308_ALC_L_DIG_CON12 - REG: 0x0070 + ch * 0xc0 586 * RK3308_ALC_R_DIG_CON12 - REG: 0x00b0 + ch * 0xc0 587 */ 588 #define RK3308_AGC_GAIN_MSK 0x1f 589 590 /* 591 * RK3308BS_ALC_L_DIG_CON12 - REG: 0x0070 + ch * 0xc0 592 * RK3308BS_ALC_R_DIG_CON12 - REG: 0x00b0 + ch * 0xc0 593 */ 594 595 /* 596 * RK3308BS_ALC_L_DIG_CON13 - REG: 0x0074 + ch * 0xc0 597 * RK3308BS_ALC_R_DIG_CON13 - REG: 0x00b4 + ch * 0xc0 598 */ 599 600 /* 601 * RK3308BS_ALC_L_DIG_CON14 - REG: 0x0078 + ch * 0xc0 602 * RK3308BS_ALC_R_DIG_CON14 - REG: 0x00b8 + ch * 0xc0 603 */ 604 #define RK3308BS_AGC_GAIN_MSK 0x1f 605 606 /* RK3308_DAC_DIG_CON01 - REG: 0x0304 */ 607 #define RK3308_DAC_I2S_LRC_POL_MSK (0x1 << 7) 608 #define RK3308_DAC_I2S_LRC_POL_REVERSAL (0x1 << 7) 609 #define RK3308_DAC_I2S_LRC_POL_NORMAL (0x0 << 7) 610 #define RK3308_DAC_I2S_VALID_LEN_SFT 5 611 #define RK3308_DAC_I2S_VALID_LEN_MSK (0x3 << RK3308_DAC_I2S_VALID_LEN_SFT) 612 #define RK3308_DAC_I2S_VALID_LEN_32BITS (0x3 << RK3308_DAC_I2S_VALID_LEN_SFT) 613 #define RK3308_DAC_I2S_VALID_LEN_24BITS (0x2 << RK3308_DAC_I2S_VALID_LEN_SFT) 614 #define RK3308_DAC_I2S_VALID_LEN_20BITS (0x1 << RK3308_DAC_I2S_VALID_LEN_SFT) 615 #define RK3308_DAC_I2S_VALID_LEN_16BITS (0x0 << RK3308_DAC_I2S_VALID_LEN_SFT) 616 #define RK3308_DAC_I2S_MODE_SFT 3 617 #define RK3308_DAC_I2S_MODE_MSK (0x3 << RK3308_DAC_I2S_MODE_SFT) 618 #define RK3308_DAC_I2S_MODE_PCM (0x3 << RK3308_DAC_I2S_MODE_SFT) 619 #define RK3308_DAC_I2S_MODE_I2S (0x2 << RK3308_DAC_I2S_MODE_SFT) 620 #define RK3308_DAC_I2S_MODE_LJ (0x1 << RK3308_DAC_I2S_MODE_SFT) 621 #define RK3308_DAC_I2S_MODE_RJ (0x0 << RK3308_DAC_I2S_MODE_SFT) 622 #define RK3308_DAC_I2S_LR_MSK (0x1 << 2) 623 #define RK3308_DAC_I2S_LR_SWAP (0x1 << 2) 624 #define RK3308_DAC_I2S_LR_NORMAL (0x0 << 2) 625 #define RK3308BS_DAC_I2S_BYPASS_MSK (0x1 << 1) 626 #define RK3308BS_DAC_I2S_BYPASS_EN (0x1 << 1) 627 #define RK3308BS_DAC_I2S_BYPASS_DIS (0x0 << 1) 628 629 /* RK3308_DAC_DIG_CON02 - REG: 0x0308 */ 630 #define RK3308BS_DAC_IO_MODE_MSK (0x1 << 7) 631 #define RK3308BS_DAC_IO_MODE_MASTER (0x1 << 7) 632 #define RK3308BS_DAC_IO_MODE_SLAVE (0x0 << 7) 633 #define RK3308BS_DAC_MODE_MSK (0x1 << 6) 634 #define RK3308BS_DAC_MODE_MASTER (0x1 << 6) 635 #define RK3308BS_DAC_MODE_SLAVE (0x0 << 6) 636 #define RK3308_DAC_IO_MODE_MSK (0x1 << 5) 637 #define RK3308_DAC_IO_MODE_MASTER (0x1 << 5) 638 #define RK3308_DAC_IO_MODE_SLAVE (0x0 << 5) 639 #define RK3308_DAC_MODE_MSK (0x1 << 4) 640 #define RK3308_DAC_MODE_MASTER (0x1 << 4) 641 #define RK3308_DAC_MODE_SLAVE (0x0 << 4) 642 #define RK3308_DAC_I2S_FRAME_LEN_SFT 2 643 #define RK3308_DAC_I2S_FRAME_LEN_MSK (0x3 << RK3308_DAC_I2S_FRAME_LEN_SFT) 644 #define RK3308_DAC_I2S_FRAME_32BITS (0x3 << RK3308_DAC_I2S_FRAME_LEN_SFT) 645 #define RK3308_DAC_I2S_FRAME_24BITS (0x2 << RK3308_DAC_I2S_FRAME_LEN_SFT) 646 #define RK3308_DAC_I2S_FRAME_20BITS (0x1 << RK3308_DAC_I2S_FRAME_LEN_SFT) 647 #define RK3308_DAC_I2S_FRAME_16BITS (0x0 << RK3308_DAC_I2S_FRAME_LEN_SFT) 648 #define RK3308_DAC_I2S_MSK (0x1 << 1) 649 #define RK3308_DAC_I2S_WORK (0x1 << 1) 650 #define RK3308_DAC_I2S_RESET (0x0 << 1) 651 #define RK3308_DAC_I2S_BIT_CLK_POL_MSK (0x1 << 0) 652 #define RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL (0x1 << 0) 653 #define RK3308_DAC_I2S_BIT_CLK_POL_NORMAL (0x0 << 0) 654 655 /* RK3308_DAC_DIG_CON03 - REG: 0x030C */ 656 #define RK3308_DAC_L_CH_BIST_SFT 2 657 #define RK3308_DAC_L_CH_BIST_MSK (0x3 << RK3308_DAC_L_CH_BIST_SFT) 658 #define RK3308_DAC_L_CH_BIST_LEFT (0x3 << RK3308_DAC_L_CH_BIST_SFT) /* normal mode */ 659 #define RK3308_DAC_L_CH_BIST_CUBE (0x2 << RK3308_DAC_L_CH_BIST_SFT) 660 #define RK3308_DAC_L_CH_BIST_SINE (0x1 << RK3308_DAC_L_CH_BIST_SFT) 661 #define RK3308_DAC_L_CH_BIST_RIGHT (0x0 << RK3308_DAC_L_CH_BIST_SFT) /* normal mode */ 662 #define RK3308_DAC_R_CH_BIST_SFT 0 663 #define RK3308_DAC_R_CH_BIST_MSK (0x3 << RK3308_DAC_R_CH_BIST_SFT) 664 #define RK3308_DAC_R_CH_BIST_LEFT (0x3 << RK3308_DAC_R_CH_BIST_SFT) /* normal mode */ 665 #define RK3308_DAC_R_CH_BIST_CUBE (0x2 << RK3308_DAC_R_CH_BIST_SFT) 666 #define RK3308_DAC_R_CH_BIST_SINE (0x1 << RK3308_DAC_R_CH_BIST_SFT) 667 #define RK3308_DAC_R_CH_BIST_RIGHT (0x0 << RK3308_DAC_R_CH_BIST_SFT) /* normal mode */ 668 669 /* RK3308_DAC_DIG_CON04 - REG: 0x0310 */ 670 #define RK3308_DAC_MODULATOR_GAIN_SFT 4 671 #define RK3308_DAC_MODULATOR_GAIN_MSK (0x7 << RK3308_DAC_MODULATOR_GAIN_SFT) 672 #define RK3308_DAC_MODULATOR_GAIN_4_8DB (0x5 << RK3308_DAC_MODULATOR_GAIN_SFT) 673 #define RK3308_DAC_MODULATOR_GAIN_4_2DB (0x4 << RK3308_DAC_MODULATOR_GAIN_SFT) 674 #define RK3308_DAC_MODULATOR_GAIN_3_5DB (0x3 << RK3308_DAC_MODULATOR_GAIN_SFT) 675 #define RK3308_DAC_MODULATOR_GAIN_2_8DB (0x2 << RK3308_DAC_MODULATOR_GAIN_SFT) 676 #define RK3308_DAC_MODULATOR_GAIN_2DB (0x1 << RK3308_DAC_MODULATOR_GAIN_SFT) 677 #define RK3308_DAC_MODULATOR_GAIN_0DB (0x0 << RK3308_DAC_MODULATOR_GAIN_SFT) 678 #define RK3308_DAC_CIC_IF_GAIN_SFT 0 679 #define RK3308_DAC_CIC_IF_GAIN_MSK (0x7 << RK3308_DAC_CIC_IF_GAIN_SFT) 680 681 /* RK3308BS_DAC_DIG_CON04 - REG: 0x0310 */ 682 #define RK3308BS_DAC_DIG_GAIN_SFT 0 683 #define RK3308BS_DAC_DIG_GAIN_MSK (0xff << RK3308BS_DAC_DIG_GAIN_SFT) 684 #define RK3308BS_DAC_DIG_GAIN(x) ((x) & RK3308BS_DAC_DIG_GAIN_MSK) 685 #define RK3308BS_DAC_DIG_0DB 0xed 686 687 /* RK3308_DAC_DIG_CON05 - REG: 0x0314 */ 688 #define RK3308_DAC_L_DATA_SEL_INPUT (0x1 << 2) 689 #define RK3308_DAC_L_DATA_SEL_NORMAL (0x0 << 2) 690 #define RK3308_DAC_R_DATA_SEL_INPUT (0x1 << 1) 691 #define RK3308_DAC_R_DATA_SEL_NORMAL (0x0 << 1) 692 693 /* RK3308BS_DAC_DIG_CON05 - REG: 0x0314 */ 694 #define RK3308BS_DAC_L_DATA_SEL_MUTE (0x1 << 2) 695 #define RK3308BS_DAC_L_DATA_SEL_NORMAL (0x0 << 2) 696 #define RK3308BS_DAC_R_DATA_SEL_MUTE (0x1 << 1) 697 #define RK3308BS_DAC_R_DATA_SEL_NORMAL (0x0 << 1) 698 699 /* RK3308_DAC_DIG_CON10 - REG: 0x0328 */ 700 #define RK3308_DAC_DATA_HI4(x) ((x) & 0xf) /* Need to RK3308_DAC_x_REG_CTL_INDATA */ 701 702 /* RK3308_DAC_DIG_CON11 - REG: 0x032c */ 703 #define RK3308_DAC_DATA_LO8(x) ((x) & 0xff) /* Need to RK3308_DAC_x_REG_CTL_INDATA */ 704 705 /* RK3308BS_DAC_DIG_CON09 - REG: 0x0324 */ 706 #define RK3308BS_DAC_DATA_HI4(x) ((x) & 0xf) /* Need to RK3308_DAC_x_REG_CTL_INDATA */ 707 708 /* RK3308BS_DAC_DIG_CON10 - REG: 0x0328 */ 709 #define RK3308BS_DAC_DATA_LO8(x) ((x) & 0xff) /* Need to RK3308_DAC_x_REG_CTL_INDATA */ 710 711 /* RK3308BS_DAC_DIG_CON11 - REG: 0x032c */ 712 #define RK3308BS_DAC_DELAY_TIME_DETECT_HI2(x) ((x) & 0x3) 713 714 /* RK3308BS_DAC_DIG_CON12 - REG: 0x0330 */ 715 #define RK3308BS_DAC_DELAY_TIME_DETECT_LO8(x) ((x) & 0xff) 716 717 /* RK3308_ADC_ANA_CON00 - REG: 0x0340 */ 718 #define RK3308_ADC_CH1_CH2_MIC_ALL_MSK (0xff << 0) 719 #define RK3308_ADC_CH1_CH2_MIC_ALL 0xff 720 #define RK3308_ADC_CH2_MIC_UNMUTE (0x1 << 7) 721 #define RK3308_ADC_CH2_MIC_MUTE (0x0 << 7) 722 #define RK3308_ADC_CH2_MIC_WORK (0x1 << 6) 723 #define RK3308_ADC_CH2_MIC_INIT (0x0 << 6) 724 #define RK3308_ADC_CH2_MIC_EN (0x1 << 5) 725 #define RK3308_ADC_CH2_MIC_DIS (0x0 << 5) 726 #define RK3308_ADC_CH2_BUF_REF_EN (0x1 << 4) 727 #define RK3308_ADC_CH2_BUF_REF_DIS (0x0 << 4) 728 #define RK3308_ADC_CH1_MIC_UNMUTE (0x1 << 3) 729 #define RK3308_ADC_CH1_MIC_MUTE (0x0 << 3) 730 #define RK3308_ADC_CH1_MIC_WORK (0x1 << 2) 731 #define RK3308_ADC_CH1_MIC_INIT (0x0 << 2) 732 #define RK3308_ADC_CH1_MIC_EN (0x1 << 1) 733 #define RK3308_ADC_CH1_MIC_DIS (0x0 << 1) 734 #define RK3308_ADC_CH1_BUF_REF_EN (0x1 << 0) 735 #define RK3308_ADC_CH1_BUF_REF_DIS (0x0 << 0) 736 737 /* RK3308_ADC_ANA_CON01 - REG: 0x0344 738 * 739 * The PGA of MIC-INs: 740 * 0x0 - MIC1~MIC8 0dB 741 * 0x1 - MIC1~MIC8 6.6dB 742 * 0x2 - MIC1~MIC8 13dB 743 * 0x3 - MIC1~MIC8 20dB 744 */ 745 #define RK3308_ADC_CH2_MIC_GAIN_MAX 0x3 746 #define RK3308_ADC_CH2_MIC_GAIN_MIN 0 747 #define RK3308_ADC_CH2_MIC_GAIN_SFT 4 748 #define RK3308_ADC_CH2_MIC_GAIN_MSK (0x3 << RK3308_ADC_CH2_MIC_GAIN_SFT) 749 #define RK3308_ADC_CH2_MIC_GAIN_20DB (0x3 << RK3308_ADC_CH2_MIC_GAIN_SFT) 750 #define RK3308_ADC_CH2_MIC_GAIN_13DB (0x2 << RK3308_ADC_CH2_MIC_GAIN_SFT) /* TRM: only used for version B */ 751 #define RK3308_ADC_CH2_MIC_GAIN_6_6DB (0x1 << RK3308_ADC_CH2_MIC_GAIN_SFT) /* TRM: only used for version B */ 752 #define RK3308_ADC_CH2_MIC_GAIN_0DB (0x0 << RK3308_ADC_CH2_MIC_GAIN_SFT) 753 754 #define RK3308_ADC_CH1_MIC_GAIN_MAX 0x3 755 #define RK3308_ADC_CH1_MIC_GAIN_MIN 0 756 #define RK3308_ADC_CH1_MIC_GAIN_SFT 0 757 #define RK3308_ADC_CH1_MIC_GAIN_MSK (0x3 << RK3308_ADC_CH1_MIC_GAIN_SFT) 758 #define RK3308_ADC_CH1_MIC_GAIN_20DB (0x3 << RK3308_ADC_CH1_MIC_GAIN_SFT) 759 #define RK3308_ADC_CH1_MIC_GAIN_13DB (0x2 << RK3308_ADC_CH1_MIC_GAIN_SFT) /* TRM: only used for version B */ 760 #define RK3308_ADC_CH1_MIC_GAIN_6_6DB (0x1 << RK3308_ADC_CH1_MIC_GAIN_SFT) /* TRM: only used for version B */ 761 #define RK3308_ADC_CH1_MIC_GAIN_0DB (0x0 << RK3308_ADC_CH1_MIC_GAIN_SFT) 762 763 /* RK3308_ADC_ANA_CON02 - REG: 0x0348 */ 764 #define RK3308_ADC_CH2_ALC_ZC_MSK (0x7 << 4) 765 #define RK3308_ADC_CH2_ZEROCROSS_DET_EN (0x1 << 6) 766 #define RK3308_ADC_CH2_ZEROCROSS_DET_DIS (0x0 << 6) 767 #define RK3308_ADC_CH2_ALC_WORK (0x1 << 5) 768 #define RK3308_ADC_CH2_ALC_INIT (0x0 << 5) 769 #define RK3308_ADC_CH2_ALC_EN (0x1 << 4) 770 #define RK3308_ADC_CH2_ALC_DIS (0x0 << 4) 771 772 #define RK3308_ADC_CH1_ALC_ZC_MSK (0x7 << 0) 773 #define RK3308_ADC_CH1_ZEROCROSS_DET_EN (0x1 << 2) 774 #define RK3308_ADC_CH1_ZEROCROSS_DET_DIS (0x0 << 2) 775 #define RK3308_ADC_CH1_ALC_WORK (0x1 << 1) 776 #define RK3308_ADC_CH1_ALC_INIT (0x0 << 1) 777 #define RK3308_ADC_CH1_ALC_EN (0x1 << 0) 778 #define RK3308_ADC_CH1_ALC_DIS (0x0 << 0) 779 780 /* RK3308_ADC_ANA_CON03 - REG: 0x034c */ 781 #define RK3308_ADC_CH1_ALC_GAIN_MAX 0x1f 782 #define RK3308_ADC_CH1_ALC_GAIN_MIN 0 783 #define RK3308_ADC_CH1_ALC_GAIN_SFT 0 784 #define RK3308_ADC_CH1_ALC_GAIN_MSK (0x1f << RK3308_ADC_CH1_ALC_GAIN_SFT) 785 #define RK3308_ADC_CH1_ALC_GAIN_PDB_28_5 (0x1f << RK3308_ADC_CH1_ALC_GAIN_SFT) 786 #define RK3308_ADC_CH1_ALC_GAIN_PDB_27 (0x1e << RK3308_ADC_CH1_ALC_GAIN_SFT) 787 #define RK3308_ADC_CH1_ALC_GAIN_PDB_25_5 (0x1d << RK3308_ADC_CH1_ALC_GAIN_SFT) 788 #define RK3308_ADC_CH1_ALC_GAIN_PDB_24 (0x1c << RK3308_ADC_CH1_ALC_GAIN_SFT) 789 #define RK3308_ADC_CH1_ALC_GAIN_PDB_22_5 (0x1b << RK3308_ADC_CH1_ALC_GAIN_SFT) 790 #define RK3308_ADC_CH1_ALC_GAIN_PDB_21 (0x1a << RK3308_ADC_CH1_ALC_GAIN_SFT) 791 #define RK3308_ADC_CH1_ALC_GAIN_PDB_19_5 (0x19 << RK3308_ADC_CH1_ALC_GAIN_SFT) 792 #define RK3308_ADC_CH1_ALC_GAIN_PDB_18 (0x18 << RK3308_ADC_CH1_ALC_GAIN_SFT) 793 #define RK3308_ADC_CH1_ALC_GAIN_PDB_16_5 (0x17 << RK3308_ADC_CH1_ALC_GAIN_SFT) 794 #define RK3308_ADC_CH1_ALC_GAIN_PDB_15 (0x16 << RK3308_ADC_CH1_ALC_GAIN_SFT) 795 #define RK3308_ADC_CH1_ALC_GAIN_PDB_13_5 (0x15 << RK3308_ADC_CH1_ALC_GAIN_SFT) 796 #define RK3308_ADC_CH1_ALC_GAIN_PDB_12 (0x14 << RK3308_ADC_CH1_ALC_GAIN_SFT) 797 #define RK3308_ADC_CH1_ALC_GAIN_PDB_10_5 (0x13 << RK3308_ADC_CH1_ALC_GAIN_SFT) 798 #define RK3308_ADC_CH1_ALC_GAIN_PDB_9 (0x12 << RK3308_ADC_CH1_ALC_GAIN_SFT) 799 #define RK3308_ADC_CH1_ALC_GAIN_PDB_7_5 (0x11 << RK3308_ADC_CH1_ALC_GAIN_SFT) 800 #define RK3308_ADC_CH1_ALC_GAIN_PDB_6 (0x10 << RK3308_ADC_CH1_ALC_GAIN_SFT) 801 #define RK3308_ADC_CH1_ALC_GAIN_PDB_4_5 (0x0f << RK3308_ADC_CH1_ALC_GAIN_SFT) 802 #define RK3308_ADC_CH1_ALC_GAIN_PDB_3 (0x0e << RK3308_ADC_CH1_ALC_GAIN_SFT) 803 #define RK3308_ADC_CH1_ALC_GAIN_PDB_1_5 (0x0d << RK3308_ADC_CH1_ALC_GAIN_SFT) 804 #define RK3308_ADC_CH1_ALC_GAIN_0DB (0x0c << RK3308_ADC_CH1_ALC_GAIN_SFT) 805 #define RK3308_ADC_CH1_ALC_GAIN_NDB_1_5 (0x0b << RK3308_ADC_CH1_ALC_GAIN_SFT) 806 #define RK3308_ADC_CH1_ALC_GAIN_NDB_3 (0x0a << RK3308_ADC_CH1_ALC_GAIN_SFT) 807 #define RK3308_ADC_CH1_ALC_GAIN_NDB_4_5 (0x09 << RK3308_ADC_CH1_ALC_GAIN_SFT) 808 #define RK3308_ADC_CH1_ALC_GAIN_NDB_6 (0x08 << RK3308_ADC_CH1_ALC_GAIN_SFT) 809 #define RK3308_ADC_CH1_ALC_GAIN_NDB_7_5 (0x07 << RK3308_ADC_CH1_ALC_GAIN_SFT) 810 #define RK3308_ADC_CH1_ALC_GAIN_NDB_9 (0x06 << RK3308_ADC_CH1_ALC_GAIN_SFT) 811 #define RK3308_ADC_CH1_ALC_GAIN_NDB_10_5 (0x05 << RK3308_ADC_CH1_ALC_GAIN_SFT) 812 #define RK3308_ADC_CH1_ALC_GAIN_NDB_12 (0x04 << RK3308_ADC_CH1_ALC_GAIN_SFT) 813 #define RK3308_ADC_CH1_ALC_GAIN_NDB_13_5 (0x03 << RK3308_ADC_CH1_ALC_GAIN_SFT) 814 #define RK3308_ADC_CH1_ALC_GAIN_NDB_15 (0x02 << RK3308_ADC_CH1_ALC_GAIN_SFT) 815 #define RK3308_ADC_CH1_ALC_GAIN_NDB_16_5 (0x01 << RK3308_ADC_CH1_ALC_GAIN_SFT) 816 #define RK3308_ADC_CH1_ALC_GAIN_NDB_18 (0x00 << RK3308_ADC_CH1_ALC_GAIN_SFT) 817 818 /* RK3308_ADC_ANA_CON04 - REG: 0x0350 */ 819 #define RK3308_ADC_CH2_ALC_GAIN_MAX 0x1f 820 #define RK3308_ADC_CH2_ALC_GAIN_MIN 0 821 #define RK3308_ADC_CH2_ALC_GAIN_SFT 0 822 #define RK3308_ADC_CH2_ALC_GAIN_MSK (0x1f << RK3308_ADC_CH2_ALC_GAIN_SFT) 823 #define RK3308_ADC_CH2_ALC_GAIN_PDB_28_5 (0x1f << RK3308_ADC_CH2_ALC_GAIN_SFT) 824 #define RK3308_ADC_CH2_ALC_GAIN_PDB_27 (0x1e << RK3308_ADC_CH2_ALC_GAIN_SFT) 825 #define RK3308_ADC_CH2_ALC_GAIN_PDB_25_5 (0x1d << RK3308_ADC_CH2_ALC_GAIN_SFT) 826 #define RK3308_ADC_CH2_ALC_GAIN_PDB_24 (0x1c << RK3308_ADC_CH2_ALC_GAIN_SFT) 827 #define RK3308_ADC_CH2_ALC_GAIN_PDB_22_5 (0x1b << RK3308_ADC_CH2_ALC_GAIN_SFT) 828 #define RK3308_ADC_CH2_ALC_GAIN_PDB_21 (0x1a << RK3308_ADC_CH2_ALC_GAIN_SFT) 829 #define RK3308_ADC_CH2_ALC_GAIN_PDB_19_5 (0x19 << RK3308_ADC_CH2_ALC_GAIN_SFT) 830 #define RK3308_ADC_CH2_ALC_GAIN_PDB_18 (0x18 << RK3308_ADC_CH2_ALC_GAIN_SFT) 831 #define RK3308_ADC_CH2_ALC_GAIN_PDB_16_5 (0x17 << RK3308_ADC_CH2_ALC_GAIN_SFT) 832 #define RK3308_ADC_CH2_ALC_GAIN_PDB_15 (0x16 << RK3308_ADC_CH2_ALC_GAIN_SFT) 833 #define RK3308_ADC_CH2_ALC_GAIN_PDB_13_5 (0x15 << RK3308_ADC_CH2_ALC_GAIN_SFT) 834 #define RK3308_ADC_CH2_ALC_GAIN_PDB_12 (0x14 << RK3308_ADC_CH2_ALC_GAIN_SFT) 835 #define RK3308_ADC_CH2_ALC_GAIN_PDB_10_5 (0x13 << RK3308_ADC_CH2_ALC_GAIN_SFT) 836 #define RK3308_ADC_CH2_ALC_GAIN_PDB_9 (0x12 << RK3308_ADC_CH2_ALC_GAIN_SFT) 837 #define RK3308_ADC_CH2_ALC_GAIN_PDB_7_5 (0x11 << RK3308_ADC_CH2_ALC_GAIN_SFT) 838 #define RK3308_ADC_CH2_ALC_GAIN_PDB_6 (0x10 << RK3308_ADC_CH2_ALC_GAIN_SFT) 839 #define RK3308_ADC_CH2_ALC_GAIN_PDB_4_5 (0x0f << RK3308_ADC_CH2_ALC_GAIN_SFT) 840 #define RK3308_ADC_CH2_ALC_GAIN_PDB_3 (0x0e << RK3308_ADC_CH2_ALC_GAIN_SFT) 841 #define RK3308_ADC_CH2_ALC_GAIN_PDB_1_5 (0x0d << RK3308_ADC_CH2_ALC_GAIN_SFT) 842 #define RK3308_ADC_CH2_ALC_GAIN_0DB (0x0c << RK3308_ADC_CH2_ALC_GAIN_SFT) 843 #define RK3308_ADC_CH2_ALC_GAIN_NDB_1_5 (0x0b << RK3308_ADC_CH2_ALC_GAIN_SFT) 844 #define RK3308_ADC_CH2_ALC_GAIN_NDB_3 (0x0a << RK3308_ADC_CH2_ALC_GAIN_SFT) 845 #define RK3308_ADC_CH2_ALC_GAIN_NDB_4_5 (0x09 << RK3308_ADC_CH2_ALC_GAIN_SFT) 846 #define RK3308_ADC_CH2_ALC_GAIN_NDB_6 (0x08 << RK3308_ADC_CH2_ALC_GAIN_SFT) 847 #define RK3308_ADC_CH2_ALC_GAIN_NDB_7_5 (0x07 << RK3308_ADC_CH2_ALC_GAIN_SFT) 848 #define RK3308_ADC_CH2_ALC_GAIN_NDB_9 (0x06 << RK3308_ADC_CH2_ALC_GAIN_SFT) 849 #define RK3308_ADC_CH2_ALC_GAIN_NDB_10_5 (0x05 << RK3308_ADC_CH2_ALC_GAIN_SFT) 850 #define RK3308_ADC_CH2_ALC_GAIN_NDB_12 (0x04 << RK3308_ADC_CH2_ALC_GAIN_SFT) 851 #define RK3308_ADC_CH2_ALC_GAIN_NDB_13_5 (0x03 << RK3308_ADC_CH2_ALC_GAIN_SFT) 852 #define RK3308_ADC_CH2_ALC_GAIN_NDB_15 (0x02 << RK3308_ADC_CH2_ALC_GAIN_SFT) 853 #define RK3308_ADC_CH2_ALC_GAIN_NDB_16_5 (0x01 << RK3308_ADC_CH2_ALC_GAIN_SFT) 854 #define RK3308_ADC_CH2_ALC_GAIN_NDB_18 (0x00 << RK3308_ADC_CH2_ALC_GAIN_SFT) 855 856 /* RK3308_ADC_ANA_CON05 - REG: 0x0354 */ 857 #define RK3308_ADC_CH2_ADC_CLK_MSK (0x7 << 4) 858 #define RK3308_ADC_CH2_ADC_WORK (0x1 << 6) 859 #define RK3308_ADC_CH2_ADC_INIT (0x0 << 6) 860 #define RK3308_ADC_CH2_ADC_EN (0x1 << 5) 861 #define RK3308_ADC_CH2_ADC_DIS (0x0 << 5) 862 #define RK3308_ADC_CH2_CLK_EN (0x1 << 4) 863 #define RK3308_ADC_CH2_CLK_DIS (0x0 << 4) 864 865 #define RK3308_ADC_CH1_ADC_CLK_MSK (0x7 << 0) 866 #define RK3308_ADC_CH1_ADC_WORK (0x1 << 2) 867 #define RK3308_ADC_CH1_ADC_INIT (0x0 << 2) 868 #define RK3308_ADC_CH1_ADC_EN (0x1 << 1) 869 #define RK3308_ADC_CH1_ADC_DIS (0x0 << 1) 870 #define RK3308_ADC_CH1_CLK_EN (0x1 << 0) 871 #define RK3308_ADC_CH1_CLK_DIS (0x0 << 0) 872 873 /* RK3308_ADC_ANA_CON06 - REG: 0x0358 */ 874 #define RK3308_ADC_CURRENT_MSK (0x1 << 0) 875 #define RK3308_ADC_CURRENT_EN (0x1 << 0) 876 #define RK3308_ADC_CURRENT_DIS (0x0 << 0) 877 878 /* RK3308_ADC_ANA_CON07 - REG: 0x035c */ 879 /* Note: The register configuration is only valid for ADC2 */ 880 #define RK3308_ADC_CH2_IN_SEL_SFT 6 881 #define RK3308_ADC_CH2_IN_SEL_MSK (0x3 << RK3308_ADC_CH2_IN_SEL_SFT) 882 #define RK3308_ADC_CH2_IN_LINEIN_MIC (0x3 << RK3308_ADC_CH2_IN_SEL_SFT) 883 #define RK3308_ADC_CH2_IN_LINEIN (0x2 << RK3308_ADC_CH2_IN_SEL_SFT) 884 #define RK3308_ADC_CH2_IN_MIC (0x1 << RK3308_ADC_CH2_IN_SEL_SFT) 885 #define RK3308_ADC_CH2_IN_NONE (0x0 << RK3308_ADC_CH2_IN_SEL_SFT) 886 /* Note: The register configuration is only valid for ADC1 */ 887 #define RK3308_ADC_CH1_IN_SEL_SFT 4 888 #define RK3308_ADC_CH1_IN_SEL_MSK (0x3 << RK3308_ADC_CH1_IN_SEL_SFT) 889 #define RK3308_ADC_CH1_IN_LINEIN_MIC (0x3 << RK3308_ADC_CH1_IN_SEL_SFT) 890 #define RK3308_ADC_CH1_IN_LINEIN (0x2 << RK3308_ADC_CH1_IN_SEL_SFT) 891 #define RK3308_ADC_CH1_IN_MIC (0x1 << RK3308_ADC_CH1_IN_SEL_SFT) 892 #define RK3308_ADC_CH1_IN_NONE (0x0 << RK3308_ADC_CH1_IN_SEL_SFT) 893 894 #define RK3308_ADC_MIC_BIAS_BUF_SFT 3 895 #define RK3308_ADC_MIC_BIAS_BUF_EN (0x1 << RK3308_ADC_MIC_BIAS_BUF_SFT) 896 #define RK3308_ADC_MIC_BIAS_BUF_DIS (0x0 << RK3308_ADC_MIC_BIAS_BUF_SFT) 897 #define RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT 0 898 #define RK3308_ADC_LEVEL_RANGE_MICBIAS_MSK (0x7 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) 899 /* 900 * The follow MICBIAS_VOLTs are based on the external reference voltage(Vref). 901 * For example, the Vref == 3.3V, the MICBIAS_VOLT_0_85 is equal: 902 * 3.3V * 0.85 = 2.805V. 903 */ 904 #define RK3308_ADC_MICBIAS_VOLT_0_85 (0x7 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) 905 #define RK3308_ADC_MICBIAS_VOLT_0_8 (0x6 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) 906 #define RK3308_ADC_MICBIAS_VOLT_0_75 (0x5 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) 907 #define RK3308_ADC_MICBIAS_VOLT_0_7 (0x4 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) 908 #define RK3308_ADC_MICBIAS_VOLT_0_65 (0x3 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) 909 #define RK3308_ADC_MICBIAS_VOLT_0_6 (0x2 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) 910 #define RK3308_ADC_MICBIAS_VOLT_0_55 (0x1 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) 911 #define RK3308_ADC_MICBIAS_VOLT_0_5 (0x0 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) 912 913 /* RK3308_ADC_ANA_CON08 - REG: 0x0360 */ 914 #define RK3308_ADC_MICBIAS_CURRENT_MSK (0x1 << 4) 915 #define RK3308_ADC_MICBIAS_CURRENT_EN (0x1 << 4) 916 #define RK3308_ADC_MICBIAS_CURRENT_DIS (0x0 << 4) 917 #define RK3308BS_ADC_MICBIAS_CURRENT_SEL(x) ((x) & 0xf) 918 919 /* RK3308BS_ADC_ANA_CON09 - REG: 0x0364 */ 920 #define RK3308BS_ADC_MICBIAS_OPA_VBIAS(x) (((x) & 0x7) << 4) 921 #define RK3308BS_ADC_VCM_SETUP_MIN_CURRENT_EN (0x0 << 1) 922 #define RK3308BS_ADC_VCM_SETUP_MIN_CURRENT_DIS (0x0 << 0) 923 924 /* RK3308_ADC_ANA_CON10 - REG: 0x0368 */ 925 #define RK3308_ADC_REF_EN (0x1 << 7) 926 #define RK3308_ADC_REF_DIS (0x0 << 7) 927 #define RK3308_ADC_CURRENT_CHARGE_SFT 0 928 #define RK3308_ADC_CURRENT_CHARGE_MSK (0x7f << RK3308_ADC_CURRENT_CHARGE_SFT) 929 /* 930 * 1: Choose the current I 931 * 0: Don't choose the current I 932 */ 933 #define RK3308_ADC_SEL_I(x) ((x) & 0x7f) 934 935 /* RK3308_ADC_ANA_CON11 - REG: 0x036c */ 936 #define RK3308_ADC_ALCR_CON_GAIN_PGAR_MSK (0x1 << 1) 937 #define RK3308_ADC_ALCR_CON_GAIN_PGAR_EN (0x1 << 1) 938 #define RK3308_ADC_ALCR_CON_GAIN_PGAR_DIS (0x0 << 1) 939 #define RK3308_ADC_ALCL_CON_GAIN_PGAL_MSK (0x1 << 0) 940 #define RK3308_ADC_ALCL_CON_GAIN_PGAL_EN (0x1 << 0) 941 #define RK3308_ADC_ALCL_CON_GAIN_PGAL_DIS (0x0 << 0) 942 943 /* RK3308_DAC_ANA_CON00 - REG: 0x0440 */ 944 #define RK3308_DAC_CURRENT_SEL_SFT 4 945 #define RK3308_DAC_CURRENT_SEL_MSK (0xf << RK3308_DAC_CURRENT_SEL_SFT) 946 #define RK3308_DAC_CURRENT_SEL(x) ((x) & RK3308_DAC_CURRENT_SEL_MSK) 947 #define RK3308_DAC_HEADPHONE_DET_MSK (0x1 << 1) 948 #define RK3308_DAC_HEADPHONE_DET_EN (0x1 << 1) 949 #define RK3308_DAC_HEADPHONE_DET_DIS (0x0 << 1) 950 #define RK3308_DAC_CURRENT_MSK (0x1 << 0) 951 #define RK3308_DAC_CURRENT_EN (0x1 << 0) 952 #define RK3308_DAC_CURRENT_DIS (0x0 << 0) 953 954 /* RK3308_DAC_ANA_CON01 - REG: 0x0444 */ 955 #define RK3308_DAC_BUF_REF_R_MSK (0x1 << 6) 956 #define RK3308_DAC_BUF_REF_R_EN (0x1 << 6) 957 #define RK3308_DAC_BUF_REF_R_DIS (0x0 << 6) 958 #define RK3308_DAC_HPOUT_POP_SOUND_R_SFT 4 959 #define RK3308_DAC_HPOUT_POP_SOUND_R_MSK (0x3 << RK3308_DAC_HPOUT_POP_SOUND_R_SFT) 960 #define RK3308_DAC_HPOUT_POP_SOUND_R_WORK (0x2 << RK3308_DAC_HPOUT_POP_SOUND_R_SFT) 961 #define RK3308_DAC_HPOUT_POP_SOUND_R_INIT (0x1 << RK3308_DAC_HPOUT_POP_SOUND_R_SFT) 962 #define RK3308_DAC_HPOUT_POP_SOUND_R_DIS (0x0 << RK3308_DAC_HPOUT_POP_SOUND_R_SFT) 963 #define RK3308_DAC_BUF_REF_L_MSK (0x1 << 2) 964 #define RK3308_DAC_BUF_REF_L_EN (0x1 << 2) 965 #define RK3308_DAC_BUF_REF_L_DIS (0x0 << 2) 966 #define RK3308_DAC_HPOUT_POP_SOUND_L_SFT 0 967 #define RK3308_DAC_HPOUT_POP_SOUND_L_MSK (0x3 << RK3308_DAC_HPOUT_POP_SOUND_L_SFT) 968 #define RK3308_DAC_HPOUT_POP_SOUND_L_WORK (0x2 << RK3308_DAC_HPOUT_POP_SOUND_L_SFT) 969 #define RK3308_DAC_HPOUT_POP_SOUND_L_INIT (0x1 << RK3308_DAC_HPOUT_POP_SOUND_L_SFT) 970 #define RK3308_DAC_HPOUT_POP_SOUND_L_DIS (0x0 << RK3308_DAC_HPOUT_POP_SOUND_L_SFT) 971 972 /* RK3308_DAC_ANA_CON02 - REG: 0x0448 */ 973 #define RK3308_DAC_R_DAC_WORK (0x1 << 7) 974 #define RK3308_DAC_R_DAC_INIT (0x0 << 7) 975 #define RK3308_DAC_R_DAC_EN (0x1 << 6) 976 #define RK3308_DAC_R_DAC_DIS (0x0 << 6) 977 #define RK3308_DAC_R_CLK_EN (0x1 << 5) 978 #define RK3308_DAC_R_CLK_DIS (0x0 << 5) 979 #define RK3308_DAC_R_REF_EN (0x1 << 4) 980 #define RK3308_DAC_R_REF_DIS (0x0 << 4) 981 #define RK3308_DAC_L_DAC_WORK (0x1 << 3) 982 #define RK3308_DAC_L_DAC_INIT (0x0 << 3) 983 #define RK3308_DAC_L_DAC_EN (0x1 << 2) 984 #define RK3308_DAC_L_DAC_DIS (0x0 << 2) 985 #define RK3308_DAC_L_CLK_EN (0x1 << 1) 986 #define RK3308_DAC_L_CLK_DIS (0x0 << 1) 987 #define RK3308_DAC_L_REF_EN (0x1 << 0) 988 #define RK3308_DAC_L_REF_DIS (0x0 << 0) 989 990 /* RK3308_DAC_ANA_CON03 - REG: 0x044c */ 991 #define RK3308_DAC_R_HPOUT_WORK (0x1 << 6) 992 #define RK3308_DAC_R_HPOUT_INIT (0x0 << 6) 993 #define RK3308_DAC_R_HPOUT_EN (0x1 << 5) 994 #define RK3308_DAC_R_HPOUT_DIS (0x0 << 5) 995 #define RK3308_DAC_R_HPOUT_UNMUTE (0x1 << 4) 996 #define RK3308_DAC_R_HPOUT_MUTE (0x0 << 4) 997 #define RK3308_DAC_L_HPOUT_WORK (0x1 << 2) 998 #define RK3308_DAC_L_HPOUT_INIT (0x0 << 2) 999 #define RK3308_DAC_L_HPOUT_EN (0x1 << 1) 1000 #define RK3308_DAC_L_HPOUT_DIS (0x0 << 1) 1001 #define RK3308_DAC_L_HPOUT_UNMUTE (0x1 << 0) 1002 #define RK3308_DAC_L_HPOUT_MUTE (0x0 << 0) 1003 1004 /* RK3308_DAC_ANA_CON04 - REG: 0x0450 */ 1005 #define RK3308_DAC_R_LINEOUT_GAIN_MAX 0x3 1006 #define RK3308_DAC_R_LINEOUT_GAIN_SFT 6 1007 #define RK3308_DAC_R_LINEOUT_GAIN_MSK (0x3 << RK3308_DAC_R_LINEOUT_GAIN_SFT) 1008 #define RK3308_DAC_R_LINEOUT_GAIN_0DB (0x3 << RK3308_DAC_R_LINEOUT_GAIN_SFT) 1009 #define RK3308_DAC_R_LINEOUT_GAIN_NDB_1_5 (0x2 << RK3308_DAC_R_LINEOUT_GAIN_SFT) 1010 #define RK3308_DAC_R_LINEOUT_GAIN_NDB_3 (0x1 << RK3308_DAC_R_LINEOUT_GAIN_SFT) 1011 #define RK3308_DAC_R_LINEOUT_GAIN_NDB_6 (0x0 << RK3308_DAC_R_LINEOUT_GAIN_SFT) 1012 #define RK3308_DAC_R_LINEOUT_UNMUTE (0x1 << 5) 1013 #define RK3308_DAC_R_LINEOUT_MUTE (0x0 << 5) 1014 #define RK3308_DAC_R_LINEOUT_EN (0x1 << 4) 1015 #define RK3308_DAC_R_LINEOUT_DIS (0x0 << 4) 1016 #define RK3308_DAC_L_LINEOUT_GAIN_MAX 0x3 1017 #define RK3308_DAC_L_LINEOUT_GAIN_SFT 2 1018 #define RK3308_DAC_L_LINEOUT_GAIN_MSK (0x3 << RK3308_DAC_L_LINEOUT_GAIN_SFT) 1019 #define RK3308_DAC_L_LINEOUT_GAIN_0DB (0x3 << RK3308_DAC_L_LINEOUT_GAIN_SFT) 1020 #define RK3308_DAC_L_LINEOUT_GAIN_NDB_1_5 (0x2 << RK3308_DAC_L_LINEOUT_GAIN_SFT) 1021 #define RK3308_DAC_L_LINEOUT_GAIN_NDB_3 (0x1 << RK3308_DAC_L_LINEOUT_GAIN_SFT) 1022 #define RK3308_DAC_L_LINEOUT_GAIN_NDB_6 (0x0 << RK3308_DAC_L_LINEOUT_GAIN_SFT) 1023 #define RK3308_DAC_L_LINEOUT_UNMUTE (0x1 << 1) 1024 #define RK3308_DAC_L_LINEOUT_MUTE (0x0 << 1) 1025 #define RK3308_DAC_L_LINEOUT_EN (0x1 << 0) 1026 #define RK3308_DAC_L_LINEOUT_DIS (0x0 << 0) 1027 1028 /* RK3308_DAC_ANA_CON05 - REG: 0x0454, step is 1.5db */ 1029 #define RK3308_DAC_L_HPOUT_GAIN_MAX 0x1e 1030 #define RK3308_DAC_L_HPOUT_GAIN_SFT 0 1031 #define RK3308_DAC_L_HPOUT_GAIN_MSK (0x1f << RK3308_DAC_L_HPOUT_GAIN_SFT) 1032 #define RK3308_DAC_L_HPOUT_GAIN_PDB_6 (0x1e << RK3308_DAC_L_HPOUT_GAIN_SFT) 1033 #define RK3308_DAC_L_HPOUT_GAIN_PDB_4_5 (0x1d << RK3308_DAC_L_HPOUT_GAIN_SFT) 1034 #define RK3308_DAC_L_HPOUT_GAIN_PDB_3 (0x1c << RK3308_DAC_L_HPOUT_GAIN_SFT) 1035 #define RK3308_DAC_L_HPOUT_GAIN_PDB_1_5 (0x1b << RK3308_DAC_L_HPOUT_GAIN_SFT) 1036 #define RK3308_DAC_L_HPOUT_GAIN_0DB (0x1a << RK3308_DAC_L_HPOUT_GAIN_SFT) 1037 #define RK3308_DAC_L_HPOUT_GAIN_NDB_1_5 (0x19 << RK3308_DAC_L_HPOUT_GAIN_SFT) 1038 #define RK3308_DAC_L_HPOUT_GAIN_NDB_3 (0x18 << RK3308_DAC_L_HPOUT_GAIN_SFT) 1039 #define RK3308_DAC_L_HPOUT_GAIN_NDB_4_5 (0x17 << RK3308_DAC_L_HPOUT_GAIN_SFT) 1040 #define RK3308_DAC_L_HPOUT_GAIN_NDB_6 (0x16 << RK3308_DAC_L_HPOUT_GAIN_SFT) 1041 #define RK3308_DAC_L_HPOUT_GAIN_NDB_7_5 (0x15 << RK3308_DAC_L_HPOUT_GAIN_SFT) 1042 #define RK3308_DAC_L_HPOUT_GAIN_NDB_9 (0x14 << RK3308_DAC_L_HPOUT_GAIN_SFT) 1043 #define RK3308_DAC_L_HPOUT_GAIN_NDB_10_5 (0x13 << RK3308_DAC_L_HPOUT_GAIN_SFT) 1044 #define RK3308_DAC_L_HPOUT_GAIN_NDB_12 (0x12 << RK3308_DAC_L_HPOUT_GAIN_SFT) 1045 #define RK3308_DAC_L_HPOUT_GAIN_NDB_13_5 (0x11 << RK3308_DAC_L_HPOUT_GAIN_SFT) 1046 #define RK3308_DAC_L_HPOUT_GAIN_NDB_15 (0x10 << RK3308_DAC_L_HPOUT_GAIN_SFT) 1047 #define RK3308_DAC_L_HPOUT_GAIN_NDB_16_5 (0x0f << RK3308_DAC_L_HPOUT_GAIN_SFT) 1048 #define RK3308_DAC_L_HPOUT_GAIN_NDB_18 (0x0e << RK3308_DAC_L_HPOUT_GAIN_SFT) 1049 #define RK3308_DAC_L_HPOUT_GAIN_NDB_19_5 (0x0d << RK3308_DAC_L_HPOUT_GAIN_SFT) 1050 #define RK3308_DAC_L_HPOUT_GAIN_NDB_21 (0x0c << RK3308_DAC_L_HPOUT_GAIN_SFT) 1051 #define RK3308_DAC_L_HPOUT_GAIN_NDB_22_5 (0x0b << RK3308_DAC_L_HPOUT_GAIN_SFT) 1052 #define RK3308_DAC_L_HPOUT_GAIN_NDB_24 (0x0a << RK3308_DAC_L_HPOUT_GAIN_SFT) 1053 #define RK3308_DAC_L_HPOUT_GAIN_NDB_25_5 (0x09 << RK3308_DAC_L_HPOUT_GAIN_SFT) 1054 #define RK3308_DAC_L_HPOUT_GAIN_NDB_27 (0x08 << RK3308_DAC_L_HPOUT_GAIN_SFT) 1055 #define RK3308_DAC_L_HPOUT_GAIN_NDB_28_5 (0x07 << RK3308_DAC_L_HPOUT_GAIN_SFT) 1056 #define RK3308_DAC_L_HPOUT_GAIN_NDB_30 (0x06 << RK3308_DAC_L_HPOUT_GAIN_SFT) 1057 #define RK3308_DAC_L_HPOUT_GAIN_NDB_31_5 (0x05 << RK3308_DAC_L_HPOUT_GAIN_SFT) 1058 #define RK3308_DAC_L_HPOUT_GAIN_NDB_33 (0x04 << RK3308_DAC_L_HPOUT_GAIN_SFT) 1059 #define RK3308_DAC_L_HPOUT_GAIN_NDB_34_5 (0x03 << RK3308_DAC_L_HPOUT_GAIN_SFT) 1060 #define RK3308_DAC_L_HPOUT_GAIN_NDB_36 (0x02 << RK3308_DAC_L_HPOUT_GAIN_SFT) 1061 #define RK3308_DAC_L_HPOUT_GAIN_NDB_37_5 (0x01 << RK3308_DAC_L_HPOUT_GAIN_SFT) 1062 #define RK3308_DAC_L_HPOUT_GAIN_NDB_39 (0x00 << RK3308_DAC_L_HPOUT_GAIN_SFT) 1063 1064 /* RK3308_DAC_ANA_CON06 - REG: 0x0458, step is 1.5db */ 1065 #define RK3308_DAC_R_HPOUT_GAIN_MAX 0x1e 1066 #define RK3308_DAC_R_HPOUT_GAIN_SFT 0 1067 #define RK3308_DAC_R_HPOUT_GAIN_MSK (0x1f << RK3308_DAC_R_HPOUT_GAIN_SFT) 1068 #define RK3308_DAC_R_HPOUT_GAIN_PDB_6 (0x1e << RK3308_DAC_R_HPOUT_GAIN_SFT) 1069 #define RK3308_DAC_R_HPOUT_GAIN_PDB_4_5 (0x1d << RK3308_DAC_R_HPOUT_GAIN_SFT) 1070 #define RK3308_DAC_R_HPOUT_GAIN_PDB_3 (0x1c << RK3308_DAC_R_HPOUT_GAIN_SFT) 1071 #define RK3308_DAC_R_HPOUT_GAIN_PDB_1_5 (0x1b << RK3308_DAC_R_HPOUT_GAIN_SFT) 1072 #define RK3308_DAC_R_HPOUT_GAIN_0DB (0x1a << RK3308_DAC_R_HPOUT_GAIN_SFT) 1073 #define RK3308_DAC_R_HPOUT_GAIN_NDB_1_5 (0x19 << RK3308_DAC_R_HPOUT_GAIN_SFT) 1074 #define RK3308_DAC_R_HPOUT_GAIN_NDB_3 (0x18 << RK3308_DAC_R_HPOUT_GAIN_SFT) 1075 #define RK3308_DAC_R_HPOUT_GAIN_NDB_4_5 (0x17 << RK3308_DAC_R_HPOUT_GAIN_SFT) 1076 #define RK3308_DAC_R_HPOUT_GAIN_NDB_6 (0x16 << RK3308_DAC_R_HPOUT_GAIN_SFT) 1077 #define RK3308_DAC_R_HPOUT_GAIN_NDB_7_5 (0x15 << RK3308_DAC_R_HPOUT_GAIN_SFT) 1078 #define RK3308_DAC_R_HPOUT_GAIN_NDB_9 (0x14 << RK3308_DAC_R_HPOUT_GAIN_SFT) 1079 #define RK3308_DAC_R_HPOUT_GAIN_NDB_10_5 (0x13 << RK3308_DAC_R_HPOUT_GAIN_SFT) 1080 #define RK3308_DAC_R_HPOUT_GAIN_NDB_12 (0x12 << RK3308_DAC_R_HPOUT_GAIN_SFT) 1081 #define RK3308_DAC_R_HPOUT_GAIN_NDB_13_5 (0x11 << RK3308_DAC_R_HPOUT_GAIN_SFT) 1082 #define RK3308_DAC_R_HPOUT_GAIN_NDB_15 (0x10 << RK3308_DAC_R_HPOUT_GAIN_SFT) 1083 #define RK3308_DAC_R_HPOUT_GAIN_NDB_16_5 (0x0f << RK3308_DAC_R_HPOUT_GAIN_SFT) 1084 #define RK3308_DAC_R_HPOUT_GAIN_NDB_18 (0x0e << RK3308_DAC_R_HPOUT_GAIN_SFT) 1085 #define RK3308_DAC_R_HPOUT_GAIN_NDB_19_5 (0x0d << RK3308_DAC_R_HPOUT_GAIN_SFT) 1086 #define RK3308_DAC_R_HPOUT_GAIN_NDB_21 (0x0c << RK3308_DAC_R_HPOUT_GAIN_SFT) 1087 #define RK3308_DAC_R_HPOUT_GAIN_NDB_22_5 (0x0b << RK3308_DAC_R_HPOUT_GAIN_SFT) 1088 #define RK3308_DAC_R_HPOUT_GAIN_NDB_24 (0x0a << RK3308_DAC_R_HPOUT_GAIN_SFT) 1089 #define RK3308_DAC_R_HPOUT_GAIN_NDB_25_5 (0x09 << RK3308_DAC_R_HPOUT_GAIN_SFT) 1090 #define RK3308_DAC_R_HPOUT_GAIN_NDB_27 (0x08 << RK3308_DAC_R_HPOUT_GAIN_SFT) 1091 #define RK3308_DAC_R_HPOUT_GAIN_NDB_28_5 (0x07 << RK3308_DAC_R_HPOUT_GAIN_SFT) 1092 #define RK3308_DAC_R_HPOUT_GAIN_NDB_30 (0x06 << RK3308_DAC_R_HPOUT_GAIN_SFT) 1093 #define RK3308_DAC_R_HPOUT_GAIN_NDB_31_5 (0x05 << RK3308_DAC_R_HPOUT_GAIN_SFT) 1094 #define RK3308_DAC_R_HPOUT_GAIN_NDB_33 (0x04 << RK3308_DAC_R_HPOUT_GAIN_SFT) 1095 #define RK3308_DAC_R_HPOUT_GAIN_NDB_34_5 (0x03 << RK3308_DAC_R_HPOUT_GAIN_SFT) 1096 #define RK3308_DAC_R_HPOUT_GAIN_NDB_36 (0x02 << RK3308_DAC_R_HPOUT_GAIN_SFT) 1097 #define RK3308_DAC_R_HPOUT_GAIN_NDB_37_5 (0x01 << RK3308_DAC_R_HPOUT_GAIN_SFT) 1098 #define RK3308_DAC_R_HPOUT_GAIN_NDB_39 (0x00 << RK3308_DAC_R_HPOUT_GAIN_SFT) 1099 1100 /* RK3308_DAC_ANA_CON07 - REG: 0x045c */ 1101 #define RK3308_DAC_R_HPOUT_DRV_SFT 4 1102 #define RK3308_DAC_R_HPOUT_DRV_MSK (0xf << RK3308_DAC_R_HPOUT_DRV_SFT) 1103 #define RK3308_DAC_R_HPOUT_DRV(x) (((x) << RK3308_DAC_R_HPOUT_DRV_SFT) & RK3308_DAC_R_HPOUT_DRV_MSK) 1104 #define RK3308_DAC_L_HPOUT_DRV_SFT 0 1105 #define RK3308_DAC_L_HPOUT_DRV_MSK (0xf << RK3308_DAC_L_HPOUT_DRV_SFT) 1106 #define RK3308_DAC_L_HPOUT_DRV(x) (((x) << RK3308_DAC_L_HPOUT_DRV_SFT) & RK3308_DAC_L_HPOUT_DRV_MSK) 1107 1108 /* RK3308_DAC_ANA_CON08 - REG: 0x0460 */ 1109 #define RK3308_DAC_R_LINEOUT_DRV_SFT 4 1110 #define RK3308_DAC_R_LINEOUT_DRV_MSK (0xf << RK3308_DAC_R_LINEOUT_DRV_SFT) 1111 #define RK3308_DAC_R_LINEOUT_DRV(x) (((x) << RK3308_DAC_R_LINEOUT_DRV_SFT) & RK3308_DAC_R_LINEOUT_DRV_MSK) 1112 #define RK3308_DAC_L_LINEOUT_DRV_SFT 0 1113 #define RK3308_DAC_L_LINEOUT_DRV_MSK (0xf << RK3308_DAC_L_LINEOUT_DRV_SFT) 1114 #define RK3308_DAC_L_LINEOUT_DRV(x) (((x) << RK3308_DAC_L_LINEOUT_DRV_SFT) & RK3308_DAC_L_LINEOUT_DRV_MSK) 1115 1116 /* RK3308_DAC_ANA_CON12 - REG: 0x0470 */ 1117 #define RK3308_DAC_R_HPMIX_SEL_SFT 6 1118 #define RK3308_DAC_R_HPMIX_SEL_MSK (0x3 << RK3308_DAC_R_HPMIX_SEL_SFT) 1119 #define RK3308_DAC_R_HPMIX_LINEIN_I2S (0x3 << RK3308_DAC_R_HPMIX_SEL_SFT) 1120 #define RK3308_DAC_R_HPMIX_LINEIN (0x2 << RK3308_DAC_R_HPMIX_SEL_SFT) 1121 #define RK3308_DAC_R_HPMIX_I2S (0x1 << RK3308_DAC_R_HPMIX_SEL_SFT) 1122 #define RK3308_DAC_R_HPMIX_NONE (0x0 << RK3308_DAC_R_HPMIX_SEL_SFT) 1123 #define RK3308_DAC_R_HPMIX_GAIN_MIN 0x1 1124 #define RK3308_DAC_R_HPMIX_GAIN_MAX 0x2 1125 #define RK3308_DAC_R_HPMIX_GAIN_SFT 4 1126 #define RK3308_DAC_R_HPMIX_GAIN_MSK (0x3 << RK3308_DAC_R_HPMIX_GAIN_SFT) 1127 #define RK3308_DAC_R_HPMIX_GAIN_0DB (0x2 << RK3308_DAC_R_HPMIX_GAIN_SFT) 1128 #define RK3308_DAC_R_HPMIX_GAIN_NDB_6 (0x1 << RK3308_DAC_R_HPMIX_GAIN_SFT) 1129 #define RK3308_DAC_L_HPMIX_SEL_SFT 2 1130 #define RK3308_DAC_L_HPMIX_SEL_MSK (0x3 << RK3308_DAC_L_HPMIX_SEL_SFT) 1131 #define RK3308_DAC_L_HPMIX_LINEIN_I2S (0x3 << RK3308_DAC_L_HPMIX_SEL_SFT) 1132 #define RK3308_DAC_L_HPMIX_LINEIN (0x2 << RK3308_DAC_L_HPMIX_SEL_SFT) 1133 #define RK3308_DAC_L_HPMIX_I2S (0x1 << RK3308_DAC_L_HPMIX_SEL_SFT) 1134 #define RK3308_DAC_L_HPMIX_NONE (0x0 << RK3308_DAC_L_HPMIX_SEL_SFT) 1135 #define RK3308_DAC_L_HPMIX_GAIN_MIN 0x1 1136 #define RK3308_DAC_L_HPMIX_GAIN_MAX 0x2 1137 #define RK3308_DAC_L_HPMIX_GAIN_SFT 0 1138 #define RK3308_DAC_L_HPMIX_GAIN_MSK (0x3 << RK3308_DAC_L_HPMIX_GAIN_SFT) 1139 #define RK3308_DAC_L_HPMIX_GAIN_0DB (0x2 << RK3308_DAC_L_HPMIX_GAIN_SFT) 1140 #define RK3308_DAC_L_HPMIX_GAIN_NDB_6 (0x1 << RK3308_DAC_L_HPMIX_GAIN_SFT) 1141 1142 /* RK3308_DAC_ANA_CON13 - REG: 0x0474 */ 1143 #define RK3308_DAC_R_HPMIX_UNMUTE (0x1 << 6) 1144 #define RK3308_DAC_R_HPMIX_MUTE (0x0 << 6) 1145 #define RK3308_DAC_R_HPMIX_WORK (0x1 << 5) 1146 #define RK3308_DAC_R_HPMIX_INIT (0x0 << 5) 1147 #define RK3308_DAC_R_HPMIX_EN (0x1 << 4) 1148 #define RK3308_DAC_R_HPMIX_DIS (0x0 << 4) 1149 #define RK3308_DAC_L_HPMIX_UNMUTE (0x1 << 2) 1150 #define RK3308_DAC_L_HPMIX_MUTE (0x0 << 2) 1151 #define RK3308_DAC_L_HPMIX_WORK (0x1 << 1) 1152 #define RK3308_DAC_L_HPMIX_INIT (0x0 << 1) 1153 #define RK3308_DAC_L_HPMIX_EN (0x1 << 0) 1154 #define RK3308_DAC_L_HPMIX_DIS (0x0 << 0) 1155 1156 /* RK3308_DAC_ANA_CON14 - REG: 0x0478 */ 1157 #define RK3308_DAC_VCM_LINEOUT_EN (0x1 << 4) 1158 #define RK3308_DAC_VCM_LINEOUT_DIS (0x0 << 4) 1159 #define RK3308_DAC_CURRENT_CHARGE_SFT 0 1160 #define RK3308_DAC_CURRENT_CHARGE_MSK (0xf << RK3308_DAC_CURRENT_CHARGE_SFT) 1161 1162 /* 1163 * 1: Choose the current I 1164 * 0: Don't choose the current I 1165 */ 1166 #define RK3308_DAC_SEL_I(x) ((x) & 0xf) 1167 1168 /* RK3308_DAC_ANA_CON15 - REG: 0x047C */ 1169 #define RK3308_DAC_LINEOUT_POP_SOUND_R_SFT 4 1170 #define RK3308_DAC_LINEOUT_POP_SOUND_R_MSK (0x3 << RK3308_DAC_LINEOUT_POP_SOUND_R_SFT) 1171 #define RK3308_DAC_R_SEL_DC_FROM_INTERNAL (0x2 << RK3308_DAC_LINEOUT_POP_SOUND_R_SFT) 1172 #define RK3308_DAC_R_SEL_DC_FROM_VCM (0x1 << RK3308_DAC_LINEOUT_POP_SOUND_R_SFT) 1173 #define RK3308_DAC_R_SEL_LINEOUT_FROM_INTERNAL (0x0 << RK3308_DAC_LINEOUT_POP_SOUND_R_SFT) 1174 #define RK3308_DAC_LINEOUT_POP_SOUND_L_SFT 0 1175 #define RK3308_DAC_LINEOUT_POP_SOUND_L_MSK (0x3 << RK3308_DAC_LINEOUT_POP_SOUND_L_SFT) 1176 #define RK3308_DAC_L_SEL_DC_FROM_INTERNAL (0x2 << RK3308_DAC_LINEOUT_POP_SOUND_L_SFT) 1177 #define RK3308_DAC_L_SEL_DC_FROM_VCM (0x1 << RK3308_DAC_LINEOUT_POP_SOUND_L_SFT) 1178 #define RK3308_DAC_L_SEL_LINEOUT_FROM_INTERNAL (0x0 << RK3308_DAC_LINEOUT_POP_SOUND_L_SFT) 1179 1180 #define RK3308_HIFI 0x0 1181 1182 #endif /* __RK3308_CODEC_H__ */ 1183