1/* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT). 5 */ 6#include <dt-bindings/soc/rockchip-system-status.h> 7#include "rk3288-dram-default-timing.dtsi" 8 9/ { 10 chosen { 11 bootargs = "earlycon=uart8250,mmio32,0xff690000 console=ttyFIQ0 vmalloc=496M rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait"; 12 }; 13 14 /delete-node/ dmc@ff610000; 15 16 dfi: dfi { 17 compatible = "rockchip,rk3288-dfi"; 18 rockchip,pmu = <&pmu>; 19 rockchip,grf = <&grf>; 20 status = "disabled"; 21 }; 22 23 dmc: dmc { 24 compatible = "rockchip,rk3288-dmc"; 25 devfreq-events = <&dfi>; 26 clocks = <&cru SCLK_DDRCLK>, <&cru PCLK_PUBL0>, 27 <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL1>, 28 <&cru PCLK_DDRUPCTL1>; 29 clock-names = "dmc_clk", "pclk_phy0", "pclk_upctl0", 30 "pclk_phy1", "pclk_upctl1"; 31 upthreshold = <55>; 32 downdifferential = <10>; 33 operating-points-v2 = <&dmc_opp_table>; 34 vop-dclk-mode = <0>; 35 min-cpu-freq = <600000>; 36 rockchip,ddr_timing = <&ddr_timing>; 37 system-status-freq = < 38 /*system status freq(KHz)*/ 39 SYS_STATUS_NORMAL 396000 40 SYS_STATUS_REBOOT 396000 41 SYS_STATUS_SUSPEND 192000 42 SYS_STATUS_VIDEO_1080P 300000 43 SYS_STATUS_VIDEO_4K 396000 44 SYS_STATUS_VIDEO_4K_10B 528000 45 SYS_STATUS_PERFORMANCE 528000 46 SYS_STATUS_BOOST 396000 47 SYS_STATUS_DUALVIEW 396000 48 SYS_STATUS_ISP 396000 49 >; 50 auto-min-freq = <396000>; 51 auto-freq-en = <0>; 52 status = "diasbled"; 53 }; 54 55 dmc_opp_table: opp_table2 { 56 compatible = "operating-points-v2"; 57 58 opp-192000000 { 59 opp-hz = /bits/ 64 <192000000>; 60 opp-microvolt = <1100000>; 61 }; 62 opp-300000000 { 63 opp-hz = /bits/ 64 <300000000>; 64 opp-microvolt = <1100000>; 65 }; 66 opp-396000000 { 67 opp-hz = /bits/ 64 <396000000>; 68 opp-microvolt = <1100000>; 69 }; 70 opp-528000000 { 71 opp-hz = /bits/ 64 <528000000>; 72 opp-microvolt = <1150000>; 73 }; 74 }; 75 76 reserved-memory { 77 ramoops_mem: ramoops@8000000 { 78 reg = <0x0 0x8000000 0x0 0xF0000>; 79 }; 80 81 drm_logo: drm-logo@00000000 { 82 compatible = "rockchip,drm-logo"; 83 reg = <0x0 0x0 0x0 0x0>; 84 }; 85 }; 86 87 fiq-debugger { 88 compatible = "rockchip,fiq-debugger"; 89 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 90 rockchip,serial-id = <2>; 91 rockchip,wake-irq = <0>; 92 rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */ 93 rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ 94 pinctrl-names = "default"; 95 pinctrl-0 = <&uart2_xfer>; 96 }; 97 98 /delete-node/ timer@ff810000; 99 100 display-subsystem { 101 status = "okay"; 102 103 ports = <&vopb_out>, <&vopl_out>; 104 logo-memory-region = <&drm_logo>; 105 106 route { 107 route_hdmi: route-hdmi { 108 status = "disabled"; 109 logo,uboot = "logo.bmp"; 110 logo,kernel = "logo_kernel.bmp"; 111 logo,mode = "center"; 112 charge_logo,mode = "center"; 113 connect = <&vopb_out_hdmi>; 114 }; 115 116 route_edp: route-edp { 117 status = "disabled"; 118 logo,uboot = "logo.bmp"; 119 logo,kernel = "logo_kernel.bmp"; 120 logo,mode = "center"; 121 charge_logo,mode = "center"; 122 connect = <&vopl_out_edp>; 123 }; 124 125 route_dsi0: route-dsi0 { 126 status = "disabled"; 127 logo,uboot = "logo.bmp"; 128 logo,kernel = "logo_kernel.bmp"; 129 logo,mode = "center"; 130 charge_logo,mode = "center"; 131 connect = <&vopl_out_dsi0>; 132 }; 133 134 route_lvds: route-lvds { 135 status = "disabled"; 136 logo,uboot = "logo.bmp"; 137 logo,kernel = "logo_kernel.bmp"; 138 logo,mode = "center"; 139 charge_logo,mode = "center"; 140 connect = <&vopl_out_lvds>; 141 }; 142 143 route_rgb: route-rgb { 144 status = "disabled"; 145 logo,uboot = "logo.bmp"; 146 logo,kernel = "logo_kernel.bmp"; 147 logo,mode = "center"; 148 charge_logo,mode = "center"; 149 connect = <&vopl_out_rgb>; 150 }; 151 }; 152 }; 153}; 154 155&dmac_bus_s { 156 /* change to non-secure dmac */ 157 reg = <0x0 0xff600000 0x0 0x4000>; 158}; 159 160&efuse { 161 compatible = "rockchip,rk3288-secure-efuse"; 162}; 163 164&mpp_srv { 165 status = "okay"; 166}; 167 168&hevc { 169 status = "okay"; 170}; 171 172&hevc_mmu { 173 status = "okay"; 174}; 175 176&iep { 177 status = "okay"; 178}; 179 180&iep_mmu { 181 status = "okay"; 182}; 183 184&rga { 185 compatible = "rockchip,rga2"; 186 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; 187 clock-names = "aclk_rga", "hclk_rga", "clk_rga"; 188 status = "okay"; 189}; 190 191&rng { 192 status = "okay"; 193}; 194 195&uart2 { 196 status = "disabled"; 197}; 198 199&vdpu { 200 status = "okay"; 201}; 202 203&vepu { 204 status = "okay"; 205}; 206 207&vpu_mmu { 208 status = "okay"; 209}; 210 211&video_phy { 212 status = "okay"; 213}; 214
