1/* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3128-cru.h> 12#include <dt-bindings/media/rockchip_mipi_dsi.h> 13#include "skeleton.dtsi" 14 15/ { 16 compatible = "rockchip,rk3128"; 17 rockchip,sram = <&sram>; 18 interrupt-parent = <&gic>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 gpio3 = &gpio3; 27 i2c0 = &i2c0; 28 i2c1 = &i2c1; 29 i2c2 = &i2c2; 30 i2c3 = &i2c3; 31 spi0 = &spi0; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 mmc0 = &emmc; 36 mmc1 = &sdmmc; 37 }; 38 39 memory { 40 device_type = "memory"; 41 reg = <0x60000000 0x40000000>; 42 }; 43 44 arm-pmu { 45 compatible = "arm,cortex-a7-pmu"; 46 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 50 }; 51 52 cpus { 53 #address-cells = <1>; 54 #size-cells = <0>; 55 enable-method = "rockchip,rk3128-smp"; 56 57 cpu0:cpu@0x000 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a7"; 60 reg = <0x000>; 61 operating-points = < 62 /* KHz uV */ 63 816000 1000000 64 >; 65 #cooling-cells = <2>; /* min followed by max */ 66 clock-latency = <40000>; 67 clocks = <&cru ARMCLK>; 68 }; 69 70 cpu1:cpu@0x001 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a7"; 73 reg = <0x001>; 74 }; 75 76 cpu2:cpu@0x002 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a7"; 79 reg = <0x002>; 80 }; 81 82 cpu3:cpu@0x003 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a7"; 85 reg = <0x003>; 86 }; 87 }; 88 89 cpu_axi_bus: cpu_axi_bus { 90 compatible = "rockchip,cpu_axi_bus"; 91 #address-cells = <1>; 92 #size-cells = <1>; 93 ranges; 94 95 qos { 96 #address-cells = <1>; 97 #size-cells = <1>; 98 ranges; 99 100 crypto { 101 reg = <0x10128080 0x20>; 102 }; 103 104 core { 105 reg = <0x1012a000 0x20>; 106 }; 107 108 peri { 109 reg = <0x1012c000 0x20>; 110 }; 111 112 gpu { 113 reg = <0x1012d000 0x20>; 114 }; 115 116 vpu { 117 reg = <0x1012e000 0x20>; 118 }; 119 120 rga { 121 reg = <0x1012f000 0x20>; 122 }; 123 ebc { 124 reg = <0x1012f080 0x20>; 125 }; 126 127 iep { 128 reg = <0x1012f100 0x20>; 129 }; 130 131 lcdc { 132 reg = <0x1012f180 0x20>; 133 rockchip,priority = <3 3>; 134 }; 135 136 vip { 137 reg = <0x1012f200 0x20>; 138 rockchip,priority = <3 3>; 139 }; 140 }; 141 142 msch { 143 #address-cells = <1>; 144 #size-cells = <1>; 145 ranges; 146 147 msch@10128000 { 148 reg = <0x10128000 0x20>; 149 rockchip,read-latency = <0x3f>; 150 }; 151 }; 152 }; 153 154 psci: psci { 155 compatible = "arm,psci-1.0"; 156 method = "smc"; 157 }; 158 159 amba { 160 compatible = "arm,amba-bus"; 161 #address-cells = <1>; 162 #size-cells = <1>; 163 interrupt-parent = <&gic>; 164 ranges; 165 166 pdma: pdma@20078000 { 167 compatible = "arm,pl330", "arm,primecell"; 168 reg = <0x20078000 0x4000>; 169 arm,pl330-broken-no-flushp;//2 170 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 172 #dma-cells = <1>; 173 clocks = <&cru ACLK_DMAC>; 174 clock-names = "apb_pclk"; 175 }; 176 }; 177 178 xin24m: xin24m { 179 compatible = "fixed-clock"; 180 clock-frequency = <24000000>; 181 clock-output-names = "xin24m"; 182 #clock-cells = <0>; 183 }; 184 185 xin12m: xin12m { 186 compatible = "fixed-clock"; 187 clocks = <&xin24m>; 188 clock-frequency = <12000000>; 189 clock-output-names = "xin12m"; 190 #clock-cells = <0>; 191 }; 192 193 194 timer { 195 compatible = "arm,armv7-timer"; 196 arm,cpu-registers-not-fw-configured; 197 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 198 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 199 clock-frequency = <24000000>; 200 }; 201 202 timer@20044000 { 203 compatible = "arm,armv7-timer"; 204 reg = <0x20044000 0xb8>; 205 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 206 rockchip,broadcast = <1>; 207 }; 208 209 watchdog: wdt@2004c000 { 210 compatible = "rockchip,watch dog"; 211 reg = <0x2004c000 0x100>; 212 clock-names = "pclk_wdt"; 213 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 214 rockchip,irq = <1>; 215 rockchip,timeout = <60>; 216 rockchip,atboot = <1>; 217 rockchip,debug = <0>; 218 }; 219 220 reset: reset@20000110 { 221 compatible = "rockchip,reset"; 222 reg = <0x20000110 0x24>; 223 #reset-cells = <1>; 224 }; 225 226 sfc: sfc@1020c000 { 227 compatible ="rockchip,rksfc","rockchip,sfc"; 228 reg = <0x1020c000 0x8000>; 229 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 230 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 231 clock-names = "clk_sfc", "hclk_sfc"; 232 assigned-clocks = <&cru SCLK_SFC>; 233 assigned-clock-rates = <60000000>; 234 status = "disabled"; 235 }; 236 237 nandc: nandc@10500000 { 238 compatible = "rockchip,rk-nandc"; 239 reg = <0x10500000 0x4000>; 240 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 241 nandc_id = <0>; 242 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 243 clock-names = "clk_nandc", "hclk_nandc"; 244 status = "disabled"; 245 }; 246 247 dmc: dmc@20004000 { 248 compatible = "rockchip,rk3128-dmc", "syscon"; 249 reg = <0x0 0x20004000 0x0 0x1000>; 250 }; 251 252 cru: clock-controller@20000000 { 253 compatible = "rockchip,rk3128-cru"; 254 reg = <0x20000000 0x1000>; 255 rockchip,grf = <&grf>; 256 #clock-cells = <1>; 257 #reset-cells = <1>; 258 assigned-clocks = <&cru PLL_GPLL>; 259 assigned-clock-rates = <594000000>; 260 }; 261 262 uart0: serial0@20060000 { 263 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 264 reg = <0x20060000 0x100>; 265 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 266 reg-shift = <2>; 267 reg-io-width = <4>; 268 clock-frequency = <24000000>; 269 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 270 clock-names = "baudclk", "apb_pclk"; 271 pinctrl-names = "default"; 272 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 273 dmas = <&pdma 2>, <&pdma 3>; 274 #dma-cells = <2>; 275 }; 276 277 uart1: serial1@20064000 { 278 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 279 reg = <0x20064000 0x100>; 280 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 281 reg-shift = <2>; 282 reg-io-width = <4>; 283 clock-frequency = <24000000>; 284 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 285 clock-names = "baudclk", "apb_pclk"; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&uart1_xfer>; 288 dmas = <&pdma 4>, <&pdma 5>; 289 #dma-cells = <2>; 290 }; 291 292 uart2: serial2@20068000 { 293 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 294 reg = <0x20068000 0x100>; 295 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 296 reg-shift = <2>; 297 reg-io-width = <4>; 298 clock-frequency = <24000000>; 299 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 300 clock-names = "baudclk", "apb_pclk"; 301 pinctrl-names = "default"; 302 pinctrl-0 = <&uart2_xfer>; 303 dmas = <&pdma 6>, <&pdma 7>; 304 #dma-cells = <2>; 305 }; 306 307 saradc: saradc@2006c000 { 308 compatible = "rockchip,saradc"; 309 reg = <0x2006c000 0x100>; 310 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 311 #io-channel-cells = <1>; 312 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 313 clock-names = "saradc", "apb_pclk"; 314 resets = <&cru SRST_SARADC>; 315 reset-names = "saradc-apb"; 316 status = "disabled"; 317 }; 318 319 pwm0: pwm0@20050000 { 320 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 321 reg = <0x20050000 0x10>; 322 #pwm-cells = <3>; 323 pinctrl-names = "active"; 324 pinctrl-0 = <&pwm0_pin>; 325 clocks = <&cru PCLK_PWM>; 326 clock-names = "pwm"; 327 }; 328 329 pwm1: pwm1@20050010 { 330 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 331 reg = <0x20050010 0x10>; 332 #pwm-cells = <2>; 333 pinctrl-names = "active"; 334 pinctrl-0 = <&pwm1_pin>; 335 clocks = <&cru PCLK_PWM>; 336 clock-names = "pwm"; 337 }; 338 339 pwm2: pwm2@20050020 { 340 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 341 reg = <0x20050020 0x10>; 342 #pwm-cells = <2>; 343 pinctrl-names = "active"; 344 pinctrl-0 = <&pwm2_pin>; 345 clocks = <&cru PCLK_PWM>; 346 clock-names = "pwm"; 347 }; 348 349 pwm3: pwm3@20050030 { 350 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 351 reg = <0x20050030 0x10>; 352 #pwm-cells = <2>; 353 pinctrl-names = "active"; 354 pinctrl-0 = <&pwm3_pin>; 355 clocks = <&cru PCLK_PWM>; 356 clock-names = "pwm"; 357 }; 358 359 sram: sram@10080400 { 360 compatible = "rockchip,rk3128-smp-sram", "mmio-sram"; 361 reg = <0x10080400 0x1C00>; 362 map-exec; 363 map-cacheable; 364 }; 365 366 pmu: syscon@100a0000 { 367 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 368 reg = <0x100a0000 0x1000>; 369 #address-cells = <1>; 370 #size-cells = <1>; 371 }; 372 373 vop: vop@1010e000 { 374 compatible = "rockchip,rk3126-vop"; 375 reg = <0x1010e000 0x100>, <0x1010ec00 0x400>; 376 reg-names = "regs", "gamma_lut"; 377 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_VOP>, <&cru HCLK_LCDC0>; 379 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 380 status = "disabled"; 381 382 vop_out: port { 383 #address-cells = <1>; 384 #size-cells = <0>; 385 386 vop_out_lvds: endpoint@0 { 387 reg = <0>; 388 remote-endpoint = <&lvds_in_vop>; 389 }; 390 391 vop_out_dsi: endpoint@1 { 392 reg = <1>; 393 remote-endpoint = <&dsi_in_vop>; 394 }; 395 396 vop_out_rgb: endpoint@2 { 397 reg = <2>; 398 remote-endpoint = <&rgb_in_vop>; 399 }; 400 }; 401 }; 402 403 dsi: dsi@10110000 { 404 compatible = "rockchip,rk3128-mipi-dsi"; 405 reg = <0x10110000 0x4000>; 406 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&cru PCLK_MIPI>, <&cru HCLK_VIO_H2P>, <&video_phy>; 408 clock-names = "pclk", "h2p", "hs_clk"; 409 resets = <&cru SRST_VIO_MIPI_DSI>; 410 reset-names = "apb"; 411 phys = <&video_phy>; 412 phy-names = "mipi_dphy"; 413 rockchip,grf = <&grf>; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 status = "disabled"; 417 418 ports { 419 port { 420 dsi_in_vop: endpoint { 421 remote-endpoint = <&vop_out_dsi>; 422 }; 423 }; 424 }; 425 }; 426 427 display_subsystem: display-subsystem { 428 compatible = "rockchip,display-subsystem"; 429 ports = <&vop_out>; 430 431 route { 432 route_lvds: route-lvds { 433 logo,uboot = "logo.bmp"; 434 logo,kernel = "logo_kernel.bmp"; 435 logo,mode = "fullscreen"; 436 charge_logo,mode = "center"; 437 connect = <&vop_out_lvds>; 438 }; 439 440 route_dsi: route-dsi { 441 logo,uboot = "logo.bmp"; 442 logo,kernel = "logo_kernel.bmp"; 443 logo,mode = "fullscreen"; 444 charge_logo,mode = "center"; 445 connect = <&vop_out_dsi>; 446 }; 447 }; 448 }; 449 450 gic: interrupt-controller@10139000 { 451 compatible = "arm,gic-400"; 452 interrupt-controller; 453 #interrupt-cells = <3>; 454 #address-cells = <0>; 455 reg = <0x10139000 0x1000>, 456 <0x1013a000 0x1000>, 457 <0x1013c000 0x2000>, 458 <0x1013e000 0x2000>; 459 interrupts = <GIC_PPI 9 0xf04>; 460 }; 461 462 usb_otg: usb@10180000 { 463 compatible = "rockchip,rk3128-usb", "rockchip,rk3288-usb", 464 "snps,dwc2"; 465 reg = <0x10180000 0x40000>; 466 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 467 dr_mode = "otg"; 468 g-use-dma; 469 hnp-srp-disable; 470 phys = <&u2phy_otg>; 471 phy-names = "usb"; 472 status = "disabled"; 473 }; 474 475 usb_host_ehci: usb@101c0000 { 476 compatible = "generic-ehci"; 477 reg = <0x101c0000 0x20000>; 478 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 479 phys = <&u2phy_host>; 480 phy-names = "usb"; 481 status = "disabled"; 482 }; 483 484 usb_host_ohci: usb@101e0000 { 485 compatible = "generic-ohci"; 486 reg = <0x101e0000 0x20000>; 487 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 488 phys = <&u2phy_host>; 489 phy-names = "usb"; 490 status = "disabled"; 491 }; 492 493 sdmmc: dwmmc@10214000 { 494 compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc"; 495 reg = <0x10214000 0x4000>; 496 max-frequency = <150000000>; 497 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 499 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 500 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 501 fifo-depth = <0x100>; 502 pinctrl-names = "default"; 503 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 504 bus-width = <4>; 505 status = "disabled"; 506 }; 507 508 emmc: dwmmc@1021c000 { 509 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 510 reg = <0x1021c000 0x4000>; 511 max-frequency = <150000000>; 512 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 514 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 515 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 516 bus-width = <8>; 517 default-sample-phase = <158>; 518 num-slots = <1>; 519 fifo-depth = <0x100>; 520 pinctrl-names = "default"; 521 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 522 resets = <&cru SRST_EMMC>; 523 reset-names = "reset"; 524 status = "disabled"; 525 }; 526 527 video_phy: video-phy@20038000 { 528 compatible = "rockchip,rk3128-video-phy"; 529 reg = <0x20038000 0x4000>, <0x10110000 0x4000>; 530 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>, 531 <&cru PCLK_MIPI>; 532 clock-names = "ref", "pclk_phy", "pclk_host"; 533 #clock-cells = <0>; 534 resets = <&cru SRST_MIPIPHY_P>; 535 reset-names = "rst"; 536 #phy-cells = <0>; 537 status = "disabled"; 538 }; 539 540 i2c0: i2c0@20072000 { 541 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 542 reg = <0x20072000 0x1000>; 543 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 clock-names = "i2c"; 547 clocks = <&cru PCLK_I2C0>; 548 pinctrl-names = "default"; 549 pinctrl-0 = <&i2c0_xfer>; 550 }; 551 552 i2c1: i2c1@20056000 { 553 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 554 reg = <0x20056000 0x1000>; 555 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 clock-names = "i2c"; 559 clocks = <&cru PCLK_I2C1>; 560 pinctrl-names = "default"; 561 pinctrl-0 = <&i2c1_xfer>; 562 }; 563 564 i2c2: i2c2@2005a000 { 565 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 566 reg = <0x2005a000 0x1000>; 567 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 clock-names = "i2c"; 571 clocks = <&cru PCLK_I2C2>; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&i2c2_xfer>; 574 }; 575 576 i2c3: i2c3@2005e000 { 577 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 578 reg = <0x2005e000 0x1000>; 579 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 580 #address-cells = <1>; 581 #size-cells = <0>; 582 clock-names = "i2c"; 583 clocks = <&cru PCLK_I2C3>; 584 pinctrl-names = "default"; 585 pinctrl-0 = <&i2c3_xfer>; 586 }; 587 588 spi0: spi@20074000 { 589 compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi"; 590 reg = <0x20074000 0x1000>; 591 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 592 pinctrl-names = "default"; 593 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; 594 clock-names = "spiclk", "apb_pclk"; 595 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 596 dmas = <&pdma 8>, <&pdma 9>; 597 dma-names = "tx", "rx"; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 status = "disabled"; 601 }; 602 603 grf: syscon@20008000 { 604 compatible = "rockchip,rk3128-grf", "syscon"; 605 reg = <0x20008000 0x1000>; 606 #address-cells = <1>; 607 #size-cells = <1>; 608 609 lvds: lvds { 610 compatible = "rockchip,rk3126-lvds"; 611 phys = <&video_phy>; 612 phy-names = "phy"; 613 status = "disabled"; 614 615 ports { 616 #address-cells = <1>; 617 #size-cells = <0>; 618 619 port@0 { 620 reg = <0>; 621 622 lvds_in_vop: endpoint { 623 remote-endpoint = <&vop_out_lvds>; 624 }; 625 }; 626 }; 627 }; 628 629 rgb: rgb { 630 compatible = "rockchip,rk3128-rgb"; 631 phys = <&video_phy>; 632 phy-names = "phy"; 633 pinctrl-names = "default", "sleep"; 634 pinctrl-0 = <&lcdc_rgb_pins>; 635 pinctrl-1 = <&lcdc_sleep_pins>; 636 status = "disabled"; 637 638 ports { 639 #address-cells = <1>; 640 #size-cells = <0>; 641 642 port@0 { 643 reg = <0>; 644 645 rgb_in_vop: endpoint { 646 remote-endpoint = <&vop_out_rgb>; 647 }; 648 }; 649 }; 650 }; 651 652 u2phy: usb2-phy@17c { 653 compatible = "rockchip,rk3128-usb2phy"; 654 reg = <0x017c 0x0c>; 655 clocks = <&cru SCLK_OTGPHY0>; 656 clock-names = "phyclk"; 657 #clock-cells = <0>; 658 clock-output-names = "usb480m_phy"; 659 assigned-clocks = <&cru SCLK_USB480M>; 660 assigned-clock-parents = <&u2phy>; 661 status = "disabled"; 662 663 u2phy_otg: otg-port { 664 #phy-cells = <0>; 665 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 668 interrupt-names = "otg-bvalid", "otg-id", 669 "linestate"; 670 status = "disabled"; 671 }; 672 673 u2phy_host: host-port { 674 #phy-cells = <0>; 675 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 676 interrupt-names = "linestate"; 677 status = "disabled"; 678 }; 679 }; 680 }; 681 682 pinctrl: pinctrl@20008000 { 683 compatible = "rockchip,rk3128-pinctrl"; 684 reg = <0x20008000 0xA8>, 685 <0x200080A8 0x4C>, 686 <0x20008118 0x20>, 687 <0x20008100 0x04>; 688 reg-names = "base", "mux", "pull", "drv"; 689 rockchip,grf = <&grf>; 690 #address-cells = <1>; 691 #size-cells = <1>; 692 ranges; 693 694 gpio0: gpio0@2007c000 { 695 compatible = "rockchip,gpio-bank"; 696 reg = <0x2007c000 0x100>; 697 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&cru PCLK_GPIO0>; 699 gpio-controller; 700 #gpio-cells = <2>; 701 interrupt-controller; 702 #interrupt-cells = <2>; 703 }; 704 705 gpio1: gpio1@20080000 { 706 compatible = "rockchip,gpio-bank"; 707 reg = <0x20080000 0x100>; 708 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&cru PCLK_GPIO1>; 710 gpio-controller; 711 #gpio-cells = <2>; 712 interrupt-controller; 713 #interrupt-cells = <2>; 714 }; 715 716 gpio2: gpio2@20084000 { 717 compatible = "rockchip,gpio-bank"; 718 reg = <0x20084000 0x100>; 719 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&cru PCLK_GPIO2>; 721 gpio-controller; 722 #gpio-cells = <2>; 723 interrupt-controller; 724 #interrupt-cells = <2>; 725 }; 726 727 gpio3: gpio2@20088000 { 728 compatible = "rockchip,gpio-bank"; 729 reg = <0x20088000 0x100>; 730 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&cru PCLK_GPIO3>; 732 gpio-controller; 733 #gpio-cells = <2>; 734 interrupt-controller; 735 #interrupt-cells = <2>; 736 }; 737 738 pcfg_pull_default: pcfg_pull_default { 739 bias-pull-pin-default; 740 }; 741 742 pcfg_pull_none: pcfg-pull-none { 743 bias-disable; 744 }; 745 746 emmc { 747 emmc_clk: emmc-clk { 748 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 749 }; 750 751 emmc_cmd: emmc-cmd { 752 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; 753 }; 754 755 emmc_cmd1: emmc-cmd1 { 756 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; 757 }; 758 759 emmc_pwr: emmc-pwr { 760 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; 761 }; 762 763 emmc_bus1: emmc-bus1 { 764 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; 765 }; 766 767 emmc_bus4: emmc-bus4 { 768 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 769 <1 RK_PD1 2 &pcfg_pull_default>, 770 <1 RK_PD2 2 &pcfg_pull_default>, 771 <1 RK_PD3 2 &pcfg_pull_default>; 772 }; 773 774 emmc_bus8: emmc-bus8 { 775 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 776 <1 RK_PD1 2 &pcfg_pull_default>, 777 <1 RK_PD2 2 &pcfg_pull_default>, 778 <1 RK_PD3 2 &pcfg_pull_default>, 779 <1 RK_PD4 2 &pcfg_pull_default>, 780 <1 RK_PD5 2 &pcfg_pull_default>, 781 <1 RK_PD6 2 &pcfg_pull_default>, 782 <1 RK_PD7 2 &pcfg_pull_default>; 783 }; 784 }; 785 786 i2c0 { 787 i2c0_xfer: i2c0-xfer { 788 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 789 <0 RK_PA1 1 &pcfg_pull_none>; 790 }; 791 }; 792 793 i2c1 { 794 i2c1_xfer: i2c1-xfer { 795 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 796 <0 RK_PA3 1 &pcfg_pull_none>; 797 }; 798 }; 799 800 i2c2 { 801 i2c2_xfer: i2c2-xfer { 802 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, 803 <2 RK_PC5 3 &pcfg_pull_none>; 804 }; 805 }; 806 807 i2c3 { 808 i2c3_xfer: i2c3-xfer { 809 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 810 <0 RK_PA7 1 &pcfg_pull_none>; 811 }; 812 }; 813 814 lcdc { 815 lcdc_rgb_pins: lcdc-rgb-pins { 816 rockchip,pins = 817 <2 RK_PB0 1 &pcfg_pull_none>, /* LCDC_DCLK */ 818 <2 RK_PB1 1 &pcfg_pull_none>, /* LCDC_HSYNC */ 819 <2 RK_PB2 1 &pcfg_pull_none>, /* LCDC_VSYNC */ 820 <2 RK_PB3 1 &pcfg_pull_none>, /* LCDC_DEN */ 821 <2 RK_PB4 1 &pcfg_pull_none>, /* LCDC_DATA10 */ 822 <2 RK_PB5 1 &pcfg_pull_none>, /* LCDC_DATA11 */ 823 <2 RK_PB6 1 &pcfg_pull_none>, /* LCDC_DATA12 */ 824 <2 RK_PB7 1 &pcfg_pull_none>, /* LCDC_DATA13 */ 825 <2 RK_PC0 1 &pcfg_pull_none>, /* LCDC_DATA14 */ 826 <2 RK_PC1 1 &pcfg_pull_none>, /* LCDC_DATA15 */ 827 <2 RK_PC2 1 &pcfg_pull_none>, /* LCDC_DATA16 */ 828 <2 RK_PC3 1 &pcfg_pull_none>, /* LCDC_DATA17 */ 829 <2 RK_PC4 1 &pcfg_pull_none>, /* LCDC_DATA18 */ 830 <2 RK_PC5 1 &pcfg_pull_none>, /* LCDC_DATA19 */ 831 <2 RK_PC6 1 &pcfg_pull_none>, /* LCDC_DATA20 */ 832 <2 RK_PC7 1 &pcfg_pull_none>, /* LCDC_DATA21 */ 833 <2 RK_PD0 1 &pcfg_pull_none>, /* LCDC_DATA22 */ 834 <2 RK_PD1 1 &pcfg_pull_none>; /* LCDC_DATA23 */ 835 }; 836 837 lcdc_sleep_pins: lcdc-sleep-pins { 838 rockchip,pins = 839 <2 RK_PB0 0 &pcfg_pull_none>, /* LCDC_DCLK */ 840 <2 RK_PB1 0 &pcfg_pull_none>, /* LCDC_HSYNC */ 841 <2 RK_PB2 0 &pcfg_pull_none>, /* LCDC_VSYNC */ 842 <2 RK_PB3 0 &pcfg_pull_none>, /* LCDC_DEN */ 843 <2 RK_PB4 0 &pcfg_pull_none>, /* LCDC_DATA10 */ 844 <2 RK_PB5 0 &pcfg_pull_none>, /* LCDC_DATA11 */ 845 <2 RK_PB6 0 &pcfg_pull_none>, /* LCDC_DATA12 */ 846 <2 RK_PB7 0 &pcfg_pull_none>, /* LCDC_DATA13 */ 847 <2 RK_PC0 0 &pcfg_pull_none>, /* LCDC_DATA14 */ 848 <2 RK_PC1 0 &pcfg_pull_none>, /* LCDC_DATA15 */ 849 <2 RK_PC2 0 &pcfg_pull_none>, /* LCDC_DATA16 */ 850 <2 RK_PC3 0 &pcfg_pull_none>, /* LCDC_DATA17 */ 851 <2 RK_PC4 0 &pcfg_pull_none>, /* LCDC_DATA18 */ 852 <2 RK_PC5 0 &pcfg_pull_none>, /* LCDC_DATA19 */ 853 <2 RK_PC6 0 &pcfg_pull_none>, /* LCDC_DATA20 */ 854 <2 RK_PC7 0 &pcfg_pull_none>, /* LCDC_DATA21 */ 855 <2 RK_PD0 0 &pcfg_pull_none>, /* LCDC_DATA22 */ 856 <2 RK_PD1 0 &pcfg_pull_none>; /* LCDC_DATA23 */ 857 }; 858 }; 859 860 uart0 { 861 uart0_xfer: uart0-xfer { 862 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, 863 <2 RK_PD3 2 &pcfg_pull_none>; 864 }; 865 866 uart0_cts: uart0-cts { 867 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; 868 }; 869 870 uart0_rts: uart0-rts { 871 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; 872 }; 873 }; 874 875 uart1 { 876 uart1_xfer: uart1-xfer { 877 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 878 <1 RK_PB2 2 &pcfg_pull_default>; 879 }; 880 881 uart1_cts: uart1-cts { 882 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 883 }; 884 885 uart1_rts: uart1-rts { 886 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 887 }; 888 }; 889 890 uart2 { 891 uart2_xfer: uart2-xfer { 892 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 893 <1 RK_PC3 2 &pcfg_pull_none>; 894 }; 895 896 uart2_cts: uart2-cts { 897 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 898 }; 899 900 uart2_rts: uart2-rts { 901 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 902 }; 903 }; 904 905 sdmmc { 906 sdmmc_clk: sdmmc-clk { 907 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 908 }; 909 910 sdmmc_cmd: sdmmc-cmd { 911 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 912 }; 913 914 sdmmc_wp: sdmmc-wp { 915 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 916 }; 917 918 sdmmc_pwren: sdmmc-pwren { 919 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>; 920 }; 921 922 sdmmc_bus4: sdmmc-bus4 { 923 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 924 <1 RK_PC3 1 &pcfg_pull_default>, 925 <1 RK_PC4 1 &pcfg_pull_default>, 926 <1 RK_PC5 1 &pcfg_pull_default>; 927 }; 928 }; 929 930 sdio { 931 sdio_clk: sdio-clk { 932 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; 933 }; 934 935 sdio_cmd: sdio-cmd { 936 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; 937 }; 938 939 sdio_pwren: sdio-pwren { 940 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; 941 }; 942 943 sdio_bus4: sdio-bus4 { 944 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, 945 <1 RK_PA2 2 &pcfg_pull_default>, 946 <1 RK_PA4 2 &pcfg_pull_default>, 947 <1 RK_PA5 2 &pcfg_pull_default>; 948 }; 949 }; 950 951 hdmi { 952 hdmii2c_xfer: hdmii2c-xfer { 953 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 954 <0 RK_PA7 2 &pcfg_pull_none>; 955 }; 956 }; 957 958 i2s { 959 i2s_bus: i2s-bus { 960 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 961 <0 RK_PB1 1 &pcfg_pull_none>, 962 <0 RK_PB3 1 &pcfg_pull_none>, 963 <0 RK_PB4 1 &pcfg_pull_none>, 964 <0 RK_PB5 1 &pcfg_pull_none>, 965 <0 RK_PB6 1 &pcfg_pull_none>; 966 }; 967 968 i2s1_bus: i2s1-bus { 969 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, 970 <1 RK_PA1 1 &pcfg_pull_none>, 971 <1 RK_PA2 1 &pcfg_pull_none>, 972 <1 RK_PA3 1 &pcfg_pull_none>, 973 <1 RK_PA4 1 &pcfg_pull_none>, 974 <1 RK_PA5 1 &pcfg_pull_none>; 975 }; 976 }; 977 978 pwm0 { 979 pwm0_pin: pwm0-pin { 980 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; 981 }; 982 }; 983 984 pwm1 { 985 pwm1_pin: pwm1-pin { 986 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 987 }; 988 }; 989 990 pwm2 { 991 pwm2_pin: pwm2-pin { 992 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 993 }; 994 }; 995 996 pwm3 { 997 pwm3_pin: pwm3-pin { 998 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; 999 }; 1000 }; 1001 1002 gmac { 1003 rgmii_pins: rgmii-pins { 1004 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 1005 <2 RK_PB1 3 &pcfg_pull_default>, 1006 <2 RK_PB3 3 &pcfg_pull_default>, 1007 <2 RK_PB4 3 &pcfg_pull_default>, 1008 <2 RK_PB5 3 &pcfg_pull_default>, 1009 <2 RK_PB6 3 &pcfg_pull_default>, 1010 <2 RK_PC0 3 &pcfg_pull_default>, 1011 <2 RK_PC1 3 &pcfg_pull_default>, 1012 <2 RK_PC2 3 &pcfg_pull_default>, 1013 <2 RK_PC3 3 &pcfg_pull_default>, 1014 <2 RK_PD1 3 &pcfg_pull_default>, 1015 <2 RK_PC4 4 &pcfg_pull_default>, 1016 <2 RK_PC5 4 &pcfg_pull_default>, 1017 <2 RK_PC6 4 &pcfg_pull_default>, 1018 <2 RK_PC7 4 &pcfg_pull_default>; 1019 }; 1020 1021 rmii_pins: rmii-pins { 1022 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 1023 <2 RK_PB4 3 &pcfg_pull_default>, 1024 <2 RK_PB5 3 &pcfg_pull_default>, 1025 <2 RK_PB6 3 &pcfg_pull_default>, 1026 <2 RK_PB7 3 &pcfg_pull_default>, 1027 <2 RK_PC0 3 &pcfg_pull_default>, 1028 <2 RK_PC1 3 &pcfg_pull_default>, 1029 <2 RK_PC3 3 &pcfg_pull_default>, 1030 <2 RK_PC4 3 &pcfg_pull_default>, 1031 <2 RK_PD1 3 &pcfg_pull_default>; 1032 }; 1033 }; 1034 1035 spdif { 1036 spdif_tx: spdif-tx { 1037 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 1038 }; 1039 }; 1040 1041 spi { 1042 spi0_clk: spi0-clk { 1043 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; 1044 }; 1045 1046 spi0_cs0: spi0-cs0 { 1047 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; 1048 }; 1049 1050 spi0_tx: spi0-tx { 1051 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; 1052 }; 1053 1054 spi0_rx: spi0-rx { 1055 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; 1056 }; 1057 1058 spi0_cs1: spi0-cs1 { 1059 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; 1060 }; 1061 1062 spi1_clk: spi1-clk { 1063 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 1064 }; 1065 1066 spi1_cs0: spi1-cs0 { 1067 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 1068 }; 1069 1070 spi1_tx: spi1-tx { 1071 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 1072 }; 1073 1074 spi1_rx: spi1-rx { 1075 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 1076 }; 1077 1078 spi1_cs1: spi1-cs1 { 1079 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 1080 }; 1081 1082 spi2_clk: spi2-clk { 1083 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; 1084 }; 1085 1086 spi2_cs0: spi2-cs0 { 1087 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; 1088 }; 1089 1090 spi2_tx: spi2-tx { 1091 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; 1092 }; 1093 1094 spi2_rx: spi2-rx { 1095 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; 1096 }; 1097 }; 1098 }; 1099}; 1100
