1 /* 2 * Copyright (C) 2022 Rockchip Electronics Co., Ltd. 3 * Authors: 4 * Cerf Yu <cerf.yu@rock-chips.com> 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 */ 18 19 #ifndef _RGA_DRIVER_IOCTL_H_ 20 #define _RGA_DRIVER_IOCTL_H_ 21 22 #include <asm/ioctl.h> 23 #include <stdint.h> 24 25 /* compatible */ 26 #include "rga2_driver.h" 27 28 #ifdef __cplusplus 29 extern "C" 30 { 31 #endif 32 33 /* Use 'r' as magic number */ 34 #define RGA_IOC_MAGIC 'r' 35 #define RGA_IOW(nr, type) _IOW(RGA_IOC_MAGIC, nr, type) 36 #define RGA_IOR(nr, type) _IOR(RGA_IOC_MAGIC, nr, type) 37 #define RGA_IOWR(nr, type) _IOWR(RGA_IOC_MAGIC, nr, type) 38 39 #define RGA_IOC_GET_DRVIER_VERSION RGA_IOR(0x1, struct rga_version_t) 40 #define RGA_IOC_GET_HW_VERSION RGA_IOR(0x2, struct rga_hw_versions_t) 41 #define RGA_IOC_IMPORT_BUFFER RGA_IOWR(0x3, struct rga_buffer_pool) 42 #define RGA_IOC_RELEASE_BUFFER RGA_IOW(0x4, struct rga_buffer_pool) 43 #define RGA_IOC_REQUEST_CREATE RGA_IOR(0x5, uint32_t) 44 #define RGA_IOC_REQUEST_SUBMIT RGA_IOWR(0x6, struct rga_user_request) 45 #define RGA_IOC_REQUEST_CONFIG RGA_IOWR(0x7, struct rga_user_request) 46 #define RGA_IOC_REQUEST_CANCEL RGA_IOWR(0x8, uint32_t) 47 48 #define RGA_BLIT_SYNC 0x5017 49 #define RGA_BLIT_ASYNC 0x5018 50 #define RGA_FLUSH 0x5019 51 #define RGA_GET_RESULT 0x501a 52 #define RGA_GET_VERSION 0x501b 53 54 #define RGA2_BLIT_SYNC 0x6017 55 #define RGA2_BLIT_ASYNC 0x6018 56 #define RGA2_FLUSH 0x6019 57 #define RGA2_GET_RESULT 0x601a 58 #define RGA2_GET_VERSION 0x601b 59 60 #define RGA_START_CONFIG RGA_IOC_REQUEST_CREATE 61 #define RGA_END_CONFIG RGA_IOC_REQUEST_SUBMIT 62 #define RGA_CMD_CONFIG RGA_IOC_REQUEST_CONFIG 63 #define RGA_CANCEL_CONFIG RGA_IOC_REQUEST_CANCEL 64 65 #define RGA_REG_CTRL_LEN 0x8 /* 8 */ 66 #define RGA_REG_CMD_LEN 0x1c /* 28 */ 67 #define RGA_CMD_BUF_SIZE 0x700 /* 16*28*4 */ 68 69 #define RGA_TASK_NUM_MAX 50 70 71 #define RGA_SCHED_PRIORITY_DEFAULT 0 72 #define RGA_SCHED_PRIORITY_MAX 6 73 74 enum rga_memory_type { 75 RGA_DMA_BUFFER = 0, 76 RGA_VIRTUAL_ADDRESS, 77 RGA_PHYSICAL_ADDRESS 78 }; 79 80 /* RGA process mode enum */ 81 enum { 82 bitblt_mode = 0x0, 83 color_palette_mode = 0x1, 84 color_fill_mode = 0x2, 85 line_point_drawing_mode = 0x3, 86 blur_sharp_filter_mode = 0x4, 87 pre_scaling_mode = 0x5, 88 update_palette_table_mode = 0x6, 89 update_patten_buff_mode = 0x7, 90 }; 91 92 /* unused */ 93 enum { 94 rop_enable_mask = 0x2, 95 dither_enable_mask = 0x8, 96 fading_enable_mask = 0x10, 97 PD_enbale_mask = 0x20, 98 }; 99 100 enum { 101 color_palette_mode0 = 0x0, /* 1K */ 102 color_palette_mode1 = 0x1, /* 2K */ 103 color_palette_mode2 = 0x2, /* 4K */ 104 color_palette_mode3 = 0x3, /* 8K */ 105 }; 106 107 enum { 108 BB_BYPASS = 0x0, /* no rotate */ 109 BB_ROTATE = 0x1, /* rotate */ 110 BB_X_MIRROR = 0x2, /* x_mirror */ 111 BB_Y_MIRROR = 0x3 /* y_mirror */ 112 }; 113 114 enum { 115 nearby = 0x0, /* no rotate */ 116 bilinear = 0x1, /* rotate */ 117 bicubic = 0x2, /* x_mirror */ 118 }; 119 120 /* RGA rotate mode */ 121 enum { 122 rotate_mode0 = 0x0, /* no rotate */ 123 rotate_mode1 = 0x1, /* rotate */ 124 rotate_mode2 = 0x2, /* x_mirror */ 125 rotate_mode3 = 0x3, /* y_mirror */ 126 }; 127 128 typedef struct rga_img_info_t { 129 uint64_t yrgb_addr; /* yrgb mem addr */ 130 uint64_t uv_addr; /* cb/cr mem addr */ 131 uint64_t v_addr; /* cr mem addr */ 132 133 uint32_t format; //definition by RK_FORMAT 134 uint16_t act_w; 135 uint16_t act_h; 136 uint16_t x_offset; 137 uint16_t y_offset; 138 139 uint16_t vir_w; 140 uint16_t vir_h; 141 142 uint16_t endian_mode; //for BPP 143 uint16_t alpha_swap; 144 145 //used by RGA3 146 uint16_t rotate_mode; 147 uint16_t rd_mode; 148 149 uint16_t is_10b_compact; 150 uint16_t is_10b_endian; 151 152 uint16_t enable; 153 } rga_img_info_t; 154 155 typedef struct POINT { 156 uint16_t x; 157 uint16_t y; 158 } POINT; 159 160 typedef struct RECT { 161 uint16_t xmin; 162 uint16_t xmax; // width - 1 163 uint16_t ymin; 164 uint16_t ymax; // height - 1 165 } RECT; 166 167 typedef struct MMU { 168 uint8_t mmu_en; 169 uint64_t base_addr; 170 uint32_t mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/ 171 } MMU; 172 173 typedef struct COLOR_FILL { 174 int16_t gr_x_a; 175 int16_t gr_y_a; 176 int16_t gr_x_b; 177 int16_t gr_y_b; 178 int16_t gr_x_g; 179 int16_t gr_y_g; 180 int16_t gr_x_r; 181 int16_t gr_y_r; 182 //u8 cp_gr_saturation; 183 } COLOR_FILL; 184 185 typedef struct FADING { 186 uint8_t b; 187 uint8_t g; 188 uint8_t r; 189 uint8_t res; 190 } FADING; 191 192 typedef struct line_draw_t { 193 POINT start_point; /* LineDraw_start_point */ 194 POINT end_point; /* LineDraw_end_point */ 195 uint32_t color; /* LineDraw_color */ 196 uint32_t flag; /* (enum) LineDrawing mode sel */ 197 uint32_t line_width; /* range 1~16 */ 198 } line_draw_t; 199 200 /* color space convert coefficient. */ 201 typedef struct csc_coe_t { 202 int16_t r_v; 203 int16_t g_y; 204 int16_t b_u; 205 int32_t off; 206 } csc_coe_t; 207 208 typedef struct full_csc_t { 209 uint8_t flag; 210 csc_coe_t coe_y; 211 csc_coe_t coe_u; 212 csc_coe_t coe_v; 213 } full_csc_t; 214 215 typedef struct rga_mosaic_info_ioctl { 216 uint8_t enable; 217 uint8_t mode; 218 } rga_mosaic_info_t; 219 220 typedef struct rga_pre_intr_info_ioctl { 221 uint8_t enable; 222 223 uint8_t read_intr_en; 224 uint8_t write_intr_en; 225 uint8_t read_hold_en; 226 uint32_t read_threshold; 227 uint32_t write_start; 228 uint32_t write_step; 229 } rga_pre_intr_info_t; 230 231 /* MAX(min, (max - channel_value)) */ 232 typedef struct rga_osd_invert_factor_ioctl { 233 uint8_t alpha_max; 234 uint8_t alpha_min; 235 uint8_t yg_max; 236 uint8_t yg_min; 237 uint8_t crb_max; 238 uint8_t crb_min; 239 } rga_osd_invert_factor_t; 240 241 typedef struct rga_color_ioctl { 242 union { 243 struct { 244 uint8_t red; 245 uint8_t green; 246 uint8_t blue; 247 uint8_t alpha; 248 }; 249 uint32_t value; 250 }; 251 } rga_color_t; 252 253 typedef struct rga_osd_bpp2_ioctl { 254 uint8_t ac_swap; // ac swap flag 255 // 0: CA 256 // 1: AC 257 uint8_t endian_swap; // rgba2bpp endian swap 258 // 0: Big endian 259 // 1: Little endian 260 rga_color_t color0; 261 rga_color_t color1; 262 } rga_osd_bpp2_t; 263 264 typedef struct rga_osd_mode_ctrl_ioctal { 265 uint8_t mode; // OSD cal mode: 266 // 0b'1: statistics mode 267 // 1b'1: auto inversion overlap mode 268 uint8_t direction_mode; // horizontal or vertical 269 // 0: horizontal 270 // 1: vertical 271 uint8_t width_mode; // using @fix_width or LUT width 272 // 0: fix width 273 // 1: LUT width 274 uint16_t block_fix_width; // OSD block fixed width 275 // real width = (fix_width + 1) * 2 276 uint8_t block_num; // OSD block num 277 uint16_t flags_index; // auto invert flags index 278 279 /* invertion config */ 280 uint8_t color_mode; // selete color 281 // 0: src1 color 282 // 1: config data color 283 uint8_t invert_flags_mode; // invert flag selete 284 // 0: use RAM flag 285 // 1: usr last result 286 uint8_t default_color_sel; // default color mode 287 // 0: default is bright 288 // 1: default is dark 289 uint8_t invert_enable; // invert channel enable 290 // 1 << 0: aplha enable 291 // 1 << 1: Y/G disable 292 // 1 << 2: C/RB disable 293 uint8_t invert_mode; // invert cal mode 294 // 0: normal(max-data) 295 // 1: swap 296 uint8_t invert_thresh; // if luma > thresh, osd_flag to be 1 297 uint8_t unfix_index; // OSD width config index 298 } rga_osd_mode_ctrl_t; 299 300 typedef struct rga_osd_info_ioctl { 301 uint8_t enable; 302 303 rga_osd_mode_ctrl_t mode_ctrl; 304 rga_osd_invert_factor_t cal_factor; 305 rga_osd_bpp2_t bpp2_info; 306 307 union { 308 struct { 309 uint32_t last_flags1; 310 uint32_t last_flags0; 311 }; 312 uint64_t last_flags; 313 }; 314 315 union { 316 struct { 317 uint32_t cur_flags1; 318 uint32_t cur_flags0; 319 }; 320 uint64_t cur_flags; 321 }; 322 } rga_osd_info_t; 323 324 #define RGA_VERSION_SIZE 16 325 #define RGA_HW_SIZE 5 326 327 struct rga_version_t { 328 uint32_t major; 329 uint32_t minor; 330 uint32_t revision; 331 uint8_t str[RGA_VERSION_SIZE]; 332 }; 333 334 struct rga_hw_versions_t { 335 struct rga_version_t version[RGA_HW_SIZE]; 336 uint32_t size; 337 }; 338 339 struct rga_memory_parm { 340 uint32_t width; 341 uint32_t height; 342 uint32_t format; 343 344 uint32_t size; 345 }; 346 347 struct rga_external_buffer { 348 uint64_t memory; 349 uint32_t type; 350 351 uint32_t handle; 352 struct rga_memory_parm memory_info; 353 354 uint8_t reserve[252]; 355 }; 356 357 struct rga_buffer_pool { 358 uint64_t buffers; 359 uint32_t size; 360 }; 361 362 struct rga_req { 363 uint8_t render_mode; /* (enum) process mode sel */ 364 365 rga_img_info_t src; /* src image info */ 366 rga_img_info_t dst; /* dst image info */ 367 rga_img_info_t pat; /* patten image info */ 368 369 uint64_t rop_mask_addr; /* rop4 mask addr */ 370 uint64_t LUT_addr; /* LUT addr */ 371 372 RECT clip; /* dst clip window default value is dst_vir */ 373 /* value from [0, w-1] / [0, h-1]*/ 374 375 int32_t sina; /* dst angle default value 0 16.16 scan from table */ 376 int32_t cosa; /* dst angle default value 0 16.16 scan from table */ 377 378 uint16_t alpha_rop_flag; /* alpha rop process flag */ 379 /* ([0] = 1 alpha_rop_enable) */ 380 /* ([1] = 1 rop enable) */ 381 /* ([2] = 1 fading_enable) */ 382 /* ([3] = 1 PD_enable) */ 383 /* ([4] = 1 alpha cal_mode_sel) */ 384 /* ([5] = 1 dither_enable) */ 385 /* ([6] = 1 gradient fill mode sel) */ 386 /* ([7] = 1 AA_enable) */ 387 /* ([8] = 1 nn_quantize) */ 388 /* ([9] = 1 Real color mode) */ 389 390 uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */ 391 392 uint32_t color_key_max; /* color key max */ 393 uint32_t color_key_min; /* color key min */ 394 395 uint32_t fg_color; /* foreground color */ 396 uint32_t bg_color; /* background color */ 397 398 COLOR_FILL gr_color; /* color fill use gradient */ 399 400 line_draw_t line_draw_info; 401 402 FADING fading; 403 404 uint8_t PD_mode; /* porter duff alpha mode sel */ 405 406 uint8_t alpha_global_value; /* global alpha value */ 407 408 uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/ 409 410 uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/ 411 412 uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/ 413 414 uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ 415 416 uint8_t endian_mode; /* 0/big endian 1/little endian*/ 417 418 uint8_t rotate_mode; /* (enum) rotate mode */ 419 /* 0x0, no rotate */ 420 /* 0x1, rotate */ 421 /* 0x2, x_mirror */ 422 /* 0x3, y_mirror */ 423 424 uint8_t color_fill_mode; /* 0 solid color / 1 patten color */ 425 426 MMU mmu_info; /* mmu information */ 427 428 uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */ 429 /* ([2~3] rop mode) */ 430 /* ([4] zero mode en) */ 431 /* ([5] dst alpha mode) (RGA1) */ 432 433 uint8_t src_trans_mode; 434 435 uint8_t dither_mode; 436 437 full_csc_t full_csc; /* full color space convert */ 438 439 int32_t in_fence_fd; 440 uint8_t core; 441 uint8_t priority; 442 int32_t out_fence_fd; 443 444 uint8_t handle_flag; 445 446 /* RGA2 1106 add */ 447 rga_mosaic_info_t mosaic_info; 448 449 uint8_t uvhds_mode; 450 uint8_t uvvds_mode; 451 452 rga_osd_info_t osd_info; 453 454 rga_pre_intr_info_t pre_intr_info; 455 456 uint8_t reservr[59]; 457 }; 458 459 struct rga_user_request { 460 uint64_t task_ptr; 461 uint32_t task_num; 462 uint32_t id; 463 uint32_t sync_mode; 464 uint32_t release_fence_fd; 465 466 uint32_t mpi_config_flags; 467 468 uint32_t acquire_fence_fd; 469 470 uint8_t reservr[120]; 471 }; 472 473 #ifdef __cplusplus 474 } 475 #endif 476 477 #endif /* _RGA_DRIVER_IOCTL_H_ */ 478