1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright 2017-2019 NXP 4 */ 5 6 #ifndef __IMX8M_H__ 7 #define __IMX8M_H__ 8 9 #include <registers/imx8m-crm.h> 10 11 #define IOMUXC_GPR_BASE 0x30340000 12 #define IOMUXC_SIZE 0x10000 13 #define GICD_BASE 0x38800000 14 #define GICR_BASE 0x38880000 15 #define UART1_BASE 0x30860000 16 #define UART2_BASE 0x30890000 17 #define UART3_BASE 0x30880000 18 #define UART4_BASE 0x30A60000 19 #define TZASC_BASE 0x32F80000 20 #define TZASC_SIZE 0x10000 21 #define CAAM_BASE 0x30900000 22 #define CAAM_SIZE 0x40000 23 #define CCM_BASE 0x30380000 24 #define CCM_SIZE 0x10000 25 #define ANATOP_BASE 0x30360000 26 #define IOMUXC_BASE 0x30330000 27 #define OCOTP_BASE 0x30350000 28 #define OCOTP_SIZE 0x10000 29 #define SNVS_BASE 0x30370000 30 #define SNVS_SIZE 0x10000 31 #define SECMEM_BASE 0x00100000 32 #define SECMEM_SIZE 0x8000 33 34 #ifdef CFG_MX8MQ 35 #define DIGPROG_OFFSET 0x06c 36 #define OCOTP_SW_INFO_B1 0x40 37 #define OCOTP_SW_MAGIC_B1 0xFF0055AA 38 #endif 39 #if defined(CFG_MX8MM) || defined(CFG_MX8MN) || defined(CFG_MX8MP) 40 #define DIGPROG_OFFSET 0x800 41 #endif 42 43 #if defined(CFG_MX8MM) || defined(CFG_MX8MQ) || defined(CFG_MX8MN) 44 #define I2C1_BASE 0x30a20000 45 #define I2C2_BASE 0x30a30000 46 #define I2C3_BASE 0x30a40000 47 #define I2C4_BASE 0x30a50000 48 49 #define IOMUXC_I2C1_SCL_CFG_OFF 0x47C 50 #define IOMUXC_I2C1_SDA_CFG_OFF 0x480 51 #define IOMUXC_I2C1_SCL_MUX_OFF 0x214 52 #define IOMUXC_I2C1_SDA_MUX_OFF 0x218 53 #endif 54 55 #if defined(CFG_MX8MP) 56 #define I2C1_BASE 0x30a20000 57 #define I2C2_BASE 0x30a30000 58 #define I2C3_BASE 0x30a40000 59 #define I2C4_BASE 0x30a50000 60 #define I2C5_BASE 0x30ad0000 61 #define I2C6_BASE 0x30ae0000 62 63 #define IOMUXC_I2C1_SCL_CFG_OFF 0x460 64 #define IOMUXC_I2C1_SDA_CFG_OFF 0x464 65 #define IOMUXC_I2C1_SCL_MUX_OFF 0x200 66 #define IOMUXC_I2C1_SDA_MUX_OFF 0x204 67 #endif 68 69 #define IOMUXC_GPR_GPR10_OFFSET 0x28 70 71 #endif /* __IMX8M_H__ */ 72