1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2011-2013 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regTOP.h 98 // Description: TSP Miu/Clk Gating Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_TOP_H_ 103 #define _REG_TOP_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 // MMFI Multi Media File In 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 #define TSP_MIU_SEL_BITS_LEN 2 137 138 //------------------------------------------------------------------------------------------------- 139 // Harware Capability 140 //------------------------------------------------------------------------------------------------- 141 142 143 //------------------------------------------------------------------------------------------------- 144 // Type and Structure 145 //------------------------------------------------------------------------------------------------- 146 147 typedef struct _REG_TOP_ProtectCtrl 148 { 149 REG32 L_BND; 150 REG32 U_BND; 151 #define REG_TOP_ProtectCtrl_BND_MASK 0x0FFFFFFF 152 #define REG_TOP_ProtectCtrl_ChkEn 0x80000000 153 } REG_TOP_ProtectCtrl; 154 155 typedef struct _REG_TOP_Ctrl // TOP (Bank:0x1703) 156 { 157 REG16 CFG_TOP_00; 158 #define CFG_TOP_00_REG_MIU_MERGE_ABT_EN 0x0001 159 160 REG16 CFG_TOP_01; 161 #define CFG_TOP_01_REG_MIU_RR_PRI_ABT_EN 0x0001 162 163 REG16 CFG_TOP_02; 164 #define CFG_TOP_02_REG_DIS_MIU_RQ_ABT 0x0001 165 166 REG16 CFG_TOP_03; 167 #define CFG_TOP_03_REG_RLAST_MASK_ABT_EN 0x0001 168 169 REG16 CFG_TOP_04; 170 #define CFG_TOP_04_REG_SEL_ABT_STATUS_NUM_MASK 0x000F 171 #define CFG_TOP_04_REG_SEL_ABT_STATUS_NUM_SHIFT 0 172 #define CFG_TOP_04_REG_ABT_STATUS_MASK 0x03F0 173 #define CFG_TOP_04_REG_ABT_STATUS_SHIFT 4 174 175 REG32 CFG_TOP_05_06; // PVR 1~10 176 #define CFG_TOP_05_06_REG_MIU_SEL_PVR_MASK 0x00000003 177 #define CFG_TOP_05_06_REG_MIU_SEL_PVR_SHIFT 0 178 179 REG16 CFG_TOP_07; 180 #define CFG_TOP_07_REG_MIU_SEL_FIQ_MASK 0x0003 181 #define CFG_TOP_07_REG_MIU_SEL_FIQ_SHIFT 0 182 183 REG16 CFG_TOP_08; 184 #define CFG_TOP_08_REG_MIU_SEL_FILEIN_MASK 0x0003 185 #define CFG_TOP_08_REG_MIU_SEL_FILEIN_SHIFT 0 186 187 REG16 CFG_TOP_09; 188 #define CFG_TOP_09_REG_MIU_SEL_VQ_MASK 0x0003 189 #define CFG_TOP_09_REG_MIU_SEL_VQ_SHIFT 0 190 #define CFG_TOP_09_REG_MIU_SEL_SEC_MASK 0x000C 191 #define CFG_TOP_09_REG_MIU_SEL_SEC_SHIFT 2 192 #define CFG_TOP_09_REG_MIU_SEL_ORZ_MASK 0x0030 193 #define CFG_TOP_09_REG_MIU_SEL_ORZ_SHIFT 4 194 #define CFG_TOP_09_REG_MIU_SEL_MMFI_MASK 0x00C0 //MMFI 0 ~ 1 195 #define CFG_TOP_09_REG_MIU_SEL_MMFI_SHIFT 6 196 #define CFG_TOP_09_REG_MIU_SEL_FIQ_MUX_MASK 0x0C00 //FIQ_MUX 0 ~ 2 197 #define CFG_TOP_09_REG_MIU_SEL_FIQ_MUX_SHIFT 10 198 199 REG16 CFG_TOP_0A; 200 #define CFG_TOP_0A_REG_FORCE_PRI_ABT_EN 0x0001 201 202 REG16 CFG_TOP_0B; 203 #define CFG_TOP_0B_REG_RRB_PLUS_PRI_EN_ABT 0x0001 204 205 REG16 CFG_TOP_0C; 206 #define CFG_TOP_0C_REG_MIU_LAT_CYCLE_CNT_EN 0x0001 207 #define CFG_TOP_0C_REG_MIU_LAT_CYCLE_CNT_CLR 0x0002 208 #define CFG_TOP_0C_REG_MIU_LAT_LEVEL_EVER_EN 0x0004 209 #define CFG_TOP_0C_REG_MIU_LAT_LEVEL_EVER_CLR 0x0008 210 #define CFG_TOP_0C_REG_MIU_LAT_LEVEL_EVER_ABT_SEL_MASK 0x00F0 211 #define CFG_TOP_0C_REG_MIU_LAT_LEVEL_EVER_ABT_SEL_SHIFT 4 212 213 REG32 CFG_TOP_0D_0E; // reg_miu_lat_level_ever 214 #define CFG_TOP_REG_MIU_LAT_THOLD_A_ABT_MASK 0x0000000F 215 #define CFG_TOP_REG_MIU_LAT_THOLD_A_ABT_SHIFT 0 216 #define CFG_TOP_REG_MIU_LAT_THOLD_B_ABT_MASK 0x000000F0 217 #define CFG_TOP_REG_MIU_LAT_THOLD_B_ABT_SHIFT 4 218 #define CFG_TOP_REG_MIU_LAT_THOLD_C_ABT_MASK 0x00000F00 219 #define CFG_TOP_REG_MIU_LAT_THOLD_C_ABT_SHIFT 8 220 #define CFG_TOP_REG_MIU_LAT_THOLD_D_ABT_MASK 0x0000F000 221 #define CFG_TOP_REG_MIU_LAT_THOLD_D_ABT_SHIFT 12 222 #define CFG_TOP_REG_MIU_LAT_THOLD_E_ABT_MASK 0x000F0000 223 #define CFG_TOP_REG_MIU_LAT_THOLD_E_ABT_SHIFT 16 224 #define CFG_TOP_REG_MIU_LAT_THOLD_F_ABT_MASK 0x00F00000 225 #define CFG_TOP_REG_MIU_LAT_THOLD_F_ABT_SHIFT 20 226 #define CFG_TOP_REG_MIU_LAT_THOLD_G_ABT_MASK 0x0F000000 227 #define CFG_TOP_REG_MIU_LAT_THOLD_G_ABT_SHIFT 24 228 #define CFG_TOP_REG_MIU_LAT_THOLD_H_ABT_MASK 0xF0000000 229 #define CFG_TOP_REG_MIU_LAT_THOLD_H_ABT_SHIFT 28 230 231 REG16 CFG_TOP_0F; // reg_miu_lat_cycle_per_tick 232 233 REG16 CFG_TOP_10_23[0x24 - 0x10]; // reg_miu_lat_thold_abt 0 ~ 9 234 235 REG16 CFG_TOP_24; // reg_miu_fixed_last_wd_en_done_z 236 #define CFG_TOP_24_REG_MIU_FIXED_LAST_WD_EN_DONE_Z_ABT 0x0001 237 #define CFG_TOP_24_REG_MIU_FIXED_LAST_WD_EN_DONE_Z_ABT_ALL 0x03FF 238 239 REG16 CFG_TOP_25; // reg_check_mi2rdy 240 #define CFG_TOP_25_REG_CHECK_MI2RDY_ABT 0x0001 241 #define CFG_TOP_25_REG_CHECK_MI2RDY_ABT_ALL 0x03FF 242 243 REG16 CFG_TOP_26_2C[0x2D - 0x26]; // reserved 244 245 REG16 CFG_TOP_2D; 246 #define CFG_TOP_2D_REG_PVR_RASP_REC_EVENT_ENABLE 0x0001 // RASP 1 ~ 10 247 248 REG16 CFG_TOP_2E; 249 #define CFG_TOP_2E_REG_PVR_LUT_REC_EVENT_ENABLE 0x0001 // LUT 1 ~ 10 250 251 REG16 CFG_TOP_2F; 252 #define CFG_TOP_2F_REG_PVR_EVENT_ENABLE 0x0001 // PVR 1 ~ 10 253 254 REG_TOP_ProtectCtrl CFG_TOP_30_4B[7]; // FILEIN 0 ~ 6 bnd 255 256 REG16 CFG_TOP_4C_4F[0x50 - 0x4C]; // reserved 257 258 REG_TOP_ProtectCtrl CFG_TOP_50_57[2]; // MMFI 0 ~ 1 bnd 259 260 REG16 CFG_TOP_58_5F[0x60 - 0x58]; // reserved 261 262 REG16 CFG_TOP_60_6C[0x6D - 0x60]; // reg_bist_fail_status 263 264 REG32 CFG_TOP_6D_6E; // reserved 265 266 REG16 CFG_TOP_6F; // reg_sync_reg_ctrl 267 #define CFG_TOP_6F_REG_EN_ALWAYS_ON 0x0001 268 #define CFG_TOP_6F_REG_EN_TIMER_POSTPONE_MASK 0x00F0 269 #define CFG_TOP_6F_REG_EN_TIMER_POSTPONE_SHIFT 4 270 271 REG16 CFG_TOP_70; // reg_clk_gating 272 #define CFG_TOP_70_REG_CLK_GATING_TSP_ENG 0x0001 273 #define CFG_TOP_70_REG_CLK_GATING_MMFI 0x0002 // MMFI 0 ~ 1 274 #define CFG_TOP_70_REG_MIU_CLK_GATING_TSP_ENG 0x0100 275 #define CFG_TOP_70_REG_MIU_CLK_GATING_MMFI 0x0200 // MMFI 0 ~ 1 276 277 REG16 CFG_TOP_71_77[0x78 - 0x71]; // reserved 278 279 REG16 CFG_TOP_78; // reg_reset_ctrl0 280 281 REG16 CFG_TOP_79; // reg_reset_ctrl1 282 283 REG16 CFG_TOP_7A; // reg_reset_ctrl2 284 285 REG16 CFG_TOP_7B; // reg_reset_ctrl3 286 287 REG16 CFG_TOP_7C; // reg_reset_ctrl4 288 289 REG16 CFG_TOP_7D; // reg_reset_ctrl5 290 #define CFG_TOP_7D_REG_RESET_OTV 0x0100 291 #define CFG_TOP_7D_REG_RESET_DEBUG_TABLE 0x0200 292 #define CFG_TOP_7D_REG_RESET_DMA_ENG 0x0400 293 #define CFG_TOP_7D_REG_RESET_SEC_CMP 0x0800 294 #define CFG_TOP_7D_REG_RESET_SECFLT_REG 0x1000 295 #define CFG_TOP_7D_REG_RESET_SEC 0x2000 296 #define CFG_TOP_7D_REG_RESET_PID_TABLE 0x4000 297 298 REG16 CFG_TOP_7E; // reg_reset_ctrl6 299 300 } REG_TOP_Ctrl; 301 302 #endif // _REG_TOP_H_ 303