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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regOTHER.h 98 // Description: TSP Resample / Misc. Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_OTHER_H_ 103 #define _REG_OTHER_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 // MMFI Multi Media File In 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 137 138 //------------------------------------------------------------------------------------------------- 139 // Harware Capability 140 //------------------------------------------------------------------------------------------------- 141 142 143 //------------------------------------------------------------------------------------------------- 144 // Type and Structure 145 //------------------------------------------------------------------------------------------------- 146 147 typedef struct _REG_OTHER_VQ_TX 148 { 149 REG32 reg_vq_base; 150 REG16 reg_vq_size_208byte; 151 REG16 reg_vq_ctrl; 152 #define REG_OTHER_VQ_TX_REG_VQ_PRIORITY_THRESHOLD_MASK 0x001F 153 #define REG_OTHER_VQ_TX_REG_VQ_PRIORITY_THRESHOLD_SHIFT 0 154 #define REG_OTHER_VQ_TX_REG_VQ_RESET 0x0100 155 #define REG_OTHER_VQ_TX_REG_VQ_OVERFLOW_INT_EN 0x0200 156 #define REG_OTHER_VQ_TX_REG_VQ_CLR_OVERFLOW_INT 0x0400 157 #define REG_OTHER_VQ_TX_REG_READ_VQ_EVER_FULL 0x1000 158 #define REG_OTHER_VQ_TX_REG_READ_VQ_EVER_OVERFLOW 0x2000 159 #define REG_OTHER_VQ_TX_REG_VQ_EMPTY 0x4000 160 #define REG_OTHER_VQ_TX_REG_READ_VQ_BUSY 0x8000 161 REG16 reg_vq_status; 162 #define REG_OTHER_VQ_TX_REG_VQ_STATUS_EMPTY 0x0001 163 #define REG_OTHER_VQ_TX_REG_VQ_STATUS_FULL 0x0002 164 #define REG_OTHER_VQ_TX_REG_VQ_STATUS_WR_EVER_LEVEL_MASK 0x000C 165 #define REG_OTHER_VQ_TX_REG_VQ_STATUS_WR_EVER_LEVEL_SHIFT 2 166 167 REG16 reg_vq_config0; 168 169 REG32 reg_vq_reserved; 170 171 } REG_OTHER_VQ_TX; 172 173 typedef struct _REG_OTHER_Ctrl // OTHER (Bank:0x1702) 174 { 175 REG16 CFG_OTHER_00_0F[0x10 - 0x0]; // reserved (for Resample) 176 177 REG16 CFG_OTHER_10_12[0x13 - 0x10]; // reg_hw_semaphore 178 179 REG16 CFG_OTHER_13; 180 #define CFG_OTHER_13_REG_3WIRE_SERIAL_MODE_EN 0x0001 181 #define CFG_OHTER_13_REG_TSP2MI_REQ_MCM_DISABLE 0x0100 182 #define CFG_OHTER_13_REG_TSP2MI_MASK_MCM_FILEIN 0x0200 183 184 REG16 CFG_OTHER_14; 185 #define CFG_OHTER_14_REG_OR_WRITE_FIX_FOR_NEW_MIU_ARBITER_DISABLE 0x0001 186 #define CFG_OHTER_14_REG_CPU_LOAD_CODE_ONLY_ONE_TIME_BY_TEE 0x0002 187 #define CFG_OHTER_14_REG_CPU_SECURE_STATUS 0x0004 188 #define CFG_OHTER_14_REG_SCR_BIT_AFTER_CA 0x0008 189 190 REG16 CFG_OTHER_15; // reg_filein_int 191 #define CFG_OTHER_15_REG_FILEIN_INT_EN_MASK 0x00FF 192 #define CFG_OTHER_15_REG_FILEIN_INT_EN_SHIFT 0 193 #define CFG_OTHER_15_FILEIN0_RDONE_INT_EN 0x0001 194 #define CFG_OTHER_15_FILEIN1_RDONE_INT_EN 0x0002 195 #define CFG_OTHER_15_FILEIN2_RDONE_INT_EN 0x0004 196 #define CFG_OTHER_15_FILEIN3_RDONE_INT_EN 0x0008 197 #define CFG_OTHER_15_FILEIN4_RDONE_INT_EN 0x0010 198 #define CFG_OTHER_15_FILEIN5_RDONE_INT_EN 0x0020 199 #define CFG_OTHER_15_FILEIN6_RDONE_INT_EN 0x0040 200 201 #define CFG_OTHER_15_REG_FILEIN_INT_STATUS_MASK 0xFF00 202 #define CFG_OTHER_15_REG_FILEIN_INT_STATUS_SHIFT 8 203 #define CFG_OTHER_15_FILEIN0_RDONE_STATUS 0x0100 204 #define CFG_OTHER_15_FILEIN1_RDONE_STATUS 0x0200 205 #define CFG_OTHER_15_FILEIN2_RDONE_STATUS 0x0400 206 #define CFG_OTHER_15_FILEIN3_RDONE_STATUS 0x0800 207 #define CFG_OTHER_15_FILEIN4_RDONE_STATUS 0x1000 208 #define CFG_OTHER_15_FILEIN5_RDONE_STATUS 0x2000 209 #define CFG_OTHER_15_FILEIN6_RDONE_STATUS 0x4000 210 211 REG16 CFG_OTHER_16; 212 #define CFG_OHTER_16_REG_CLR_SRAM_COLLISION 0x0001 213 #define CFG_OHTER_16_REG_PREVENT_SRAM_COLLISION 0x0002 214 #define CFG_OHTER_16_REG_RW_CONDITION_0 0x0004 215 #define CFG_OHTER_16_REG_RW_CONDITION_1 0x0008 216 #define CFG_OHTER_16_REG_BURST4_NEW_MODE_0 0x0010 217 #define CFG_OHTER_16_REG_BURST4_NEW_MODE_1 0x0020 218 #define CFG_OHTER_16_REG_MASK_DMA_OVERFLOW 0x0040 219 #define CFG_OHTER_16_REG_FIX_PINPON_SYNCP_IN 0x0080 220 #define CFG_OHTER_16_REG_FIXED_DMA_WADDR_NEXT_OVERFLOW 0x0100 221 222 REG16 CFG_OTHER_17; // reserved 223 224 REG16 CFG_OTHER_18; 225 #define CFG_OTHER_18_REG_PVR1_DMAW_PROTECT_EN 0x0001 226 #define CFG_OTHER_18_REG_MMFI0_DMAR_PROTECT_EN 0x0100 227 #define CFG_OTHER_18_REG_MMFI0_ILLEGAL_ADDR_0 0x0400 228 #define CFG_OTHER_18_REG_MMFI0_ILLEGAL_MIU_NS_EN 0x1000 229 #define CFG_OTHER_18_REG_DISABLE_MMFI0_ADDR_LEN_BY_TEE 0x4000 230 231 REG16 CFG_OTHER_19; 232 #define CFG_OTHER_19_REG_FILEIN0_DMAR_PROTECT_EN 0x0001 233 #define CFG_OTHER_19_REG_FILEIN0_ILLEGAL_ADDR_0 0x0100 234 235 REG16 CFG_OTHER_1A; 236 #define CFG_OTHER_1A_REG_FILEIN0_ILLEGAL_MIU_NS_EN 0x0001 237 #define CFG_OTHER_1A_REG_DISABLE_FILEIN0_ADDR_LEN_BY_TEE 0x0100 238 239 REG16 CFG_OTHER_1B_1E[0x1F - 0x1B]; // reserved 240 241 REG16 CFG_OTHER_1F; 242 #define CFG_OTHER_1F_REG_SRC_AES_PVR_KEY_MASK 0x000F 243 #define CFG_OTHER_1F_REG_SRC_AES_PVR_KEY_SHIFT 0 244 #define CFG_OTHER_1F_REG_SRC_AES_FILEIN_KEY_MASK 0x00F0 245 #define CFG_OTHER_1F_REG_SRC_AES_FILEIN_KEY_SHIFT 4 246 247 REG16 CFG_OTHER_20_27[0x28 - 0x20]; // reg_aes_key_pvr 248 249 REG16 CFG_OTHER_28_2F[0x30 - 0x28]; // reg_aes_key_filein 250 251 REG_OTHER_VQ_TX CFG_OTHER_30_67[7]; // vqtx 0 ~ 6 252 253 REG16 CFG_OTHER_68_6F[0x70 - 0x68]; // reserved 254 255 REG16 CFG_OTHER_70; 256 #define CFG_OTHER_70_REG_VQ_FORCEFIRE_CNT_1K_MASK 0x003F 257 #define CFG_OTHER_70_REG_VQ_FORCEFIRE_CNT_1K_SHIFT 0 258 #define CFG_OTHER_70_REG_VQ_STATUS_CLR 0x0040 259 #define CFG_OTHER_70_REG_VQ_IDLE_CNT_DISABLE 0x0080 260 #define CFG_OTHER_70_REG_VQ_WR_THRESHOLD_MASK 0x1F00 261 #define CFG_OTHER_70_REG_VQ_WR_THRESHOLD_SHIFT 8 262 #define CFG_OTHER_70_REG_VQ_RX_ARBITER_MODE_MASK 0xC000 263 #define CFG_OTHER_70_REG_VQ_RX_ARBITER_MODE_SHIFT 14 264 265 REG16 CFG_OTHER_71_74[0x75 - 0x71]; // reg_vq_rx_priority 266 #define CFG_OTHER_VQ_RX_PRIORITY_EVEN_MASK 0x007F 267 #define CFG_OTHER_VQ_RX_PRIORITY_EVEN_SHIFT 0 268 #define CFG_OTHER_VQ_RX_PRIORITY_ODD_MASK 0x7F00 269 #define CFG_OTHER_VQ_RX_PRIORITY_ODD_SHIFT 8 270 271 REG16 CFG_OTHER_75; 272 #define CFG_OTHER_75_REG_VQ_TX_BLOCK_DISABLE 0x0001 273 #define CFG_OTHER_75_REG_FIXED_MIU_REQ_FLUSH 0x0100 274 #define CFG_OTHER_75_REG_CHECK_BURST_LEN 0x0200 275 #define CFG_OTHER_75_REG_CLR_NO_HIT_INT 0x0400 276 #define CFG_OTHER_75_REG_VQ_RX_THRESHOLD_MASK 0x3800 277 #define CFG_OTHER_75_REG_VQ_RX_THRESHOLD_SHIFT 11 278 279 REG16 CFG_OTHER_76_7D[0x7E - 0x76]; // reserved 280 281 REG16 CFG_OTHER_7E; // reg_reset_ctrl 282 #define CFG_OTHER_7E_REG_VQ_TOP_RESET 0x0001 283 #define CFG_OTHER_7E_REG_VQ_RX_RESET 0x0002 284 #define CFG_OTHER_7E_REG_VQ_TX_RESET 0x0004 285 286 REG16 CFG_OTHER_7F; 287 #define CFG_OTHER_7E_REG_CLK_GATING_VQ_TX_TSP 0x0001 288 #define CFG_OTHER_7E_REG_CLK_GATING_VQ_TX_MIU 0x0100 289 290 } REG_OTHER_Ctrl; 291 292 #endif // _REG_OTHER_H_ 293