1 /*
2 * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <common/debug.h>
8 #include <lib/gpt_rme/gpt_rme.h>
9 #include <plat/arm/common/plat_arm.h>
10 #include <plat/common/platform.h>
11 #include <nrd_plat.h>
12
13 /*
14 * The GPT library might modify the gpt regions structure to optimize
15 * the layout, so the array cannot be constant.
16 */
17 static pas_region_t pas_regions[] = {
18 NRD_PAS_SHARED_SRAM,
19 NRD_PAS_SYSTEM_NCI,
20 NRD_PAS_DEBUG_NIC,
21 NRD_PAS_NS_UART,
22 NRD_PAS_REALM_UART,
23 NRD_PAS_AP_NS_WDOG,
24 NRD_PAS_AP_ROOT_WDOG,
25 NRD_PAS_AP_SECURE_WDOG,
26 NRD_PAS_SECURE_SRAM_ERB_AP,
27 NRD_PAS_NS_SRAM_ERB_AP,
28 NRD_PAS_ROOT_SRAM_ERB_AP,
29 NRD_PAS_REALM_SRAM_ERB_AP,
30 NRD_PAS_SECURE_SRAM_ERB_SCP,
31 NRD_PAS_NS_SRAM_ERB_SCP,
32 NRD_PAS_ROOT_SRAM_ERB_SCP,
33 NRD_PAS_REALM_SRAM_ERB_SCP,
34 NRD_PAS_SECURE_SRAM_ERB_MCP,
35 NRD_PAS_NS_SRAM_ERB_MCP,
36 NRD_PAS_ROOT_SRAM_ERB_MCP,
37 NRD_PAS_REALM_SRAM_ERB_MCP,
38 NRD_PAS_SECURE_SRAM_ERB_RSE,
39 NRD_PAS_NS_SRAM_ERB_RSE,
40 NRD_PAS_ROOT_SRAM_ERB_RSE,
41 NRD_PAS_REALM_SRAM_ERB_RSE,
42 NRD_PAS_RSE_SECURE_SRAM_ERB_RSM,
43 NRD_PAS_RSE_NS_SRAM_ERB_RSM,
44 NRD_PAS_SCP_SECURE_SRAM_ERB_RSM,
45 NRD_PAS_SCP_NS_SRAM_ERB_RSM,
46 NRD_PAS_MCP_SECURE_SRAM_ERB_RSM,
47 NRD_PAS_MCP_NS_SRAM_ERB_RSM,
48 NRD_PAS_AP_SCP_ROOT_MHU,
49 NRD_PAS_AP_MCP_NS_MHU,
50 NRD_PAS_AP_MCP_SECURE_MHU,
51 NRD_PAS_AP_MCP_ROOT_MHU,
52 NRD_PAS_AP_RSE_NS_MHU,
53 NRD_PAS_AP_RSE_SECURE_MHU,
54 NRD_PAS_AP_RSE_ROOT_MHU,
55 NRD_PAS_AP_RSE_REALM_MHU,
56 NRD_PAS_SCP_MCP_RSE_CROSS_CHIP_MHU,
57 NRD_PAS_SYNCNT_MSTUPDTVAL_ADDR,
58 NRD_PAS_STM_SYSTEM_ITS,
59 NRD_PAS_SCP_MCP_RSE_SHARED_SRAM,
60 NRD_PAS_GIC,
61 NRD_PAS_NS_DRAM,
62 #if SPD_spmd && SPMD_SPM_AT_SEL2
63 NRD_PAS_BL32,
64 #endif
65 NRD_PAS_RMM,
66 NRD_PAS_L1GPT,
67 NRD_PAS_CMN,
68 NRD_PAS_LCP_PERIPHERAL,
69 NRD_PAS_DDR_IO,
70 NRD_PAS_SMMU_NCI_IO,
71 NRD_PAS_DRAM2_CHIP0,
72 #if NRD_CHIP_COUNT > 1
73 NRD_PAS_DRAM1_CHIP1,
74 NRD_PAS_DRAM2_CHIP1,
75 #endif
76 #if NRD_CHIP_COUNT > 2
77 NRD_PAS_DRAM1_CHIP2,
78 NRD_PAS_DRAM2_CHIP2,
79 #endif
80 #if NRD_CHIP_COUNT > 3
81 NRD_PAS_DRAM1_CHIP3,
82 NRD_PAS_DRAM2_CHIP3
83 #endif
84 };
85
86 static const arm_gpt_info_t arm_gpt_info = {
87 .pas_region_base = pas_regions,
88 .pas_region_count = (unsigned int)ARRAY_SIZE(pas_regions),
89 .l0_base = (uintptr_t)ARM_L0_GPT_BASE,
90 .l1_base = (uintptr_t)ARM_L1_GPT_BASE,
91 .l0_size = (size_t)ARM_L0_GPT_SIZE,
92 .l1_size = (size_t)ARM_L1_GPT_SIZE,
93 .pps = GPCCR_PPS_256TB,
94 .pgs = GPCCR_PGS_4K
95 };
96
plat_arm_get_gpt_info(void)97 const arm_gpt_info_t *plat_arm_get_gpt_info(void)
98 {
99 return &arm_gpt_info;
100 }
101