1 /* 2 * Copyright (c) 2025-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef RDASPEN_RAS_H 8 #define RDASPEN_RAS_H 9 10 #include <lib/extensions/ras.h> 11 #include <plat/common/platform.h> 12 #include <platform_def.h> 13 14 /* 15 * CPU IRQ RAS Defines 16 */ 17 #define CPU_FAULT_IRQ PLAT_CORE_FAULT_IRQ 18 19 /* CPU RAS Control Register Defines */ 20 #define ERX_CTRL_CFI_ENABLE U(1UL << 8) 21 #define ERX_CTRL_FI_ENABLE U(1UL << 3) 22 #define ERX_CTRL_UI_ENABLE U(1UL << 2) 23 #define ERX_CTRL_ED_ENABLE U(1UL << 0) 24 25 /* CPU RAS STATUS Register Defines */ 26 #define ERX_STATUS_AV U(1UL << 31) 27 #define ERX_STATUS_ADDRV(x) (((x) & ERX_STATUS_AV) != 0U) 28 #define ERX_STATUS_V U(1UL << 30) 29 #define ERX_STATUS_CE U(1UL << 25) 30 #define ERX_STATUS_UE U(1UL << 29) 31 #define ERX_STATUS_DE U(1UL << 23) 32 33 #define ERXMISC0_UNIT_MASK ULL(0xF) 34 #define ERXMISC0_UNIT(x) ((unsigned int)((x) & ERXMISC0_UNIT_MASK)) 35 36 #define ERXMISC0_UNIT_L1I U(0x1) 37 #define ERXMISC0_UNIT_L2_TLB U(0x2) 38 #define ERXMISC0_UNIT_L1D U(0x4) 39 #define ERXMISC0_UNIT_L2_CACHE U(0x8) 40 41 /* Interrupt ID to trigger to EL1 */ 42 #define ERROR_NOTIFICATION_IRQ 89U 43 44 /* Assembly helpers for CPU RAS Registers */ 45 void clear_cpu_pfg_ctrl_register(void); 46 void clear_cpu_pfg_cdn_register(void); 47 void clear_cpu_erx_misc0_register(void); 48 49 void rdaspen_ras_init_per_cpu(void); 50 void rdaspen_css_pwr_domain_on_finish(const psci_power_state_t *target_state); 51 52 #endif /* RDASPEN_RAS_H */ 53