1 /* 2 * Copyright (c) 2024-2025, Linaro Limited. All rights reserved. 3 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 #ifndef QEMU_PAS_DEF_H 8 #define QEMU_PAS_DEF_H 9 10 #include <lib/gpt_rme/gpt_rme.h> 11 #include "platform_def.h" 12 13 /***************************************************************************** 14 * PAS regions used to initialize the Granule Protection Table (GPT) 15 ****************************************************************************/ 16 17 /* EL3 SRAM */ 18 #define QEMU_PAS_ROOT_BASE (BL32_MEM_BASE + BL32_MEM_SIZE) 19 #define QEMU_PAS_ROOT_SIZE (BL_RAM_SIZE - \ 20 (BL32_MEM_SIZE + RME_GPT_DRAM_SIZE)) 21 22 /* Secure DRAM */ 23 #define QEMU_PAS_SEC_BASE BL32_MEM_BASE /* BL32_SRAM_BASE */ 24 #define QEMU_PAS_SEC_SIZE BL32_MEM_SIZE 25 26 /* GPTs */ 27 #define QEMU_PAS_GPT_BASE RME_GPT_DRAM_BASE /* PLAT_QEMU_L0_GPT_BASE */ 28 #define QEMU_PAS_GPT_SIZE RME_GPT_DRAM_SIZE 29 30 /* RMM */ 31 #if ENABLE_RMM 32 #define QEMU_PAS_RMM_BASE RMM_BASE 33 #define QEMU_PAS_RMM_SIZE PLAT_QEMU_RMM_SIZE 34 35 /* Shared area between EL3 and RMM */ 36 #define QEMU_PAS_RMM_SHARED_BASE RMM_SHARED_BASE 37 #define QEMU_PAS_RMM_SHARED_SIZE RMM_SHARED_SIZE 38 #endif /* ENABLE_RMM */ 39 40 #define QEMU_PAS_ROOT GPT_MAP_REGION_GRANULE(QEMU_PAS_ROOT_BASE, \ 41 QEMU_PAS_ROOT_SIZE, \ 42 GPT_GPI_ROOT) 43 44 #define QEMU_PAS_SECURE GPT_MAP_REGION_GRANULE(QEMU_PAS_SEC_BASE, \ 45 QEMU_PAS_SEC_SIZE, \ 46 GPT_GPI_SECURE) 47 48 #define QEMU_PAS_GPTS GPT_MAP_REGION_GRANULE(QEMU_PAS_GPT_BASE, \ 49 QEMU_PAS_GPT_SIZE, \ 50 GPT_GPI_ROOT) 51 52 /* 53 * NS0 base address and size are fetched from the DT at runtime. 54 * See bl31_adjust_pas_regions() for details 55 */ 56 #define QEMU_PAS_NS0 GPT_MAP_REGION_GRANULE(0, 0, GPT_GPI_NS) 57 58 #if ENABLE_RMM 59 #define QEMU_PAS_REALM GPT_MAP_REGION_GRANULE(QEMU_PAS_RMM_BASE, \ 60 QEMU_PAS_RMM_SIZE + \ 61 QEMU_PAS_RMM_SHARED_SIZE, \ 62 GPT_GPI_REALM) 63 #endif /* ENABLE_RMM */ 64 65 /* Cover 4TB with L0GTP */ 66 #define PLAT_QEMU_GPCCR_PPS GPCCR_PPS_4TB 67 #define PLAT_QEMU_PPS SZ_4T 68 69 /* GPT Configuration options */ 70 #define PLATFORM_L0GPTSZ GPCCR_L0GPTSZ_30BITS 71 72 #endif /* QEMU_PAS_DEF_H */ 73