1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6/dts-v1/; 7#include "px30.dtsi" 8#include "rk3326-linux.dtsi" 9#include "px30-evb-ddr3-v10.dtsi" 10 11/ { 12 model = "Rockchip linux PX30 evb ddr3 board"; 13 compatible = "rockchip,px30-evb-ddr3-v10-linux", "rockchip,px30"; 14 15 /delete-node/ test-power; 16}; 17 18&dsi { 19 status = "okay"; 20 21 panel@0 { 22 compatible = "sitronix,st7703", "simple-panel-dsi"; 23 reg = <0>; 24 power-supply = <&vcc3v3_lcd>; 25 backlight = <&backlight>; 26 prepare-delay-ms = <2>; 27 reset-delay-ms = <1>; 28 init-delay-ms = <20>; 29 enable-delay-ms = <120>; 30 disable-delay-ms = <50>; 31 unprepare-delay-ms = <20>; 32 33 width-mm = <68>; 34 height-mm = <121>; 35 36 dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 37 MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 38 dsi,format = <MIPI_DSI_FMT_RGB888>; 39 dsi,lanes = <4>; 40 41 panel-init-sequence = [ 42 05 fa 01 11 43 39 00 04 b9 f1 12 83 44 39 00 1c ba 33 81 05 f9 0e 0e 00 00 00 45 00 00 00 00 00 44 25 00 91 0a 46 00 00 02 4f 01 00 00 37 47 15 00 02 b8 25 48 39 00 04 bf 02 11 00 49 39 00 0b b3 0c 10 0a 50 03 ff 00 00 00 50 00 51 39 00 0a c0 73 73 50 50 00 00 08 70 00 52 15 00 02 bc 46 53 15 00 02 cc 0b 54 15 00 02 b4 80 55 39 00 04 b2 c8 12 30 56 39 00 0f e3 07 07 0b 0b 03 0b 00 00 00 57 00 ff 00 c0 10 58 39 00 0d c1 53 00 1e 1e 77 e1 cc dd 67 59 77 33 33 60 39 00 07 c6 00 00 ff ff 01 ff 61 39 00 03 b5 09 09 62 39 00 03 b6 87 95 63 39 00 40 e9 c2 10 05 05 10 05 a0 12 31 64 23 3f 81 0a a0 37 18 00 80 01 65 00 00 00 00 80 01 00 00 00 48 66 f8 86 42 08 88 88 80 88 88 88 67 58 f8 87 53 18 88 88 81 88 88 68 88 00 00 00 01 00 00 00 00 00 69 00 00 00 00 70 39 00 3e ea 00 1a 00 00 00 00 02 00 00 71 00 00 00 1f 88 81 35 78 88 88 72 85 88 88 88 0f 88 80 24 68 88 73 88 84 88 88 88 23 10 00 00 1c 74 00 00 00 00 00 00 00 00 00 00 75 00 00 00 00 00 30 05 a0 00 00 76 00 00 77 39 00 23 e0 00 06 08 2a 31 3f 38 36 07 78 0c 0d 11 13 12 13 11 18 00 06 79 08 2a 31 3f 38 36 07 0c 0d 11 80 13 12 13 11 18 81 05 32 01 29 82 ]; 83 84 panel-exit-sequence = [ 85 05 00 01 28 86 05 00 01 10 87 ]; 88 89 display-timings { 90 native-mode = <&timing0>; 91 92 timing0: timing0 { 93 clock-frequency = <64000000>; 94 hactive = <720>; 95 vactive = <1280>; 96 hfront-porch = <40>; 97 hsync-len = <10>; 98 hback-porch = <40>; 99 vfront-porch = <22>; 100 vsync-len = <4>; 101 vback-porch = <11>; 102 hsync-active = <0>; 103 vsync-active = <0>; 104 de-active = <0>; 105 pixelclk-active = <0>; 106 }; 107 }; 108 109 ports { 110 #address-cells = <1>; 111 #size-cells = <0>; 112 113 port@0 { 114 reg = <0>; 115 panel_in_dsi: endpoint { 116 remote-endpoint = <&dsi_out_panel>; 117 }; 118 }; 119 }; 120 }; 121 122 ports { 123 #address-cells = <1>; 124 #size-cells = <0>; 125 126 port@1 { 127 reg = <1>; 128 dsi_out_panel: endpoint { 129 remote-endpoint = <&panel_in_dsi>; 130 }; 131 }; 132 }; 133}; 134