1 /*
2 * Copyright (c) 2023-2026, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <stdint.h>
9
10 #include <common/bl_common.h>
11 #include <drivers/generic_delay_timer.h>
12 #include <drivers/st/stm32_console.h>
13 #include <drivers/st/stm32mp_reset.h>
14 #include <lib/xlat_tables/xlat_tables_v2.h>
15 #include <plat/common/platform.h>
16
17 #include <platform_def.h>
18
19 static entry_point_info_t bl32_image_ep_info;
20 static entry_point_info_t bl33_image_ep_info;
21
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)22 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
23 u_register_t arg2, u_register_t arg3)
24 {
25 bl_params_t *params_from_bl2;
26 int ret;
27
28 /*
29 * Invalidate remaining data from second half of SYSRAM (used by BL2) as this area will
30 * be later used as non-secure.
31 */
32 inv_dcache_range(STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U,
33 STM32MP_SYSRAM_SIZE / 2U);
34
35 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
36 BL_CODE_END - BL_CODE_BASE,
37 MT_CODE | MT_SECURE);
38
39 /*
40 * Map soc_fw_config device tree with secure property, i.e. default region.
41 * DDR region definitions will be finalized at BL32 level.
42 */
43 mmap_add_region(arg1, arg1, STM32MP_SOC_FW_CONFIG_MAX_SIZE, MT_RO_DATA | MT_SECURE);
44
45 #if USE_COHERENT_MEM
46 /* Map coherent memory */
47 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
48 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
49 MT_DEVICE | MT_RW | MT_SECURE);
50 #endif
51
52 configure_mmu();
53
54 ret = dt_open_and_check(arg1);
55 if (ret < 0) {
56 EARLY_ERROR("%s: failed to open DT (%d)\n", __func__, ret);
57 panic();
58 }
59
60 ret = stm32mp2_clk_init();
61 if (ret < 0) {
62 EARLY_ERROR("%s: failed init clocks (%d)\n", __func__, ret);
63 panic();
64 }
65
66 generic_delay_timer_init();
67
68 (void)stm32mp_uart_console_setup();
69
70 /*
71 * Map upper SYSRAM where bl_params_t are stored in BL2
72 */
73 ret = mmap_add_dynamic_region(STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U,
74 STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U,
75 STM32MP_SYSRAM_SIZE / 2U, MT_RO_DATA | MT_SECURE);
76 if (ret < 0) {
77 ERROR("BL2 params area mapping: %d\n", ret);
78 panic();
79 }
80
81 assert(arg0 != 0UL);
82 params_from_bl2 = (bl_params_t *)arg0;
83 assert(params_from_bl2 != NULL);
84 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
85 assert(params_from_bl2->h.version >= VERSION_2);
86
87 bl_params_node_t *bl_params = params_from_bl2->head;
88
89 while (bl_params != NULL) {
90 /*
91 * Copy BL33 entry point information.
92 * They are stored in Secure RAM, in BL2's address space.
93 */
94 if (bl_params->image_id == BL33_IMAGE_ID) {
95 bl33_image_ep_info = *bl_params->ep_info;
96 /*
97 * Check if hw_configuration is given to BL32 and
98 * share it to BL33
99 */
100 if (arg2 != 0U) {
101 bl33_image_ep_info.args.arg0 = 0U;
102 bl33_image_ep_info.args.arg1 = 0U;
103 bl33_image_ep_info.args.arg2 = arg2;
104 }
105 }
106
107 if (bl_params->image_id == BL32_IMAGE_ID) {
108 bl32_image_ep_info = *bl_params->ep_info;
109
110 if (arg2 != 0U) {
111 bl32_image_ep_info.args.arg3 = arg2;
112 }
113 }
114
115 bl_params = bl_params->next_params_info;
116 }
117
118 ret = mmap_remove_dynamic_region(STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U,
119 STM32MP_SYSRAM_SIZE / 2U);
120 if (ret < 0) {
121 ERROR("BL2 params area unmapping: %d\n", ret);
122 panic();
123 }
124 }
125
bl31_plat_arch_setup(void)126 void bl31_plat_arch_setup(void)
127 {
128 stm32mp_gic_init();
129 }
130
bl31_platform_setup(void)131 void bl31_platform_setup(void)
132 {
133 }
134
bl31_plat_get_next_image_ep_info(unsigned int type)135 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
136 {
137 entry_point_info_t *next_image_info = NULL;
138
139 assert(sec_state_is_valid(type));
140
141 switch (type) {
142 case NON_SECURE:
143 next_image_info = &bl33_image_ep_info;
144 break;
145
146 case SECURE:
147 next_image_info = &bl32_image_ep_info;
148 break;
149
150 default:
151 break;
152 }
153
154 /* None of the next images on ST platforms can have 0x0 as the entrypoint */
155 if ((next_image_info == NULL) || (next_image_info->pc == 0UL)) {
156 return NULL;
157 }
158
159 return next_image_info;
160 }
161
162 /* Only support system reset for serial boot and no low power feature to reduce BL31 size */
163 #if !STM32MP_SUPPORT_PM
stm32_system_reset(void)164 static void __dead2 stm32_system_reset(void)
165 {
166 stm32mp_system_reset();
167 }
168
169 static const plat_psci_ops_t stm32_psci_ops = {
170 .system_reset = stm32_system_reset,
171 };
172
173 /* Stub PSCI platform functions */
plat_get_target_pwr_state(unsigned int lvl,const plat_local_state_t * states,unsigned int ncpu)174 plat_local_state_t plat_get_target_pwr_state(unsigned int lvl,
175 const plat_local_state_t *states,
176 unsigned int ncpu)
177 {
178 return 0U;
179 }
180
plat_setup_psci_ops(uintptr_t sec_entrypoint,const plat_psci_ops_t ** psci_ops)181 int plat_setup_psci_ops(uintptr_t sec_entrypoint,
182 const plat_psci_ops_t **psci_ops)
183 {
184 *psci_ops = &stm32_psci_ops;
185 return 0;
186 }
187 #endif /* STM32MP_SUPPORT_PM */
188