1 /*
2 * Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <platform_def.h>
8
9 #include <arch.h>
10 #include <arch_helpers.h>
11 #include <common/bl_common.h>
12 #include <common/debug.h>
13 #include <lib/mmio.h>
14 #include <lib/xlat_tables/xlat_mmu_helpers.h>
15 #include <lib/xlat_tables/xlat_tables_defs.h>
16 #include <drivers/generic_delay_timer.h>
17 #if TRANSFER_LIST
18 #include <transfer_list.h>
19 #endif
20
21 #include <plat/common/platform.h>
22 #include <rpi_shared.h>
23
24 /* Data structure which holds the extents of the trusted SRAM for BL1 */
25 static meminfo_t bl1_tzram_layout;
26 #if TRANSFER_LIST
27 /* Secure transfer list header (firmware handoff) */
28 struct transfer_list_header *secure_tl;
29 #endif
30
bl1_plat_sec_mem_layout(void)31 meminfo_t *bl1_plat_sec_mem_layout(void)
32 {
33 return &bl1_tzram_layout;
34 }
35
36 /*******************************************************************************
37 * Perform any BL1 specific platform actions.
38 ******************************************************************************/
bl1_early_platform_setup(void)39 void bl1_early_platform_setup(void)
40 {
41 /* use the 19.2 MHz clock for the architected timer */
42 mmio_write_32(RPI3_INTC_BASE_ADDRESS + RPI3_INTC_CONTROL_OFFSET, 0);
43 mmio_write_32(RPI3_INTC_BASE_ADDRESS + RPI3_INTC_PRESCALER_OFFSET,
44 0x80000000);
45
46 /* Initialize the console to provide early debug support */
47 rpi3_console_init();
48
49 /*
50 * Write the System Timer Frequency to CNTFRQ manually, this
51 * is required to use the delay_timer functionality.
52 */
53 write_cntfrq_el0(plat_get_syscnt_freq2());
54
55 /* Enable arch timer */
56 generic_delay_timer_init();
57
58 /* Allow BL1 to see the whole Trusted RAM */
59 bl1_tzram_layout.total_base = BL_RAM_BASE;
60 bl1_tzram_layout.total_size = BL_RAM_SIZE;
61
62 #if TRANSFER_LIST
63 /* Initialize the secure transfer list in the reserved FW handoff region */
64 secure_tl = transfer_list_init((void *)(uintptr_t)FW_HANDOFF_BASE,
65 FW_HANDOFF_SIZE);
66 if (secure_tl == NULL) {
67 ERROR("BL1: Failed to initialize transfer list\n");
68 panic();
69 }
70 #endif /* TRANSFER_LIST */
71 }
72
73 /******************************************************************************
74 * Perform the very early platform specific architecture setup. This only
75 * does basic initialization. Later architectural setup (bl1_arch_setup())
76 * does not do anything platform specific.
77 *****************************************************************************/
bl1_plat_arch_setup(void)78 void bl1_plat_arch_setup(void)
79 {
80 rpi3_setup_page_tables(bl1_tzram_layout.total_base,
81 bl1_tzram_layout.total_size,
82 BL_CODE_BASE, BL1_CODE_END,
83 BL1_RO_DATA_BASE, BL1_RO_DATA_END
84 #if USE_COHERENT_MEM
85 , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END
86 #endif
87 );
88
89 enable_mmu_el3(0);
90 }
91
bl1_platform_setup(void)92 void bl1_platform_setup(void)
93 {
94 uint32_t __unused rev;
95 int __unused rc;
96
97 #if TRANSFER_LIST
98 image_desc_t *bl2_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
99 assert(bl2_desc != NULL);
100
101 bl2_desc->ep_info.args.arg3 = (uint64_t)secure_tl;
102 #endif
103
104 rc = rpi3_vc_hardware_get_board_revision(&rev);
105
106 if (rc == 0) {
107 const char __unused *model, __unused *info;
108
109 switch (rev) {
110 case 0xA02082:
111 model = "Raspberry Pi 3 Model B";
112 info = "(1GB, Sony, UK)";
113 break;
114 case 0xA22082:
115 model = "Raspberry Pi 3 Model B";
116 info = "(1GB, Embest, China)";
117 break;
118 case 0xA020D3:
119 model = "Raspberry Pi 3 Model B+";
120 info = "(1GB, Sony, UK)";
121 break;
122 default:
123 model = "Unknown";
124 info = "(Unknown)";
125 ERROR("rpi3: Unknown board revision 0x%08x\n", rev);
126 break;
127 }
128
129 NOTICE("rpi3: Detected: %s %s [0x%08x]\n", model, info, rev);
130 } else {
131 ERROR("rpi3: Unable to detect board revision\n");
132 }
133
134 /* Initialise the IO layer and register platform IO devices */
135 plat_rpi3_io_setup();
136 }
137