1/* 2 * Copyright (c) 2013-2025, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2015-2026, Renesas Electronics Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8#include <arch.h> 9#include <asm_macros.S> 10#include <common/bl_common.h> 11#include <common/runtime_svc.h> 12#include <cortex_a55.h> 13#include <platform_def.h> 14 15#include "rcar_def.h" 16 17 .globl plat_get_my_entrypoint 18 .extern plat_set_my_stack 19 .globl platform_mem_init 20 21 .globl plat_crash_console_init 22 .globl plat_crash_console_putc 23 .globl plat_crash_console_flush 24 .globl plat_invalidate_icache 25 .globl plat_secondary_reset 26 .globl plat_my_core_pos 27 .globl plat_renesas_calc_core_pos 28 .globl bl31_plat_enable_mmu 29 30 .extern console_renesas_init 31 .extern console_renesas_putc 32 .extern console_renesas_flush 33 .extern rcar_pwrc_code_copy_to_system_ram 34 35 /* ----------------------------------------------------- 36 * void platform_get_core_pos (mpidr) 37 * ----------------------------------------------------- 38 */ 39func plat_renesas_calc_core_pos 40 lsr x0, x0, #8 41 and x1, x0, #MPIDR_CPU_MASK 42 and x0, x0, #MPIDR_CLUSTER_MASK 43 add x0, x1, x0, LSR #7 44 ret 45endfunc plat_renesas_calc_core_pos 46 47 /* ----------------------------------------------------- 48 * void platform_my_core_pos 49 * ----------------------------------------------------- 50 */ 51func plat_my_core_pos 52 mrs x0, mpidr_el1 53 b plat_renesas_calc_core_pos 54endfunc plat_my_core_pos 55 56 /* ----------------------------------------------------- 57 * void platform_get_my_entrypoint (unsigned int mpid); 58 * 59 * Main job of this routine is to distinguish between 60 * a cold and warm boot. 61 * On a cold boot the secondaries first wait for the 62 * platform to be initialized after which they are 63 * hotplugged in. The primary proceeds to perform the 64 * platform initialization. 65 * On a warm boot, each cpu jumps to the address in its 66 * mailbox. 67 * 68 * TODO: Not a good idea to save lr in a temp reg 69 * ----------------------------------------------------- 70 */ 71func plat_get_my_entrypoint 72 mrs x0, mpidr_el1 73 mov x9, x30 /* lr */ 74 75 ldr x1, =BOOT_KIND_BASE 76 ldr x21, [x1] 77 78 /* Check the reset info */ 79 and x1, x21, #0x000c 80 cmp x1, #0x0008 81 beq el3_panic 82 cmp x1, #0x000c 83 beq el3_panic 84 85 /* Check the boot kind */ 86 and x1, x21, #0x0003 87 cmp x1, #0x0002 88 beq el3_panic 89 cmp x1, #0x0003 90 beq el3_panic 91 92 /* warm boot or cold boot */ 93 and x1, x21, #1 94 cmp x1, #0 95 bne warm_reset 96 97 /* Cold boot */ 98 mov x0, #0 99 b exit 100 101warm_reset: 102 /* -------------------------------------------------------------------- 103 * A per-cpu mailbox is maintained in the trusted SDRAM. Its flushed out 104 * of the caches after every update using normal memory so its safe to 105 * read it here with SO attributes 106 * --------------------------------------------------------------------- 107 */ 108 ldr x10, =MBOX_BASE 109 bl plat_renesas_calc_core_pos 110 lsl x0, x0, #CACHE_WRITEBACK_SHIFT 111 ldr x0, [x10, x0] 112 cbz x0, _panic 113exit: 114 ret x9 115_panic: 116 b el3_panic 117 118endfunc plat_get_my_entrypoint 119 120 /* --------------------------------------------- 121 * plat_secondary_reset 122 * 123 * --------------------------------------------- 124 */ 125func plat_secondary_reset 126 mrs x0, sctlr_el3 127 bic x0, x0, #SCTLR_EE_BIT 128 msr sctlr_el3, x0 129 isb 130 131 mrs x0, cptr_el3 132 bic w0, w0, #TCPAC_BIT 133 bic w0, w0, #TTA_BIT 134 bic w0, w0, #TFP_BIT 135 msr cptr_el3, x0 136 137 mov_imm x0, PARAMS_BASE 138 mov_imm x2, BL31_BASE 139 ldr x3, =BOOT_KIND_BASE 140 mov x1, #0x1 141 str x1, [x3] 142 br x2 /* jump to BL31 */ 143 nop 144 nop 145 nop 146endfunc plat_secondary_reset 147 148 /* ----------------------------------------------------- 149 * void platform_mem_init (void); 150 * 151 * Zero out the mailbox registers in the shared memory 152 * and set the rcar_boot_kind_flag. 153 * The mmu is turned off right now and only the primary can 154 * ever execute this code. Secondaries will read the 155 * mailboxes using SO accesses. 156 * ----------------------------------------------------- 157 */ 158func platform_mem_init 159 ldr x0, =MBOX_BASE 160 mov w1, #PLATFORM_CORE_COUNT 161loop: 162 str xzr, [x0], #CACHE_WRITEBACK_GRANULE 163 subs w1, w1, #1 164 b.gt loop 165 ret 166endfunc platform_mem_init 167 168 /* --------------------------------------------- 169 * int plat_crash_console_init(void) 170 * Function to initialize log area 171 * --------------------------------------------- 172 */ 173func plat_crash_console_init 174 mov x1, sp 175 mov_imm x2, RCAR_CRASH_STACK 176 mov sp, x2 177 str x1, [sp, #-16]! 178 str x30, [sp, #-16]! 179 bl console_renesas_init 180 ldr x30, [sp], #16 181 ldr x1, [sp], #16 182 mov sp, x1 183 mov x0, #1 184 ret 185endfunc plat_crash_console_init 186 187 /* --------------------------------------------- 188 * int plat_crash_console_putc(int c) 189 * Function to store a character to log area 190 * --------------------------------------------- 191 */ 192func plat_crash_console_putc 193 mov x1, sp 194 mov_imm x2, RCAR_CRASH_STACK 195 mov sp, x2 196 str x1, [sp, #-16]! 197 str x30, [sp, #-16]! 198 str x3, [sp, #-16]! 199 str x4, [sp, #-16]! 200 str x5, [sp, #-16]! 201 str x6, [sp, #-16]! 202 str x7, [sp, #-16]! 203 bl console_renesas_putc 204 ldr x7, [sp], #16 205 ldr x6, [sp], #16 206 ldr x5, [sp], #16 207 ldr x4, [sp], #16 208 ldr x3, [sp], #16 209 ldr x30, [sp], #16 210 ldr x1, [sp], #16 211 mov sp, x1 212 ret 213endfunc plat_crash_console_putc 214 215 /* --------------------------------------------- 216 * void plat_crash_console_flush() 217 * --------------------------------------------- 218 */ 219func plat_crash_console_flush 220 ret 221endfunc plat_crash_console_flush 222 223 /* --------------------------------------------- 224 * void plat_invalidate_icache(void) 225 * Instruction Cache Invalidate All to PoU 226 * --------------------------------------------- 227 */ 228func plat_invalidate_icache 229 ic iallu 230 ret 231endfunc plat_invalidate_icache 232 233 /* ----------------------------------------------------- 234 * void bl31_plat_enable_mmu(uint32_t flags); 235 * 236 * Enable MMU in BL31. 237 * And copy the code to run on System RAM. 238 * Note: This function call will only be done from Warm boot. 239 * ----------------------------------------------------- 240 */ 241func bl31_plat_enable_mmu 242 mov x28, x30 243 bl enable_mmu_direct_el3 244 bl rcar_pwrc_code_copy_to_system_ram 245 mov x30, x28 246 ret 247endfunc bl31_plat_enable_mmu 248