1 /*
2 * Copyright (c) 2019-2024, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
4 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include <assert.h>
10 #include <arch.h>
11 #include <arch_helpers.h>
12 #include <common/bl_common.h>
13 #include <drivers/arm/gic_common.h>
14 #include <drivers/arm/gicv3.h>
15 #include <drivers/ti/uart/uart_16550.h>
16 #include <lib/mmio.h>
17 #include <lib/xlat_tables/xlat_mmu_helpers.h>
18 #include <lib/xlat_tables/xlat_tables_v2.h>
19 #include <plat/common/platform.h>
20
21 #include "agilex5_cache.h"
22 #include "agilex5_power_manager.h"
23 #include "ccu/ncore_ccu.h"
24 #include "socfpga_dt.h"
25 #include "socfpga_mailbox.h"
26 #include "socfpga_private.h"
27 #include "socfpga_reset_manager.h"
28
29 /* Get non-secure SPSR for BL33. Zephyr and Linux */
30 uint32_t arm_get_spsr_for_bl33_entry(void);
31
32 static entry_point_info_t bl32_image_ep_info;
33 static entry_point_info_t bl33_image_ep_info;
34
35 /* The GICv3 driver only needs to be initialized in EL3 */
36 static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
37
38 #define SMMU_SDMMC
39
bl31_plat_get_next_image_ep_info(uint32_t type)40 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
41 {
42 entry_point_info_t *next_image_info;
43
44 next_image_info = (type == NON_SECURE) ?
45 &bl33_image_ep_info : &bl32_image_ep_info;
46
47 /* None of the images on this platform can have 0x0 as the entrypoint */
48 if (next_image_info->pc)
49 return next_image_info;
50 else
51 return NULL;
52 }
53
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)54 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
55 u_register_t arg2, u_register_t arg3)
56 {
57 static console_t console;
58
59 mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY);
60
61 console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
62 PLAT_BAUDRATE, &console);
63
64 /* Enable TF-A BL31 logs when running from non-secure world also. */
65 console_set_scope(&console,
66 (CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH));
67
68 setup_smmu_stream_id();
69
70 /*
71 * Check params passed from BL31 should not be NULL,
72 */
73 void *from_bl2 = (void *) arg0;
74
75 #if RESET_TO_BL31
76 /* There are no parameters from BL2 if BL31 is a reset vector */
77 assert(from_bl2 == NULL);
78 void *plat_params_from_bl2 = (void *) arg3;
79
80 assert(plat_params_from_bl2 == NULL);
81
82 /* Populate entry point information for BL33 */
83 SET_PARAM_HEAD(&bl33_image_ep_info,
84 PARAM_EP,
85 VERSION_1,
86 0);
87
88 # if ARM_LINUX_KERNEL_AS_BL33
89 /*
90 * According to the file ``Documentation/arm64/booting.txt`` of the
91 * Linux kernel tree, Linux expects the physical address of the device
92 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
93 * must be 0.
94 */
95 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
96 bl33_image_ep_info.args.arg1 = 0U;
97 bl33_image_ep_info.args.arg2 = 0U;
98 bl33_image_ep_info.args.arg3 = 0U;
99 # endif
100
101 #else /* RESET_TO_BL31 */
102 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
103
104 assert(params_from_bl2 != NULL);
105
106 /*
107 * Copy BL32 (if populated by BL31) and BL33 entry point information.
108 * They are stored in Secure RAM, in BL31's address space.
109 */
110
111 if (params_from_bl2->h.type == PARAM_BL_PARAMS &&
112 params_from_bl2->h.version >= VERSION_2) {
113
114 bl_params_node_t *bl_params = params_from_bl2->head;
115
116 while (bl_params) {
117 if (bl_params->image_id == BL33_IMAGE_ID) {
118 bl33_image_ep_info = *bl_params->ep_info;
119 }
120 bl_params = bl_params->next_params_info;
121 }
122 } else {
123 struct socfpga_bl31_params *arg_from_bl2 =
124 (struct socfpga_bl31_params *) from_bl2;
125
126 assert(arg_from_bl2->h.type == PARAM_BL31);
127 assert(arg_from_bl2->h.version >= VERSION_1);
128
129 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
130 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
131 }
132
133 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
134 bl33_image_ep_info.args.arg1 = 0U;
135 bl33_image_ep_info.args.arg2 = 0U;
136 bl33_image_ep_info.args.arg3 = 0U;
137 #endif
138
139 /*
140 * Tell BL31 where the non-trusted software image
141 * is located and the entry state information
142 */
143 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
144 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
145
146 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
147 }
148
149 static const interrupt_prop_t agx5_interrupt_props[] = {
150 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(INTR_GROUP1S),
151 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(INTR_GROUP0)
152 };
153
154 gicv3_driver_data_t plat_gicv3_gic_data = {
155 .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE,
156 .gicr_base = PLAT_INTEL_SOCFPGA_GICR_BASE,
157 .interrupt_props = agx5_interrupt_props,
158 .interrupt_props_num = ARRAY_SIZE(agx5_interrupt_props),
159 .rdistif_num = PLATFORM_CORE_COUNT,
160 .rdistif_base_addrs = rdistif_base_addrs,
161 };
162
163 /*******************************************************************************
164 * Perform any BL3-1 platform setup code
165 ******************************************************************************/
bl31_platform_setup(void)166 void bl31_platform_setup(void)
167 {
168 socfpga_delay_timer_init();
169
170 /* TODO: DTB not available */
171 // socfpga_dt_populate_gicv3_config(SOCFPGA_DTB_BASE, &plat_gicv3_gic_data);
172 // NOTICE("SOCFPGA: GIC GICD base address 0x%lx\n", plat_gicv3_gic_data.gicd_base);
173 // NOTICE("SOCFPGA: GIC GICR base address 0x%lx\n", plat_gicv3_gic_data.gicr_base);
174
175 /* Initialize the gic cpu and distributor interfaces */
176 gicv3_driver_init(&plat_gicv3_gic_data);
177 gicv3_distif_init();
178 gicv3_rdistif_init(plat_my_core_pos());
179 gicv3_cpuif_enable(plat_my_core_pos());
180
181 #if SIP_SVC_V3
182 /*
183 * Re-initialize the mailbox to include V3 specific routines.
184 * In V3, this re-initialize is required because prior to BL31, U-Boot
185 * SPL has its own mailbox settings and this initialization will
186 * override to those settings as required by the V3 framework.
187 */
188 mailbox_init();
189 #endif
190
191 mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
192 }
193
194 const mmap_region_t plat_agilex_mmap[] = {
195 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
196 MAP_REGION_FLAT(PSS_BASE, PSS_SIZE, MT_DEVICE | MT_RW | MT_NS),
197 MAP_REGION_FLAT(MPFE_BASE, MPFE_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
198 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, MT_NON_CACHEABLE | MT_RW | MT_SECURE),
199 MAP_REGION_FLAT(CCU_BASE, CCU_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
200 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS),
201 MAP_REGION_FLAT(GIC_BASE, GIC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
202 {0}
203 };
204
205 /*******************************************************************************
206 * Perform the very early platform specific architectural setup here. At the
207 * moment this is only initializes the mmu in a quick and dirty way.
208 ******************************************************************************/
bl31_plat_arch_setup(void)209 void bl31_plat_arch_setup(void)
210 {
211 uint32_t boot_core = 0x00;
212 uint32_t cpuid = 0x00;
213
214 cpuid = MPIDR_AFFLVL1_VAL(read_mpidr());
215 boot_core = ((mmio_read_32(AGX5_PWRMGR(MPU_BOOTCONFIG)) & 0xC00) >> 10);
216 NOTICE("SOCFPGA: Boot Core = %x\n", boot_core);
217 NOTICE("SOCFPGA: CPU ID = %x\n", cpuid);
218 INFO("SOCFPGA: Invalidate Data cache\n");
219 invalidate_dcache_all();
220 /* Invalidate for NS EL2 and EL1 */
221 invalidate_cache_low_el();
222
223 NOTICE("SOCFPGA: Setting CLUSTERECTRL_EL1\n");
224 setup_clusterectlr_el1();
225 }
226
227 /* Get non-secure image entrypoint for BL33. Zephyr and Linux */
plat_get_ns_image_entrypoint(void)228 uintptr_t plat_get_ns_image_entrypoint(void)
229 {
230 #ifdef PRELOADED_BL33_BASE
231 return PRELOADED_BL33_BASE;
232 #else
233 return PLAT_NS_IMAGE_OFFSET;
234 #endif
235 }
236
237 /* Get non-secure SPSR for BL33. Zephyr and Linux */
arm_get_spsr_for_bl33_entry(void)238 uint32_t arm_get_spsr_for_bl33_entry(void)
239 {
240 unsigned int mode;
241 uint32_t spsr;
242
243 /* Figure out what mode we enter the non-secure world in */
244 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
245
246 /*
247 * TODO: Consider the possibility of specifying the SPSR in
248 * the FIP ToC and allowing the platform to have a say as
249 * well.
250 */
251 spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
252 return spsr;
253 }
254
255 /* SMP: Secondary cores BL31 setup reset vector */
bl31_plat_set_secondary_cpu_entrypoint(unsigned int cpu_id)256 void bl31_plat_set_secondary_cpu_entrypoint(unsigned int cpu_id)
257 {
258 unsigned int pch_cpu = 0x00;
259 unsigned int pchctlr_old = 0x00;
260 unsigned int pchctlr_new = 0x00;
261 uint32_t boot_core = 0x00;
262
263 /* Set bit for SMP secondary cores boot */
264 mmio_clrsetbits_32(L2_RESET_DONE_REG, BS_REG_MAGIC_KEYS_MASK,
265 SMP_SEC_CORE_BOOT_REQ);
266 boot_core = (mmio_read_32(AGX5_PWRMGR(MPU_BOOTCONFIG)) & 0xC00);
267 /* Update the p-channel based on cpu id */
268 pch_cpu = 1 << cpu_id;
269
270 if (boot_core == 0x00) {
271 /* Update reset vector to 0x00 */
272 mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU2,
273 (uint64_t) plat_secondary_cpus_bl31_entry >> 2);
274 } else {
275 /* Update reset vector to 0x00 */
276 mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU0,
277 (uint64_t) plat_secondary_cpus_bl31_entry >> 2);
278 }
279
280 /* Update reset vector to 0x00 */
281 mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU1, (uint64_t) plat_secondary_cpus_bl31_entry >> 2);
282 mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU3, (uint64_t) plat_secondary_cpus_bl31_entry >> 2);
283
284 /* On all cores - temporary */
285 pchctlr_old = mmio_read_32(AGX5_PWRMGR(MPU_PCHCTLR));
286 pchctlr_new = pchctlr_old | (pch_cpu<<1);
287 mmio_write_32(AGX5_PWRMGR(MPU_PCHCTLR), pchctlr_new);
288
289 /* We will only release the target secondary CPUs */
290 /* Bit mask for each CPU BIT0-3 */
291 mmio_write_32(RSTMGR_CPUSTRELEASE_CPUx, pch_cpu);
292 }
293
bl31_plat_reset_secondary_cpu(unsigned int cpu_id)294 void bl31_plat_reset_secondary_cpu(unsigned int cpu_id)
295 {
296 uint32_t mask = 0x1;
297 uint32_t value = 0;
298 uint32_t pwrctlr_addr = 0;
299 uint32_t pwrstat_addr = 0;
300 uint32_t ret = 0;
301
302 mask <<= cpu_id;
303
304 switch (cpu_id) {
305 case 0:
306 pwrctlr_addr = AGX5_PWRMGR(CPU_PWRCTLR0);
307 pwrstat_addr = AGX5_PWRMGR(CPU_PWRSTAT0);
308 break;
309 case 1:
310 pwrctlr_addr = AGX5_PWRMGR(CPU_PWRCTLR1);
311 pwrstat_addr = AGX5_PWRMGR(CPU_PWRSTAT1);
312 break;
313 case 2:
314 pwrctlr_addr = AGX5_PWRMGR(CPU_PWRCTLR2);
315 pwrstat_addr = AGX5_PWRMGR(CPU_PWRSTAT2);
316 break;
317 case 3:
318 pwrctlr_addr = AGX5_PWRMGR(CPU_PWRCTLR3);
319 pwrstat_addr = AGX5_PWRMGR(CPU_PWRSTAT3);
320 break;
321 default:
322 ERROR("BL31: %s: Invalid CPU ID\n", __func__);
323 break;
324 }
325
326 /* PSTATE = 0, RUN_PCH = 1 */
327 mmio_write_32(pwrctlr_addr, AGX5_PWRMGR_CPU_RUN_PCH(1));
328
329 /* Poll for CPU OFF */
330 SOCFPGA_POLL(!((AGX5_PWRMGR_CPU_RUN_PCH(
331 mmio_read_32(pwrstat_addr)) == 0) ||
332 (AGX5_PWRMGR_CPU_SINGLE_FSM_STATE(
333 mmio_read_32(pwrstat_addr)) != 0)),
334 AGX5_PWRMGR_CPU_POLL_COUNT,
335 AGX5_PWRMGR_CPU_DELAY_10_US, udelay, ret);
336
337 if (ret != 0)
338 ERROR("BL31: %s: Timeout when polling for CPU OFF\n", __func__);
339
340 /* Performs the warm reset CPUx */
341 value = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_WARM_9));
342 mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_WARM_9), value | mask);
343 udelay(1);
344 mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_WARM_9), value & ~mask);
345 udelay(1);
346
347 /* Power up sequence */
348 mmio_write_32(pwrctlr_addr, AGX5_PWRMGR_CPU_PROG_CPU_ON_STATE |
349 AGX5_PWRMGR_CPU_RUN_PCH(1));
350
351 /* Poll for CPU ON */
352 SOCFPGA_POLL(!((AGX5_PWRMGR_CPU_RUN_PCH(
353 mmio_read_32(pwrstat_addr)) == 0) ||
354 AGX5_PWRMGR_CPU_SINGLE_FSM_STATE(
355 mmio_read_32(pwrstat_addr)) == 0),
356 AGX5_PWRMGR_CPU_POLL_COUNT,
357 AGX5_PWRMGR_CPU_DELAY_10_US, udelay, ret);
358 if (ret !=0 )
359 ERROR("BL31: %s: Timeout when polling for CPU ON\n", __func__);
360 }
361
bl31_plat_set_secondary_cpu_off(void)362 void bl31_plat_set_secondary_cpu_off(void)
363 {
364 unsigned int pch_cpu = 0x00;
365 unsigned int pch_cpu_off = 0x00;
366 unsigned int cpu_id = plat_my_core_pos();
367
368 pch_cpu_off = 1 << cpu_id;
369
370 pch_cpu = mmio_read_32(AGX5_PWRMGR(MPU_PCHCTLR));
371 pch_cpu = pch_cpu & ~(pch_cpu_off << 1);
372
373 mmio_write_32(AGX5_PWRMGR(MPU_PCHCTLR), pch_cpu);
374 }
375
setup_clusterectlr_el1(void)376 void setup_clusterectlr_el1(void)
377 {
378 uint64_t value = 0;
379
380 /* Read CLUSTERECTLR_EL1 */
381 asm volatile("mrs %0, S3_0_C15_C3_4" : "=r"(value));
382
383 /* Disable broadcasting atomics */
384 value |= 0x80; /* set bit 7 */
385 /* Disable sending data with clean evicts */
386 value &= 0xFFFFBFFF; /* Mask out bit 14 */
387
388 /* Write CLUSTERECTLR_EL1 */
389 asm volatile("msr S3_0_C15_C3_4, %0" :: "r"(value));
390 }
391
bl31_plat_runtime_setup(void)392 void bl31_plat_runtime_setup(void)
393 {
394 /* Dummy override function. */
395 }
396
bl31_plat_enable_mmu(uint32_t flags)397 void bl31_plat_enable_mmu(uint32_t flags)
398 {
399 /* TODO: Enable mmu when needed */
400 }
401