1 /*
2 * Copyright 2025 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <stdbool.h>
9
10 #include "../drivers/arm/gic/v3/gicv3_private.h"
11
12 #include <arch_helpers.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <context.h>
16
17 #include <drivers/arm/gic.h>
18 #include <drivers/console.h>
19 #include <drivers/generic_delay_timer.h>
20 #include <lib/el3_runtime/context_mgmt.h>
21 #include <lib/mmio.h>
22 #include <lib/xlat_tables/xlat_tables_v2.h>
23 #include <plat/common/platform.h>
24
25 #include <ele_api.h>
26 #include <imx8_lpuart.h>
27 #include <imx_plat_common.h>
28 #include <imx_scmi_client.h>
29 #include <plat_imx8.h>
30 #include <platform_def.h>
31
32 extern gicv3_driver_data_t gic_data;
33
34 static entry_point_info_t bl32_image_ep_info;
35 static entry_point_info_t bl33_image_ep_info;
36
37 extern const mmap_region_t imx_mmap[];
38 extern uintptr_t gpio_base[GPIO_NUM];
39
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)40 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
41 u_register_t arg2, u_register_t arg3)
42 {
43 static console_t console;
44
45 console_lpuart_register(IMX_LPUART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
46 IMX_CONSOLE_BAUDRATE, &console);
47
48 /* this console is only used for boot stage */
49 console_set_scope(&console, CONSOLE_FLAG_BOOT);
50
51 /*
52 * tell bl3-1 where the non-secure software image is located
53 * and the entry state information.
54 */
55 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
56 bl33_image_ep_info.spsr = plat_get_spsr_for_bl33_entry();
57 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
58
59 #if defined(SPD_opteed) || defined(SPD_trusty)
60 /* Populate entry point information for BL32 */
61 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
62 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
63 bl32_image_ep_info.pc = BL32_BASE;
64 bl32_image_ep_info.spsr = 0;
65
66 /* Pass TEE base and size to bl33 */
67 bl33_image_ep_info.args.arg1 = BL32_BASE;
68 bl33_image_ep_info.args.arg2 = BL32_SIZE;
69
70 #ifdef SPD_trusty
71 bl32_image_ep_info.args.arg0 = BL32_SIZE;
72 bl32_image_ep_info.args.arg1 = BL32_BASE;
73 #else
74 /* Make sure memory is clean */
75 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0);
76 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
77 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
78 #endif
79 #endif
80 }
81
bl31_plat_arch_setup(void)82 void bl31_plat_arch_setup(void)
83 {
84 /* Assign all the GPIO pins to non-secure world by default */
85 for (unsigned int i = 0U; i < GPIO_NUM; i++) {
86 mmio_write_32(gpio_base[i] + 0x10, 0xffffffff);
87 mmio_write_32(gpio_base[i] + 0x14, 0x3);
88 mmio_write_32(gpio_base[i] + 0x18, 0xffffffff);
89 mmio_write_32(gpio_base[i] + 0x1c, 0x3);
90 }
91
92 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE),
93 MT_MEMORY | MT_RW | MT_SECURE);
94 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE),
95 MT_MEMORY | MT_RO | MT_SECURE);
96
97 #ifdef SPD_trusty
98 mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW);
99 #endif
100 mmap_add(imx_mmap);
101
102 init_xlat_tables();
103
104 enable_mmu_el3(0);
105 }
106
bl31_platform_setup(void)107 void bl31_platform_setup(void)
108 {
109 uint32_t gicr_ctlr;
110 uintptr_t gicr_base;
111
112 generic_delay_timer_init();
113
114 /*
115 * In order to apply platform specific gic workaround, the
116 * gicv3_driver_data need to be initialized, the 'USE_GIC_DRIVER'
117 * will init it again, it should be fine.
118 */
119 gic_data.gicr_base = PLAT_ARM_GICR_BASE;
120 gicv3_driver_init(&gic_data);
121 /* Ensure to mark the core as asleep, required for reset case. */
122 gic_cpuif_disable(plat_my_core_pos());
123 /* Clear LPIs */
124 for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++) {
125 gicr_base = gicv3_driver_data->rdistif_base_addrs[i];
126 gicr_ctlr = gicr_read_ctlr(gicr_base);
127 gicr_write_ctlr(gicr_base, gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT));
128 }
129
130 /* get soc info */
131 ele_get_soc_info();
132
133 #if HAS_XSPI_SUPPORT
134 /* i.MX94 specific */
135 ele_release_gmid();
136 #endif
137
138 plat_imx9_scmi_setup();
139 }
140
bl31_plat_get_next_image_ep_info(unsigned int type)141 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
142 {
143 if (type == NON_SECURE) {
144 return &bl33_image_ep_info;
145 }
146
147 if (type == SECURE) {
148 return &bl32_image_ep_info;
149 }
150
151 return NULL;
152 }
153
plat_get_syscnt_freq2(void)154 unsigned int plat_get_syscnt_freq2(void)
155 {
156 return COUNTER_FREQUENCY;
157 }
158
159 #ifdef SPD_trusty
plat_trusty_set_boot_args(aapcs64_params_t * args)160 void plat_trusty_set_boot_args(aapcs64_params_t *args)
161 {
162 args->arg0 = BL32_SIZE;
163 args->arg1 = BL32_BASE;
164 args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
165 }
166 #endif
167