xref: /rk3399_ARM-atf/plat/arm/board/fvp/fvp_security.c (revision 430f246e58d146949d399d72294f56403672bee0)
1 /*
2  * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <plat/arm/common/arm_config.h>
8 #include <plat/arm/common/plat_arm.h>
9 #include <platform_def.h>
10 
11 /*
12  * We assume that all security programming is done by the primary core.
13  */
plat_arm_security_setup(void)14 void plat_arm_security_setup(void)
15 {
16 	/*
17 	 * The Base FVP has a TrustZone address space controller.
18 	 *
19 	 * If the platform had additional peripheral specific security
20 	 * configurations, those would be configured here.
21 	 */
22 
23 	const arm_tzc_regions_info_t fvp_tzc_regions[] = {
24 		ARM_TZC_REGIONS_DEF,
25 #if ENABLE_RMM
26 		{ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END,
27 		 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS},
28 #else
29 		{FVP_DRAM3_BASE, FVP_DRAM3_END,
30 		 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS},
31 		{FVP_DRAM4_BASE, FVP_DRAM4_END,
32 		 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS},
33 		{FVP_DRAM5_BASE, FVP_DRAM5_END,
34 		 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS},
35 		{FVP_DRAM6_BASE, FVP_DRAM6_END,
36 		 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS},
37 #endif
38 		{0}
39 	};
40 
41 	if ((get_arm_config()->flags & ARM_CONFIG_HAS_TZC) != 0U)
42 		arm_tzc400_setup(PLAT_ARM_TZC_BASE, fvp_tzc_regions);
43 }
44