1 /*
2 * Copyright (c) 2015-2026, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <platform_def.h>
9
10 #include <common/debug.h>
11 #include <common/interrupt_props.h>
12 #include <drivers/arm/gicv3.h>
13 #include <fconf_hw_config_getter.h>
14 #include <lib/utils.h>
15 #include <plat/arm/common/plat_arm.h>
16 #include <plat/arm/common/fconf_sec_intr_config.h>
17 #include <plat/common/platform.h>
18
19 #if FVP_GICR_REGION_PROTECTION
20 /* To indicate GICR region of the core initialized as Read-Write */
21 static bool fvp_gicr_rw_region_init[PLATFORM_CORE_COUNT] = {false};
22 #endif /* FVP_GICR_REGION_PROTECTION */
23
24 static const interrupt_prop_t __unused fvp_interrupt_props[] = {
25 PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
26 PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0)
27 };
28
29 extern gicv3_driver_data_t gic_data;
30
31 /******************************************************************************
32 * This function gets called per core to make its redistributor frame rw
33 *****************************************************************************/
fvp_gicv3_make_rdistrif_rw(unsigned int core_pos)34 void fvp_gicv3_make_rdistrif_rw(unsigned int core_pos)
35 {
36 #if FVP_GICR_REGION_PROTECTION
37 /* Make the redistributor frame RW if it is not done previously */
38 if (fvp_gicr_rw_region_init[core_pos] != true) {
39 int ret = xlat_change_mem_attributes(BASE_GICR_BASE +
40 (core_pos * BASE_GICR_SIZE),
41 BASE_GICR_SIZE,
42 MT_EXECUTE_NEVER |
43 MT_DEVICE | MT_RW |
44 MT_SECURE);
45
46 if (ret != 0) {
47 ERROR("Failed to make redistributor frame \
48 read write = %d\n", ret);
49 panic();
50 } else {
51 fvp_gicr_rw_region_init[core_pos] = true;
52 }
53 }
54 #else
55 return;
56 #endif /* FVP_GICR_REGION_PROTECTION */
57 }
58
fvp_gic_driver_pre_init(void)59 void fvp_gic_driver_pre_init(void)
60 {
61 /* FCONF won't be used in these cases, so we couldn't do this */
62 #if !(RESET_TO_BL31 || RESET_TO_SP_MIN || RESET_TO_BL2)
63 /*
64 * Get GICD and GICR base addressed through FCONF APIs.
65 * FCONF is not supported in BL32 for FVP.
66 */
67 #if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \
68 (defined(__aarch64__) && defined(IMAGE_BL31))
69 gic_data.gicd_base = (uintptr_t)FCONF_GET_PROPERTY(hw_config,
70 gicv3_config,
71 gicd_base);
72 arm_gicr_base_addrs[0] = FCONF_GET_PROPERTY(hw_config, gicv3_config,
73 gicr_base);
74 #if SEC_INT_DESC_IN_FCONF
75 gic_data.interrupt_props = FCONF_GET_PROPERTY(hw_config,
76 sec_intr_prop, descriptor);
77 gic_data.interrupt_props_num = FCONF_GET_PROPERTY(hw_config,
78 sec_intr_prop, count);
79 #else
80 gic_data.interrupt_props = fvp_interrupt_props;
81 gic_data.interrupt_props_num = ARRAY_SIZE(fvp_interrupt_props);
82 #endif
83 #else
84 gic_data.gicd_base = PLAT_ARM_GICD_BASE;
85 arm_gicr_base_addrs[0] = PLAT_ARM_GICR_BASE;
86 gic_data.interrupt_props = fvp_interrupt_props;
87 gic_data.interrupt_props_num = ARRAY_SIZE(fvp_interrupt_props);
88 #endif
89 #endif /* !(RESET_TO_BL31 || RESET_TO_SP_MIN || RESET_TO_BL2) */
90 gic_set_gicr_frames(arm_gicr_base_addrs);
91 }
92