1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Rockchip MIPI CSI2 DPHY driver 4 * 5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd. 6 */ 7 8 #ifndef _PHY_ROCKCHIP_CSI2_DPHY_COMMON_H_ 9 #define _PHY_ROCKCHIP_CSI2_DPHY_COMMON_H_ 10 11 #include <linux/rk-camera-module.h> 12 #include <linux/rkcif-config.h> 13 14 #define PHY_MAX 16 15 #define MAX_DEV_NAME_LEN 32 16 17 #define MAX_SAMSUNG_PHY_NUM 2 18 19 #define MAX_INNO_PHY_NUM 2 20 21 /* add new chip id in tail by time order */ 22 enum csi2_dphy_chip_id { 23 CHIP_ID_RK3568 = 0x0, 24 CHIP_ID_RK3588 = 0x1, 25 CHIP_ID_RK3588_DCPHY = 0x2, 26 CHIP_ID_RV1106 = 0x3, 27 CHIP_ID_RK3562 = 0x4, 28 }; 29 30 enum csi2_dphy_rx_pads { 31 CSI2_DPHY_RX_PAD_SINK = 0, 32 CSI2_DPHY_RX_PAD_SOURCE, 33 CSI2_DPHY_RX_PADS_NUM, 34 }; 35 36 enum csi2_dphy_lane_mode { 37 LANE_MODE_UNDEF = 0x0, 38 LANE_MODE_FULL, 39 LANE_MODE_SPLIT, 40 }; 41 42 struct grf_reg { 43 u32 offset; 44 u32 mask; 45 u32 shift; 46 }; 47 48 struct csi2dphy_reg { 49 u32 offset; 50 }; 51 52 #define MAX_DPHY_SENSORS (2) 53 #define MAX_NUM_CSI2_DPHY (0x2) 54 55 struct csi2_sensor { 56 struct v4l2_subdev *sd; 57 struct v4l2_mbus_config mbus; 58 struct v4l2_mbus_framefmt format; 59 int lanes; 60 }; 61 62 struct csi2_dphy_hw; 63 struct samsung_mipi_dcphy; 64 65 struct dphy_drv_data { 66 const char dev_name[MAX_DEV_NAME_LEN]; 67 enum csi2_dphy_chip_id chip_id; 68 char num_inno_phy; 69 char num_samsung_phy; 70 }; 71 72 struct csi2_dphy { 73 struct device *dev; 74 struct list_head list; 75 struct csi2_dphy_hw *dphy_hw; 76 struct csi2_dphy_hw *dphy_hw_group[MAX_INNO_PHY_NUM]; 77 struct samsung_mipi_dcphy *samsung_phy; 78 struct samsung_mipi_dcphy *samsung_phy_group[MAX_SAMSUNG_PHY_NUM]; 79 struct v4l2_async_notifier notifier; 80 struct v4l2_subdev sd; 81 struct mutex mutex; /* lock for updating protection */ 82 struct media_pad pads[CSI2_DPHY_RX_PADS_NUM]; 83 struct csi2_sensor sensors[MAX_DPHY_SENSORS]; 84 u64 data_rate_mbps; 85 int num_sensors; 86 int phy_index; 87 struct rkcif_csi_info csi_info; 88 void *phy_hw[RKMODULE_MULTI_DEV_NUM]; 89 bool is_streaming; 90 int lane_mode; 91 const struct dphy_drv_data *drv_data; 92 struct rkmodule_csi_dphy_param dphy_param; 93 }; 94 95 struct dphy_hw_drv_data { 96 const struct hsfreq_range *hsfreq_ranges; 97 int num_hsfreq_ranges; 98 const struct hsfreq_range *hsfreq_ranges_cphy; 99 int num_hsfreq_ranges_cphy; 100 const struct grf_reg *grf_regs; 101 const struct txrx_reg *txrx_regs; 102 const struct csi2dphy_reg *csi2dphy_regs; 103 void (*individual_init)(struct csi2_dphy_hw *hw); 104 int (*stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); 105 int (*stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); 106 enum csi2_dphy_chip_id chip_id; 107 }; 108 109 struct csi2_dphy_hw { 110 struct device *dev; 111 struct regmap *regmap_grf; 112 struct regmap *regmap_sys_grf; 113 const struct grf_reg *grf_regs; 114 const struct txrx_reg *txrx_regs; 115 const struct csi2dphy_reg *csi2dphy_regs; 116 const struct dphy_hw_drv_data *drv_data; 117 void __iomem *hw_base_addr; 118 struct clk_bulk_data *clks_bulk; 119 struct reset_control *rsts_bulk; 120 struct csi2_dphy *dphy_dev[MAX_NUM_CSI2_DPHY]; 121 struct v4l2_subdev sd; 122 struct mutex mutex; /* lock for updating protection */ 123 atomic_t stream_cnt; 124 int num_clks; 125 int num_sensors; 126 int dphy_dev_num; 127 enum csi2_dphy_lane_mode lane_mode; 128 129 int (*stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); 130 int (*stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); 131 int (*ttl_mode_enable)(struct csi2_dphy_hw *hw); 132 void (*ttl_mode_disable)(struct csi2_dphy_hw *hw); 133 }; 134 135 int rockchip_csi2_dphy_hw_init(void); 136 int rockchip_csi2_dphy_init(void); 137 138 #endif 139